JPS55145356A - Fabricating method of semiconductor device - Google Patents

Fabricating method of semiconductor device

Info

Publication number
JPS55145356A
JPS55145356A JP5365579A JP5365579A JPS55145356A JP S55145356 A JPS55145356 A JP S55145356A JP 5365579 A JP5365579 A JP 5365579A JP 5365579 A JP5365579 A JP 5365579A JP S55145356 A JPS55145356 A JP S55145356A
Authority
JP
Japan
Prior art keywords
film
phosphorus
semiconductor device
wiring metal
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5365579A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Hirakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP5365579A priority Critical patent/JPS55145356A/en
Publication of JPS55145356A publication Critical patent/JPS55145356A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the disconnection and cracks of a wiring metal in a semiconductor device by forming a CVD SiO2 film as an interlayer insulating film, then forming high density phosphorus glass on the surface of the film by a phosphorus treatment and varying stepwise shape of the film. CONSTITUTION:A field insulating film 302, a gate oxide film 304, a gate metal 305, the first layer wiring metal 306 and a diffused layer 303 are sequentially formed on a silicon substrate 301. Then, a CVD SiO2 film 307 is formed as an interlayer insulating film, treated with phosphorus to diffuse the phosphorus in the film 307, and thus formed with a phosphorus glass layer 308. Thereafter, the second layer wiring metal 309 is formed thereon.
JP5365579A 1979-05-01 1979-05-01 Fabricating method of semiconductor device Pending JPS55145356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5365579A JPS55145356A (en) 1979-05-01 1979-05-01 Fabricating method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5365579A JPS55145356A (en) 1979-05-01 1979-05-01 Fabricating method of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55145356A true JPS55145356A (en) 1980-11-12

Family

ID=12948876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5365579A Pending JPS55145356A (en) 1979-05-01 1979-05-01 Fabricating method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55145356A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6425551A (en) * 1987-07-22 1989-01-27 Toshiba Corp Semiconductor device
US7160768B2 (en) 2003-07-10 2007-01-09 Seiko Epson Corporation Method of manufacturing electronic device and method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6425551A (en) * 1987-07-22 1989-01-27 Toshiba Corp Semiconductor device
US7160768B2 (en) 2003-07-10 2007-01-09 Seiko Epson Corporation Method of manufacturing electronic device and method of manufacturing semiconductor device

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