JPS54156492A - Manufacture for integrated circuit device - Google Patents

Manufacture for integrated circuit device

Info

Publication number
JPS54156492A
JPS54156492A JP6525578A JP6525578A JPS54156492A JP S54156492 A JPS54156492 A JP S54156492A JP 6525578 A JP6525578 A JP 6525578A JP 6525578 A JP6525578 A JP 6525578A JP S54156492 A JPS54156492 A JP S54156492A
Authority
JP
Japan
Prior art keywords
film
under
psg
sio
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6525578A
Other languages
Japanese (ja)
Inventor
Kimiyoshi Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6525578A priority Critical patent/JPS54156492A/en
Publication of JPS54156492A publication Critical patent/JPS54156492A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To form the diffusion layer in suitable depth with an arbitrary condition without being affected with the smoothness, by making smooth the SiO2 film surface including P in high concentration.
CONSTITUTION: On the oxide films 3 and 4 of the P type Si substrate 1, the gate electrode 4 and wiring layer 5 by polycrystal Si are formed selectively, and it is covered with polycrystal Si 6. Succeedingly, it is covered with PSG 7 of high concentration to avoid unevenness of surface by liquidifying through the process under N2 at 1000°C. In this case, P is diffused in the layers 4,5,6 and they are changed to the conductive layers. P is not diffused to the substrate under the films 6,5',4'. Succeedingly, the surface of the films 4',5',6 are oxided with wet oxidation to for SiO film under PSG 7. Simultaneously, the film 6 is completely converted into SiO2 form the film 3' in continuity with the film 3. Next, processing is made under N2 at 1000°C to form the film 3' with PSG, then it is processed under N2 at 920°C, and the phosphorus diffusion layer 8 is formed by easily controlling the concentration and depth.
COPYRIGHT: (C)1979,JPO&Japio
JP6525578A 1978-05-30 1978-05-30 Manufacture for integrated circuit device Pending JPS54156492A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6525578A JPS54156492A (en) 1978-05-30 1978-05-30 Manufacture for integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6525578A JPS54156492A (en) 1978-05-30 1978-05-30 Manufacture for integrated circuit device

Publications (1)

Publication Number Publication Date
JPS54156492A true JPS54156492A (en) 1979-12-10

Family

ID=13281609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6525578A Pending JPS54156492A (en) 1978-05-30 1978-05-30 Manufacture for integrated circuit device

Country Status (1)

Country Link
JP (1) JPS54156492A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6439064A (en) * 1987-08-04 1989-02-09 Mitsubishi Electric Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6439064A (en) * 1987-08-04 1989-02-09 Mitsubishi Electric Corp Semiconductor device

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