JPS5664431A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5664431A
JPS5664431A JP14104879A JP14104879A JPS5664431A JP S5664431 A JPS5664431 A JP S5664431A JP 14104879 A JP14104879 A JP 14104879A JP 14104879 A JP14104879 A JP 14104879A JP S5664431 A JPS5664431 A JP S5664431A
Authority
JP
Japan
Prior art keywords
organic polymer
impurity
type
substrate
desired density
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14104879A
Other languages
Japanese (ja)
Inventor
Hideaki Ozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14104879A priority Critical patent/JPS5664431A/en
Publication of JPS5664431A publication Critical patent/JPS5664431A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE:To obtain an impurity implanted layer having a desired density with preferable reproducibility with a conductive impurity mixed in an organic polymer as a diffusion source. CONSTITUTION:An Si3N4 mask 4 is formed through an SiO2 film 3 on a P type Si substrate 1 formed with an MOS transistor forming region 2 thereon. An organic polymer 5 such as a polyvinyl alcohol or the like containing 1ppm by weight of P type impurity in the form chemically combined with an oxide or organic polymer is rotatably coated thereon. Subsequently, the organic polymer is exposed with O2 plasma and is thus completely ashed, and the P type impurity 6 is precipitated on the Si substrate. Then, it is wet oxidized, a field oxide film 7 is formed on the periphery of the region 2 covered with the mask 4, and a P type channel-cut layer 8 is formed under the oxide film 7 with the imopurity 6 as a thermal diffusion source. According to this configuration the impurity implanted layer having desired density can be formed without irregularity and with preferable reproducibility, the characteristics of the semiconductor device can be equalized, and the yield of the device can be improved.
JP14104879A 1979-10-31 1979-10-31 Manufacture of semiconductor device Pending JPS5664431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14104879A JPS5664431A (en) 1979-10-31 1979-10-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14104879A JPS5664431A (en) 1979-10-31 1979-10-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5664431A true JPS5664431A (en) 1981-06-01

Family

ID=15283030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14104879A Pending JPS5664431A (en) 1979-10-31 1979-10-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5664431A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62239571A (en) * 1986-04-10 1987-10-20 Nec Corp Manufacture of semiconductor memory
JPH01135017A (en) * 1987-11-20 1989-05-26 Fujitsu Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62239571A (en) * 1986-04-10 1987-10-20 Nec Corp Manufacture of semiconductor memory
JPH01135017A (en) * 1987-11-20 1989-05-26 Fujitsu Ltd Manufacture of semiconductor device

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