JPS5640276A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5640276A
JPS5640276A JP11646779A JP11646779A JPS5640276A JP S5640276 A JPS5640276 A JP S5640276A JP 11646779 A JP11646779 A JP 11646779A JP 11646779 A JP11646779 A JP 11646779A JP S5640276 A JPS5640276 A JP S5640276A
Authority
JP
Japan
Prior art keywords
region
window
layer
emitter
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11646779A
Other languages
Japanese (ja)
Other versions
JPS6346584B2 (en
Inventor
Tomio Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11646779A priority Critical patent/JPS5640276A/en
Publication of JPS5640276A publication Critical patent/JPS5640276A/en
Publication of JPS6346584B2 publication Critical patent/JPS6346584B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To prevent a short-circuit between the emitter and base of a semiconductor by coating the side surfaces of a polycrystalline Si layer containing impurities provided on a semiconductor substrate with a SiO2 film before forming an emitter region by using the Si layer as a diffusion source. CONSTITUTION:On an Si substrate 1, a shallow base region 2 and an annular deep graft-base region 3 surrounding the region 2 and contacting with its circumference are formed by diffusion. The whole surface is coated with an SiO2 film 4, and a window 5 for impurity diffusion is made corresponding to an emitter region 8 to be provided in the region 2. Then, in the window 5, a polycrystalline Si layer 6 containing impurities is formed covering the film 4 on the circumference of the window 5, and coated with a CVD SiO2 film 7. The whole surface including the film 7 is also coated with a CVD SiO2 film 13 to cover the side surface of the Si layer 6. At the same time, the inpurities in the Si layer 6 is diffused to produce an emitter region 8 in the region 2. A window 9 is made over the region 8, and a window 10 on the region 3. Then an emitter lead electrode 11 is provided in the window 9, and a base lead electrode 12 in the window 10.
JP11646779A 1979-09-11 1979-09-11 Preparation of semiconductor device Granted JPS5640276A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11646779A JPS5640276A (en) 1979-09-11 1979-09-11 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11646779A JPS5640276A (en) 1979-09-11 1979-09-11 Preparation of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5640276A true JPS5640276A (en) 1981-04-16
JPS6346584B2 JPS6346584B2 (en) 1988-09-16

Family

ID=14687818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11646779A Granted JPS5640276A (en) 1979-09-11 1979-09-11 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5640276A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0455991U (en) * 1990-09-19 1992-05-13
JPH0455990U (en) * 1990-09-19 1992-05-13

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504984A (en) * 1973-05-16 1975-01-20
JPS5010578A (en) * 1973-05-24 1975-02-03
JPS51130174A (en) * 1975-05-06 1976-11-12 Matsushita Electric Ind Co Ltd Semiconductor device process
JPS5482177A (en) * 1977-12-14 1979-06-30 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its manufacture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504984A (en) * 1973-05-16 1975-01-20
JPS5010578A (en) * 1973-05-24 1975-02-03
JPS51130174A (en) * 1975-05-06 1976-11-12 Matsushita Electric Ind Co Ltd Semiconductor device process
JPS5482177A (en) * 1977-12-14 1979-06-30 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its manufacture

Also Published As

Publication number Publication date
JPS6346584B2 (en) 1988-09-16

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