JPS5580334A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5580334A
JPS5580334A JP15393178A JP15393178A JPS5580334A JP S5580334 A JPS5580334 A JP S5580334A JP 15393178 A JP15393178 A JP 15393178A JP 15393178 A JP15393178 A JP 15393178A JP S5580334 A JPS5580334 A JP S5580334A
Authority
JP
Japan
Prior art keywords
film
regions
sio
mask
windows
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15393178A
Other languages
Japanese (ja)
Inventor
Shigero Kuninobu
Atsushi Ueno
Takeshi Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15393178A priority Critical patent/JPS5580334A/en
Publication of JPS5580334A publication Critical patent/JPS5580334A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To obtain a small contact of 2W3μm2 and increase the density of IC by the method such that when a polycrystalline Si conducting film is formed on source, drain and gate regions provided on a semiconductor substrate, their heights are aligned.
CONSTITUTION: SiO2 film 12 and Si3N4 film 13 are laminated on p-type Si substrate 11, and mask 14 is formed by retaining those on the element active regions only. Next, thick field SiO2 film 16 is formed on both sides in substrate 11 with mask 14 aligned with the surface. Mask 14 is made into gate SiO2 film 17, and windows 18 and 19 are provided on both ends. Then, the entire surface is covered with n-type polycrystalline Si film 20. Subsequently, by heat treatment, n-type source and drain regions 12 and 22 are diffused into windows 18 and 19. Film 20 on a part of these regions and on the central region of film 17 is retained as conducting films 23, 24 and 25. Next, by injecting ions, shallow transition regions 27 and 28 are formed in regions 21 and 22. The entire surface is covered with SiO2 film 29, and by opening windows 30 and 31, metal wiring layer 32 is fitted on films 24 and 25.
COPYRIGHT: (C)1980,JPO&Japio
JP15393178A 1978-12-12 1978-12-12 Manufacture of semiconductor device Pending JPS5580334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15393178A JPS5580334A (en) 1978-12-12 1978-12-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15393178A JPS5580334A (en) 1978-12-12 1978-12-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5580334A true JPS5580334A (en) 1980-06-17

Family

ID=15573203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15393178A Pending JPS5580334A (en) 1978-12-12 1978-12-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5580334A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50113177A (en) * 1974-02-14 1975-09-05

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50113177A (en) * 1974-02-14 1975-09-05

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