JPS6449270A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6449270A JPS6449270A JP20523887A JP20523887A JPS6449270A JP S6449270 A JPS6449270 A JP S6449270A JP 20523887 A JP20523887 A JP 20523887A JP 20523887 A JP20523887 A JP 20523887A JP S6449270 A JPS6449270 A JP S6449270A
- Authority
- JP
- Japan
- Prior art keywords
- psg
- film
- flattened
- drain
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000005360 phosphosilicate glass Substances 0.000 abstract 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
PURPOSE:To easily form a wiring part on a PSG film and to form the device characteristic of a desired value by a method wherein, when a MOSFET is to be manufactured, a PSG interlayer insulating film is melted and flattened and, after that, a source and a drain are formed by implanting an impurity. CONSTITUTION:An SiO2 film 17 is formed on an Si substrate 16; an island- shaped single-crystal Si layer (an SOI island) 19 is formed thereon. A gate insulating film 11 and a gate electrode 12 are formed on the surface of the SOI island 19; after that, a PSG (phospho-silicate glass) insulating film 13 is deposited on the whole surface of the substrate. A contact hole is made in the PSG film 13; after that, the assembly is annealed in an atmosphere of N2 at 1050 deg.C for 30 minutes; the PSG film is melted; the surface is flattened. Then, ions of As are implanted via the contact hole; a source 14 and a drain 15 are formed. Then, an Al wiring part 22 is formed. Because the PSG film is flattened, a disconnection of the Al wiring part can be prevented. After the formation of the source and the drain, a high-temperature process is not executed; accordingly, a device characteristic is not changed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20523887A JPS6449270A (en) | 1987-08-20 | 1987-08-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20523887A JPS6449270A (en) | 1987-08-20 | 1987-08-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6449270A true JPS6449270A (en) | 1989-02-23 |
Family
ID=16503690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20523887A Pending JPS6449270A (en) | 1987-08-20 | 1987-08-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6449270A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013016783A (en) * | 2011-06-10 | 2013-01-24 | Semiconductor Energy Lab Co Ltd | Manufacturing method of semiconductor device |
| JP2014082389A (en) * | 2012-10-17 | 2014-05-08 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacturing method of the same |
-
1987
- 1987-08-20 JP JP20523887A patent/JPS6449270A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013016783A (en) * | 2011-06-10 | 2013-01-24 | Semiconductor Energy Lab Co Ltd | Manufacturing method of semiconductor device |
| JP2014082389A (en) * | 2012-10-17 | 2014-05-08 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacturing method of the same |
| US9852904B2 (en) | 2012-10-17 | 2017-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
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