JPS61216341A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61216341A JPS61216341A JP5688585A JP5688585A JPS61216341A JP S61216341 A JPS61216341 A JP S61216341A JP 5688585 A JP5688585 A JP 5688585A JP 5688585 A JP5688585 A JP 5688585A JP S61216341 A JPS61216341 A JP S61216341A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- etching
- film
- silica
- films
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上のオI」用分野〕
本発明は半導体基板表面の平滑化技術を改善した。半導
体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field] The present invention improves the technique for smoothing the surface of a semiconductor substrate. The present invention relates to a method for manufacturing a semiconductor device.
従来、半導体装置の製造方法において、バターニングさ
れた多結晶シリコン膜上に2層、又は、それ以上の絶縁
膜を形成した後、トランジスタ回W11t−得るために
、この絶縁膜上にアルミニウム配線全形成する場合があ
る。Conventionally, in a method for manufacturing a semiconductor device, after forming two or more insulating films on a patterned polycrystalline silicon film, aluminum wiring is entirely formed on this insulating film in order to obtain a transistor circuit W11t-. may form.
第2図はかかる従来の半導体装置の一例を示す断面図で
ある。半導体基板l上に絶縁膜2を介して多結晶シリコ
ン膜3が形成バターニングされ、その上にさらに絶縁膜
4が形成され、その表面にアルミニウム配線7が形成さ
れる。FIG. 2 is a sectional view showing an example of such a conventional semiconductor device. A polycrystalline silicon film 3 is formed and patterned on a semiconductor substrate l via an insulating film 2, an insulating film 4 is further formed on the polycrystalline silicon film 3, and an aluminum wiring 7 is formed on the surface thereof.
このような従来の製造方法によると、第2図に示すよう
に、多結晶シリコン膜パターン上の段部の急峻な部分を
アルミニウム配線が横切ると5段差の為にアルミニウム
配線の1fTsが生じ、半導体装置の歩留低下・品質低
下を招いていた。According to such a conventional manufacturing method, as shown in FIG. 2, when an aluminum wiring crosses a steep step part on a polycrystalline silicon film pattern, 1fTs of the aluminum wiring occurs due to the 5-step difference, and the semiconductor This resulted in a decrease in yield and quality of the equipment.
更に、年々パターンの縮少化が進むKつれて。Furthermore, as the number of patterns decreases year by year.
配線の寸法及び間隔が厳しくなり、段差のある部分での
感光性樹脂の解像度がほぼ限界の領域までに達してきた
。フォトレジスト工程における解像度は平坦な部分では
まだ解像度の限界領域までKは達しておらず、半導体基
板表面の段差をなくす。The dimensions and spacing of wiring have become stricter, and the resolution of photosensitive resin in areas with steps has almost reached its limit. The resolution in the photoresist process is such that K has not yet reached the resolution limit region in flat areas, and steps on the surface of the semiconductor substrate are eliminated.
いわゆる平滑化技術が重要視されてきている。この平滑
化の為にシリカ系塗布液を厚く塗布し、半導体基板表面
の段差をなく丁方法も検討されているが、厚くするとシ
リカ系脆布膜表面にクラックを生じゃすくなシ、半導体
装置の信頼性を低下させてしまう問題を招いていた。So-called smoothing technology is becoming more important. In order to smooth this, a method of coating a silica-based coating liquid thickly to eliminate the level difference on the surface of the semiconductor substrate is being considered, but if it is thick, it will not cause cracks on the surface of the silica-based brittle film. This led to problems that reduced reliability.
従って、本発明の目的は係る問題点全解決し、半導体装
置の歩留低下・品質低下をさせる事のない半導体基板表
面の平滑化技術を改善した、半導体装置の製造方法を提
供する事にある。Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that solves all of these problems and improves the technique for smoothing the surface of a semiconductor substrate without reducing the yield or quality of the semiconductor device. .
本発明の半導体装置の製造方法は、半導体基板上のバタ
ーニングされた多結晶シリコン膜上に第1の絶縁膜を形
成する工程と、該第1の絶縁膜上にシリカ系を主成分と
する塗布液t−塗布し熱処理することにより前記第1の
絶縁膜と同等のエツチング速度比を有するシリカ系塗布
膜を形成する工程と、該シリカ系塗布膜と前記第1の絶
縁膜を同等のエツチング速度比でエツチングしそれらの
表面をはt!一様に平滑化する工程と、該平滑化された
前記シリカ系塗布膜及び前記@1の絶縁膜の表f上に第
2の絶縁膜を形成する工程とを有している。The method for manufacturing a semiconductor device of the present invention includes the steps of forming a first insulating film on a patterned polycrystalline silicon film on a semiconductor substrate; A step of forming a silica-based coating film having an etching rate equivalent to that of the first insulating film by applying a coating solution T and heat-treating the same; and etching the silica-based coating film and the first insulating film to the same extent. Etch those surfaces with a speed ratio of t! The method includes a step of uniformly smoothing the film, and a step of forming a second insulating film on the smoothed silica-based coating film and the surface f of the insulating film @1.
本発明においては、第1の絶縁膜と同等のエツチング速
度比になる様に高温処理されたシリカ系塗布膜と第1の
絶縁膜とをエツチング処理する事で、半導体基板上のシ
リカ系塗布膜及び第1の絶縁膜が平滑化される。In the present invention, the silica-based coating film on the semiconductor substrate is etched by etching the silica-based coating film and the first insulating film, which have been subjected to high temperature treatment so that the etching rate ratio is the same as that of the first insulating film. and the first insulating film is smoothed.
これによシ、従来発生していた後工程におけるアルミニ
ウム配線の段部における断*’i防止することができ、
半導体装置の歩留向上・品質向上に貢献できる6更に今
後進むであろう配線の縮少化にも対応ができる。As a result, it is possible to prevent breakage *'i at the step part of the aluminum wiring in the post-process, which conventionally occurred.
It can contribute to improving the yield and quality of semiconductor devices.6 It can also respond to the reduction in wiring that is expected to progress in the future.
次に1本発明の実施例について図面を用いて説明する。 Next, an embodiment of the present invention will be described with reference to the drawings.
第1図1al〜(elFi本発明の一実施例を説明する
為の主要工程における半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device in main steps for explaining an embodiment of the present invention.
初めIC!1図(alに示すように、半導体基板1上を
酸化処理し絶lik膜2t−形成し九後K、多結晶シリ
コン膜3のバターニング全行ない、更く絶縁膜4を形成
する。First IC! As shown in FIG. 1 (al), the semiconductor substrate 1 is oxidized to form an insulating film 2t, and then the polycrystalline silicon film 3 is completely patterned, and an insulating film 4 is formed.
次に第1図[b)K示すように、この絶縁[4上K。Next, as shown in FIG. 1 [b) K, this insulation [4 upper K].
シリカ系を主成分とする塗布液を半導体基板1表面が平
滑化される程度まで塗布し、絶縁膜4とほぼ同等のエツ
チング速度比になる様に高温処理する事によって有機物
を除去し変化せしめシリカ系塗布膜5を形成する。A coating liquid containing silica as a main component is applied to the surface of the semiconductor substrate 1 to the extent that it is smoothed, and organic matter is removed and the silica is transformed by applying high temperature treatment so that the etching rate ratio is almost the same as that of the insulating film 4. A coating film 5 is formed.
次に第1図fc)K示すように、このシリカ系塗布膜5
を、絶縁膜4とほぼ同等のエツチング速度比でエツチン
グ処m’i行ない、それらの表面をほぼ一様に平滑化す
る。Next, as shown in FIG. 1fc)K, this silica-based coating film 5
The etching process m'i is performed at substantially the same etching speed ratio as that of the insulating film 4, so that their surfaces are substantially uniformly smoothed.
次にwc1図(dK示すように、このエツチング処理に
より、多結晶シリコン膜3上の絶縁膜4が薄くなり、後
工程で絶縁膜4上に金属配線を形成した場合、多結晶シ
リコン[3と金属配線間の容量が大きくなる事、絶縁耐
圧が小さくなる又外部からの汚染等の問題を解決する意
味で、その後絶縁膜6を形成する。Next, as shown in FIG. An insulating film 6 is then formed to solve problems such as an increase in capacitance between metal wirings, a decrease in dielectric strength voltage, and contamination from the outside.
次に第1図f61に示すように、この絶縁膜6上にアル
ミニウム配417t−形成する。Next, as shown in FIG. 1 f61, an aluminum interconnect 417t- is formed on this insulating film 6.
本実施例によれば、以上説明したように、平滑化された
半導体基板(第1図(d))上におけるフォトレジスト
工程での感光性樹脂の解像度は、段部における解像度よ
シも良い方向でわり、これからの縮少パターンに対して
も対応できるし、多結晶シリコン膜3の段部のアルミニ
ウム配[7の断線を防止でき、半導体装置の歩留向上・
品質向上に貢献できる。又、従来の平滑化技術において
、シリカ系塗布液を厚く塗布する事により後の高温処理
工程で発生する表面クラックの問題も後工程のエツチン
グ処理工程でシリカ系塗布膜5の表面をエツチング処理
し、シリカ系塗布膜會薄くする事で少なくなり、半導体
装置の信頼性向上にも貢献できる。According to this embodiment, as explained above, the resolution of the photosensitive resin in the photoresist process on the smoothed semiconductor substrate (FIG. 1(d)) is better than the resolution at the stepped portion. This makes it possible to cope with future shrinking patterns, and prevents disconnection of the aluminum wiring 7 in the step part of the polycrystalline silicon film 3, improving the yield of semiconductor devices.
Can contribute to quality improvement. In addition, in the conventional smoothing technology, the problem of surface cracks that occur in the subsequent high temperature treatment process due to the thick application of the silica coating liquid can be solved by etching the surface of the silica coating film 5 in the subsequent etching treatment process. By making the silica-based coating film thinner, it can be reduced, contributing to improving the reliability of semiconductor devices.
以上、詳細説明したとお塾、本発明によれば、バターニ
ングされた多結晶シリコン膜上の第1の絶縁膜と同等の
エツチング速度比を有するシリカ塗布膜を杉皮し、この
シリカ塗布膜と第1の絶縁[−はぼ同等のエツチング速
度比でエツチングしそれらの表面をほぼ一様に:5IF
lIII化する工程を有しているので、アルニウム配線
の段部における断線や、フォトレジストの解像度の低下
を防止でき、歩留゛品質の向上し九半導体装置が得られ
る。さらに、従来のように厚いシリカ塗布膜を用いる事
がないので%表面クラックが防止でき、信頼性の向上し
た半導体装置が得られる。As described above in detail, according to the present invention, a silica coating film having the same etching rate ratio as the first insulating film on a buttered polycrystalline silicon film is coated with cedar bark, and this silica coating film and The first insulation [- is etched at approximately the same etching rate ratio and their surfaces are approximately uniform: 5IF
Since the method includes a step of converting the aluminum into aluminum, it is possible to prevent breakage at the stepped portion of the aluminum wiring and to prevent a decrease in the resolution of the photoresist, thereby improving the yield and quality of the semiconductor device. Furthermore, since a thick silica coating film is not used as in the conventional method, surface cracks can be prevented and a semiconductor device with improved reliability can be obtained.
第1図1a1〜(6)は本発明の一実施例全説明するた
めの半導体装置の主要工程における断面図、第2図は従
来例による半導体装置の断面図である。
1・・・・・・半導体基板、2・・・・・・絶縁膜、3
・・・・・・多結晶/リコン膜、4・・・・・・絶縁膜
、5・・・・・・シリカ系塗布膜、6・・・・・・絶縁
膜、7・・・・・・アルミニウム配線。
代理人 弁理士 内 原 晋、゛・亭1頂
予2団FIGS. 1A1 to 1A6 are sectional views of main steps of a semiconductor device for fully explaining an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. 1... Semiconductor substrate, 2... Insulating film, 3
...Polycrystalline/recon film, 4...Insulating film, 5...Silica-based coating film, 6...Insulating film, 7...・Aluminum wiring. Agent: Susumu Uchihara, Patent Attorney, Group 1, Group 2
Claims (1)
に第1の絶縁膜を形成する工程と、該第1の絶縁膜上に
シリカ系を主成分とする塗布液を塗布し熱処理すること
により前記第1の絶縁膜と同等のエッチング速度比を有
するシリカ系塗布膜を形成する工程と、該シリカ系塗布
膜と前記第1の絶縁膜を同等のエッチング速度比でエッ
チングしそれらの表面をほぼ一様に平滑化する工程と、
該平滑化された前記シリカ系塗布膜及び前記第1の絶縁
膜の表面上に第2の絶縁膜を形成する工程とを含む事を
特徴とする半導体装置の製造方法。The step of forming a first insulating film on a patterned polycrystalline silicon film on a semiconductor substrate, and applying a coating liquid mainly composed of silica on the first insulating film and heat-treating the first insulating film, forming a silica-based coating film having an etching rate equivalent to that of the first insulating film, and etching the silica-based coating film and the first insulating film at an equivalent etching rate ratio to make their surfaces substantially uniform; a smoothing process,
A method for manufacturing a semiconductor device, comprising the step of forming a second insulating film on the smoothed surface of the silica-based coating film and the first insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5688585A JPS61216341A (en) | 1985-03-20 | 1985-03-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5688585A JPS61216341A (en) | 1985-03-20 | 1985-03-20 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61216341A true JPS61216341A (en) | 1986-09-26 |
Family
ID=13039875
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5688585A Pending JPS61216341A (en) | 1985-03-20 | 1985-03-20 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61216341A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62250656A (en) * | 1986-04-23 | 1987-10-31 | Nec Corp | Semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57100748A (en) * | 1980-12-15 | 1982-06-23 | Toshiba Corp | Manufacture of semiconductor device |
JPS5896752A (en) * | 1981-12-03 | 1983-06-08 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS5951549A (en) * | 1982-09-17 | 1984-03-26 | Nec Corp | Manufacture of integrated circuit device |
-
1985
- 1985-03-20 JP JP5688585A patent/JPS61216341A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57100748A (en) * | 1980-12-15 | 1982-06-23 | Toshiba Corp | Manufacture of semiconductor device |
JPS5896752A (en) * | 1981-12-03 | 1983-06-08 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS5951549A (en) * | 1982-09-17 | 1984-03-26 | Nec Corp | Manufacture of integrated circuit device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62250656A (en) * | 1986-04-23 | 1987-10-31 | Nec Corp | Semiconductor device |
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