JPH02213144A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form a pattern, which is fine and large in sectional area, without being restricted by the resolution of photolithography by forming dummy layers wherein etching rate is higher the lower the layer is, and then forming a dummy pattern that the dummy layers are undercut using anisotropic etching and isotropic etching, etc. CONSTITUTION:Two or more dummy layers 2 and 3 wherein etching rate is higher the lower the layer is are formed on a semiconductor substrate 1, and then with the dummy layers 2 and 3 as masks anisotropic etching is done. Next, by isotropic etching, a dummy pattern, in the form that the dummy layers 2 and 3 are more undercut the lower the layer is, is formed. Next, it is flattened with a resist film 6 and the uppermost head exposure of the dummy layer 6 is done, and then the dummy layers 2 and 3 are all removed by etching, whereby a mask by a resist pattern is formed. Thereafter, a desired metallic pattern 6 is formed by deposition and lift-off. For example, as a material for said dummy layers 2 and 3, silicide, SiO2, SiON, SiN, alumina, or the like is suitable.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an electrode pattern.

(Prior Art) FIGS. 3(a) to 3(c) are cross-sectional views showing the manufacturing process of a conventional method called lift-off method for forming fine patterns on a semiconductor substrate. In the lift-off method, photoresist 4 is patterned into a desired pattern on semiconductor substrate 1 by photolithography (FIG. 3(a)). Next, electrode metal 5' is deposited by vacuum deposition (FIG. 3(b)). Finally, the pattern of the photoresist 4 is removed using an organic solvent such as Ascent, and at the same time, the unnecessary electrode metal 5' is removed to pattern the desired electrode 5 on the semiconductor substrate 1 (this is called a lift-off method). ) (Figure 3 (C))
.

In the above-mentioned conventional lift-off method, the pattern size is determined by the size LPR of the opening in the photoresist 4, and in photolithography using normal optical exposure, the limit is about 0.5 μm; requires expensive and highly sophisticated electron beam exposure (abbreviated as EB exposure).

On the other hand, the thickness t of the electrode 5 depends on the thickness T of the photoresist 4 in this lift-off method.
From the point of view of miniaturization, it cannot be made too thick, and the appropriate opening size is approximately LPR. Therefore, the thickness t of electric &5
However, there are limits, and it cannot be made too thick. Moreover, as the wiring becomes finer, that is, the pattern size becomes smaller, the wiring resistance increases, which deteriorates the device characteristics. Therefore, for the purpose of increasing the electrode surface area, there is a demand for making the thickness of the electrode 5 more narrow or making the electrode cross section T-shaped. It is difficult to meet these requirements such as shortening the pattern size, increasing the thickness t of the electrode 5, and the T cross section using conventional optical exposure photolithography or the foot-off method, and requires expensive equipment such as EB exposure. I had no choice but to use

[Problem to be solved by the invention]

Patterns are formed by the conventional lift-off method as described above, so the pattern line width formed by the lift-off method is limited by photolithography technology, and the cross-sectional shape of the electrodes formed is also subject to manufacturing constraints. Therefore, there was a drawback that the cross-sectional area could not be made very thick. For this reason, when used for the wiring of a semiconductor device or the gate of a field effect transistor (hereinafter abbreviated as FET), there is a problem that the wiring resistance increases with miniaturization.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a method for manufacturing a semiconductor device that can form fine patterns with large cross-sectional areas without being limited by the resolution of photolithography. shall be.

(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention is to form a dummy layer of 2M or more on a semiconductor substrate in which the etching rate is higher in the lower layers, and then use the dummy layer as a resist pattern as a mask. Anisotropic etching is performed, and then isotropic etching is performed to form a dummy pattern in which the dummy layer has a more undercut shape as it goes to the lower layer, and is then flattened with a resist film to form a dummy pattern on the top of the dummy layer. After performing cueing, only the dummy layer is completely removed by etching, a resist pattern mask is formed thereon, and then a desired metal pattern is formed by vapor deposition and lift-off.

(Function) In this invention, a multi-layered dummy layer whose etching rate is faster as it goes to the lower layer is formed, and a dummy pattern is formed by undercutting the dummy layer using anisotropic etching and isotropic etching. After the photoresist is formed, the dummy layer pattern is removed, an electrode metal is deposited, and the unnecessary electrode metal is removed together with the photoresist using a lift-off method to form a metal pattern on the semiconductor device. The pattern dimensions are not limited by the resolution of photolithography, and the T-shaped pattern has a large cross-sectional area.
A mold metal pattern is formed.

(Example) Hereinafter, an example of the present invention will be described with reference to FIGS. 1(a) to 1(g).

First, dummy layers 2.3 having different etching rates are formed on the semiconductor substrate 1. The dummy layer 2 is formed of a material that exhibits a higher etching rate than the dummy layer 3 during etching for undercutting in a subsequent process. Further, the material of the dummy layer 2.3 may be metal or a current-carrying body as long as it can be etched using the photoresist 4 as a mask. For example, silicide, S j02, S tON
.

Any one of SiN, alumina, etc. or a combination thereof is suitable. Next, a photoresist 4 is formed on the dummy layer 3 and patterned by photolithography to form a photoresist pattern mask (FIG. 1(a)).

Thereafter, the dummy layer 2.3 is etched by anisotropic etching such as RIE using the resist pattern 4 as a mask (FIG. 1(b)). Next, the dummy layers 2 and 3 are undercut by isotropic etching such as plasma etching or wet etching to form a dummy pattern (FIG. 1C). At this time, since the etching rate of the lower dummy layer 2 is faster than that of the dummy layer 3, the undercut becomes large, and as a result, the cross section of the dummy pattern becomes T-shaped. Next, for example, a photoresist 6 that is easily soluble in an organic solvent is applied and flattened. At this time, if the top of the dummy layer 3 cannot be exposed due to planarization, the photoresist 6 is etched by RIE or the like to expose the top of the dummy layer 3 (FIG. 1(d)). After that, the dummy layers 2 and 3 are removed by wet etching etc. (FIG. 1(e)), and the photoresist pattern thus formed is used to remove the dummy layers 2 and 3.
8i metal 5' is vapor deposited (FIG. 1(f)), and then the electrode 5 is formed by a lift-off method (FIG. 1(g)).

According to the method described above, the pattern size can be made shorter than the opening size LPR by photolithography by the amount that the dummy layer 2 is undercut, and a pattern of 4 μm or less per layer can be easily formed. can. Further, the thickness T of the photoresist 4 used for limiting the thickness t of the electrode 5 or for lift-off is determined only by the thickness of the dummy layer 2.3 without affecting the resolution of photolithography in any way, unlike in the conventional case. Also,
Increasing the thickness of the dummy layers 2 and 3 makes it easier to locate the beginning of the dummy layer 3 in the middle of the process. Therefore, in the manufacturing method of the present invention, it is easier to increase the thickness t of the electrode 5. Further, the cross-sectional shape can easily be T-shaped by making the etching rate of the dummy layers 2 and 3 larger than that of the lower dummy layer 2.

Furthermore, although the embodiment shown in Fig. 1 shows a T-shaped case with two dummy layers 2 and 3, an inverted triangular shape can also be obtained by adding more layers and using a material with a higher etching rate for the lower layers. .

By using such a manufacturing method, fine patterns can be easily formed without increasing wiring resistance and without being limited by the resolution of photolithography.

Figure 2 shows an FET manufactured using the manufacturing method of this invention.
A cross-sectional view is shown. That is, the active layer 7 is formed on the semiconductor substrate 1.
1(a) to (g) are placed on a semiconductor substrate 1 on which source and drain ohmic electrodes 8.9 are formed.
) The gate electrode 10 is formed using the method described above. The groove (referred to as a recess) in the gate portion can be obtained by etching a part of the active layer 7 after the process shown in FIG. . For example, in a GaAsFET having a cross-sectional shape as shown in FIG. 2, both the gate length and the gate resistance can be greatly reduced, so that the high speed and low noise characteristics of the FET can be greatly improved.

[Effects of the Invention] As explained above, the present invention includes forming two or more dummy layers on a semiconductor substrate, the etching rate of which is higher as the lower layer is lower, and then anisotropically etching the dummy layer using a resist pattern as a mask. After that, the dummy layer is isotropically etched to form a dummy pattern in which the undercut becomes more advanced toward the bottom, and then, after flattening with a resist film and re-locating the top of the dummy layer, Only the dummy layer is completely removed by etching, a resist pattern mask is formed on it, and then the desired metal pattern is formed by vapor deposition and lift-off, so fine patterns can be easily formed regardless of the resolution of photolithography. ,
Furthermore, since the cross-sectional shape can be made into a T-shape or an inverted triangle, wiring resistance can also be reduced. In addition, by using this manufacturing method for forming the gate electrode of an FET, it is possible to simultaneously reduce the gate length and gate resistance, which has the effect of realizing higher speed, higher frequency, lower noise, etc. of the FET.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the manufacturing process of an embodiment of the present invention;
FIG. 2 is a sectional view of an FET using the manufacturing method of the present invention for forming a gate electrode, and FIG. 3 is a sectional view showing a conventional manufacturing method. In the figure, 1 is a semiconductor substrate, 2 and 3 are dummy layers having different etching rates, 4.6 is a photoresist, and 5 is an electrode. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 LpH1 Figure Figure 2 Figure [P Kasumi]

Claims (1)

[Claims] After forming two or more dummy layers on a semiconductor substrate, the etching rate of which is higher for the lower layer, anisotropic etching is performed on the dummy layer using a resist pattern as a mask, and then isotropic etching is performed to remove the dummy layer from the lower layer. A dummy pattern with a shape that becomes more undercut is formed as the pattern progresses, and after that, it is flattened with a resist film to locate the top of the dummy layer, and only the dummy layer is completely etched away. A method for manufacturing a semiconductor device, comprising forming a mask using a resist pattern thereon, and then forming a desired metal pattern by vapor deposition and lift-off.