JPH0330369A - Manufacture of mis type semiconductor device - Google Patents

Abstract

PURPOSE:To enable fine gate electrode to be formed by a method wherein a residual etching thin film in different selection ratio of anisotropical etching process from that of a gate electrode material is selectively formed and then the whole thin film for gate electrode coating the whole surface is anisotropically etched away. CONSTITUTION:After forming a residual etching thin film 10, the whole surface is coated with another thin film for gate electrode 11. Next, the said thin film 11 is selectively removed to form the residual sidewall pattern 13 as the gate electrode along the sidewall of the residual etching thin film 10 which is selectively removed later. Accordingly, the line width and the level of the residual sidewall pattern as the gate electrode are determined by the thickness of the film for gate electrode 11 and the step level of the residual etching thin film 10. Through these procedures, the line width of the gate electrode can be miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a Mis (MOS) type semiconductor device, and more particularly to a technique for using a sidewall-remaining pattern as a gate electrode.

[Conventional technology]

In recent years, as electronic devices have become smaller and more sophisticated, MIS type semiconductor integrated circuits are required to be even more highly integrated and faster. Therefore, it is necessary to reduce the dimensions of each element in the MIS type semiconductor integrated circuit, and in particular, reducing the dimensions of the gate electrode is very important in increasing the speed of the element.

FIG. 5 shows a method of forming a gate electrode in a conventional MIS type semiconductor device. First, as shown in Figure 5(a),
A gate oxide film 2 is formed on the surface of an element region on a silicon substrate 1. Note that 3 is a field oxide film. Next, the fifth
As shown in Figure (b), after a polycrystalline silicon thin film 4 is deposited on the entire surface, a photoresist 5 is selectively formed by patterning.

Next, reactive ion etching is performed using the photoresist 5 as a mask, and as shown in FIG. Remove resist 5.

[Problem to be solved by the invention]

According to the above conventional manufacturing method, the minimum processing size of the gate electrode 4a is limited by the minimum processing size of the photoresist 5 when photoresist baking is used.

When using ultraviolet light, which is currently the mainstream,
The minimum processing dimension of the photoresist 5 that can be processed with good reproducibility is about 0.5 μm at most, and in order to process the photoresist 5 to dimensions smaller than this, patterning is performed using electron beams or X-rays instead of ultraviolet light. There is a need. However, the patterning process using electron beams or X-rays requires expensive manufacturing equipment and has poor throughput, making it unsuitable for mass production.

Therefore, an object of the present invention is to create a MIS type semiconductor device in which it is possible to obtain a thin gate electrode by using anisotropic etching without using a patterning process using an electron beam or X''m. The purpose of this invention is to provide a method for manufacturing the same.

[Means to solve the problem]

In order to solve the above problems, the means taken by the present invention is to first form a thin film (pattern) for etching, then deposit a thin film for the gate electrode on the entire surface, and then apply the thin film for the gate electrode. The etching residue thin film is selectively removed to form a sidewall pattern as a gate electrode along the sidewall of the etching residue thin film, and then the etching residue thin film is selectively removed.

[Effect]

According to this means, the line width and height of the sidewall leaving pattern as a gate electrode are determined by the thickness of the gate electrode thin film and the height of the step of the etching remaining thin film, and the gate electrode thin film is not used as in the conventional method. Compared to the case where the gate electrode is formed by patterning, the line width of the gate electrode can be made finer.

〔Example〕

Next, embodiments of the present invention will be described based on the accompanying drawings.

1 to 4 are diagrams showing semiconductor structures for explaining each process in one embodiment of the present invention, and each figure (a
) is a plan view, and each figure) represents the − point &i! in the corresponding figure (a). FIG. 2 is a cross-sectional view showing a state cut along II.

First, as shown in FIGS. 1(a) and 1(b), a gate oxide film 2 with a thickness of approximately 100 nm is grown on the surface of an element region on a silicon substrate 1, and then a thick A silicon nitride (S+J*) film of approximately 5000A is deposited. Next, this silicon nitride film is processed by patterning using ultraviolet light and reactive ion etching using, for example, (CzFs +C2Hz) gas, and the resist is removed to form a silicon nitride pattern 10 as a thin film for etching.

Next, as shown in FIGS. 2(a) and 2(c), a polycrystalline silicon film 11 having a thickness of approximately 5000 Å is deposited over the entire surface by low pressure CVD. Then, a resist mask 12 is applied only to the region of the polycrystalline silicon film 11 where a wiring contact portion is to be formed.
be coated with.

Next, the polycrystalline silicon film 11 is removed by performing reactive ion etching on the entire surface with a gas containing, for example, CCE and setting the end point of the etching at an appropriate time. ), a sidewall pattern 13 is left on the sidewall portion of the silicon nitride pattern 10 as a gate electrode. This anisotropic etching process also leaves the wiring contact portion 14 under the resist mask 12 shown in FIG. 2(a). This wiring contact portion 14 is made of wiring metal (A
/etc.) After removing the resist mask 12, a photoresist is applied to areas other than the non-resist areas 15.

Next, by performing reactive ion etching with a gas containing CC1, for example, a part of the gate electrode in the non-resist region 15 is removed, as shown in FIG. 4, and then the photoresist is removed. For example, by etching the entire surface by reactive ion etching using (CJs+C2L) gas, the pattern 13 remaining on the sidewall as a gate electrode is etched.
Then, the silicon nitride pattern 10 is removed while leaving the wiring contact portion 14. Thereafter, according to the usual process for MO3 type semiconductor devices, formation of a source-drain expansion layer, formation of an interlayer insulating film, opening of contact holes, formation of wiring patterns, etc. are performed.

In this way, the sidewall remaining pattern 13 is used as the gate electrode, but when the gate electrode is directly formed by conventional patterning using ultraviolet rays, the gate electrode width is 0.
The limit was about 5 μm, but when the sidewall remaining pattern 13 is used as a gate electrode, the line width can be reduced to about 1 μm. The line width and height are determined by the thickness of the polycrystalline silicon film 11 and the step height of the silicon nitride pattern 10.

〔Effect of the invention〕

As explained above, the present invention selectively forms etching-remaining thin films with different anisotropic etching selectivity with respect to the gate electrode material, and deposits the gate electrode thin film on the entire surface with a different anisotropic etching selectivity. By performing directional etching, a sidewall pattern is formed as a gate electrode along the sidewall of the thin film for etching, so compared to the conventional case where the gate electrode is directly formed by patterning using ultraviolet rays. A fine gate electrode can be obtained.

[Brief explanation of drawings]

1 to 4 are diagrams showing semiconductor structures for explaining each process in one embodiment of the present invention, and each figure (a
) is a plan view, and figure (b) is a cutaway view showing the state cut along the dashed-dotted line in the corresponding figure (a). FIGS. 5(a) to 5(C) are longitudinal cross-sectional views of a semiconductor structure for explaining a conventional method of manufacturing an MIS type semiconductor device. l Silicon substrate, 2 Gate oxide film, 3 Field oxide film, 1 (L silicon nitride pattern, 11 Polycrystalline silicon film, 12 Resist mask, 13 Sidewall remaining pattern as gate electrode, 14 Wiring contact part, 1
5 Non-resist area. Figure 1 Ward 3 Figure 5

Claims (1)

[Claims] 1) After forming a gate insulating film in an element region on a semiconductor substrate, a thin film for leaving etching with a different anisotropic etching selectivity with respect to the gate electrode material is formed in a region including the element region, and then a gate insulating film is formed in a region including the element region. After depositing the gate electrode thin film on the entire surface, the gate electrode thin film is selectively removed by anisotropic etching to form a sidewall pattern along the sidewall of the etched thin film as a gate electrode, and then ,
A method for manufacturing an MIS type semiconductor device, characterized by selectively removing the etching-remaining thin film.