JP2872298B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a multilayer resist technique suitable for etching a layer to be etched having large irregularities. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can be etched with a pattern according to dimensions.
A second step of forming a mask layer patterned into a predetermined shape on the flattening layer, a third step of etching the flattening layer halfway using the mask layer as a mask, A fourth step of depositing a resistance layer having resistance to an etching gas on the entire surface, and the mask shaved in the third step by anisotropically etching to leave the resistance layer on a side wall of the planarization layer. A fourth step of recovering and correcting the loss of the layer; and a step of etching the flattening layer using the mask layer and a resistant layer on a sidewall of the flattening layer as a mask.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a multilayer resist technique suitable for etching a layer to be etched having large irregularities.

2. Description of the Related Art As a semiconductor integrated circuit becomes finer and more complicated, a layer to be etched is often not flat but has a large uneven shape. The multilayer resist technology has been developed to pattern such an etched layer having large irregularities into an accurate fine shape.

[Prior Art] FIG. 3 shows a method of manufacturing a semiconductor device by a conventional multilayer resist technique.

First, a flattening layer 12 having a resist thickness of, for example, 4.0 μm is applied on a layer 10 to be etched such as a semiconductor substrate to be etched, an interlayer insulating layer, a conductive metal layer, or the like in order to flatten a step. Subsequently, a resist layer 14 having a thickness of 0.2 μm is applied on the flattening layer 12 (FIG. 3A).

Next, the upper resist layer 14 is exposed to, for example, an electron beam, and only the upper resist layer 14 is etched and patterned into a predetermined shape (FIG. 3B).

Next, using the patterned resist layer 14 as a mask, the planarizing layer 12 is anisotropically etched by reactive ion etching of oxygen (FIG. 3C).

As described above, according to the multilayer resist technique, the resist layer on the flattening layer is accurately patterned, and the thick flattening layer is etched using the patterned resist layer as a mask. Even if there is a step, a fine mask can be formed.

[Problems to be Solved by the Invention] However, in the conventional multilayer resist technology, when the planarization layer 12 is subjected to reactive ion etching, the resist layer 14 as a mask is also scraped off from the edge by a physical sputtering action, As shown in FIG. 3 (c), there is a problem that the pattern of the planarizing layer 12 eventually shifts by a length a from the design dimension.

An object of the present invention is to provide a method of manufacturing a semiconductor device that can etch a layer to be etched having a step with a pattern according to design dimensions without shifting.

[Means for Solving the Problems] The object is to provide a first step of forming a flattening layer for flattening a layer to be etched, and a second step of forming a mask layer patterned in a predetermined shape on the flattening layer. A third step of partially etching the flattening layer using the mask layer as a mask, a fourth step of depositing a resistance layer having resistance to an etching gas for the flattening layer on the entire surface, and anisotropic etching. A fourth step of recovering and correcting the loss of the mask layer removed in the third step by leaving the resistant layer on the side wall of the planarization layer, Etching the flattening layer using the resistive layer on the side wall as a mask.

[Operation] According to the present invention, the shift amount due to the etching of the flattening layer is corrected by the resistive film remaining on the side wall to form a wiring pattern, a through-hole pattern and the like as designed.

Embodiment A method of manufacturing a semiconductor device according to an embodiment of the present invention
This will be described with reference to the drawings. The same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be simplified or omitted.

In this embodiment, the present invention is applied to a two-layer resist method of a multilayer resist technique.

First, a flattening layer 12 of, for example, a resist (NPR-820: manufactured by Nagase & Co., Ltd.) having a thickness of 4.0 μm is applied on a layer 10 to be etched such as a semiconductor substrate to be etched, an interlayer insulating layer, and a conductive metal layer. . After application, heat to about 300 ° C and planarize layer 12
Make the surface flat. Subsequently, a resist layer 14 having a thickness of 0.2 μm is applied on the flattening layer 12. This resist layer 1
4 is made of, for example, polymethylcissesquioxa (PMSS) which is a polymer material containing Si. Subsequently, the resist layer 14 is exposed to an electron beam, developed, and patterned into a predetermined shape (FIG. 1A).

Next, using the patterned resist layer 14 as a mask, the planarizing layer 12 is anisotropically etched halfway by oxygen reactive ion etching. O ₂ gas flow rate is 400SCC
Etching is performed under the conditions of M, 0.03 Torr, and 3.8 W / cm ² . At this time, the resist layer 14 is scraped off and shifted by a length a as in the conventional case (FIG. 1B).

Next, an SiO ₂ film 16 is deposited on the entire surface by a CVD method as a resistant film resistant to oxygen reactive etching (first method).
Figure (c). At this time, the SiO ₂ film 16 is also deposited on the side wall of the etched planarization layer 12. The SiO ₂ film is adhered to the side wall by a thickness that corrects the shift length a of the resist layer 14.
Form 16. For example, a SiH ₄ flow rate of 6 SCCM and an N ₂ O flow rate of 26
0 SCCM, and N ₂ flow rate 50 SCCM, S under the conditions of 0.25W / cm ^2, 200 ℃
An iO ₂ film 16 is deposited.

Next, reactive ion etching is performed on the entire surface with a CF ₄ -based gas to leave the SiO ₂ film 16 only on the side wall of the planarization layer 12 (FIG. 1D). For example, CF ₄ gas is 100 SCCM, 0.3 Torr,
Reactive ion etching is performed under the condition of 4.5 W / cm ² . By combining the resist layer 14 and the SiO ₂ film 16 remaining on the side walls, a mask having the designed dimensions is formed.

Next, using the resist layer 14 and the SiO ₂ film 16 remaining on the side walls as a mask, a planarizing layer is formed by reactive ion etching of oxygen.
12 is etched to the end (FIG. 1 (e)). Resist layer
By correcting the length a shifted by 14 with the SiO ₂ film 16 on the side wall, the flattening layer 12 is etched according to the design dimensions.

As described above, according to the present embodiment, the shift amount of the resist layer due to the etching of the flattening layer can be corrected by the SiO ₂ film to form a pattern as designed.

A method of manufacturing a semiconductor device according to another embodiment of the present invention will be described with reference to FIG. The same components as those in FIG. 1 are denoted by the same reference numerals, and the description will be simplified.

In this embodiment, the present invention is applied to a three-layer resist method of a multilayer resist technique.

First, for example, a resist (NPR-8
20: Nagase & Co., Ltd.) and a flattening layer 12 having a thickness of 4.0 μm. Subsequently, a 0.2 μm-thick, for example, OLD7F11
2 (manufactured by Tokyo Ohka) is formed. Next, middle layer 1
A resist layer 20, which is the upper layer of NPR-820, is formed on 8 and patterned into a predetermined shape by light exposure and development (FIG. 2 (a)).

Next, using the patterned resist layer 20 as a mask, the intermediate layer 18 is etched (FIG. 2B). CF ₄
Under the conditions of a gas flow rate of 100 SCCM, 0.3 Torr, 5 W / cm ² , the intermediate layer 18
Is patterned.

Next, the planarizing layer 12 is anisotropically etched halfway by reactive ion etching of oxygen using the patterned intermediate layer 18 as a mask. At this time, the intermediate layer 18 is scraped and shifted by the length a (FIG. 2 (c)).

Thereafter, as in the embodiment of FIG. 1, an SiO ₂ film 16 is deposited on the entire surface by the CVD method (FIG. 2 (d)), and reactive ion etching is performed on the entire surface with a CF ₄ -based gas. ₂ membrane
16 is left on the side wall of the planarizing layer 12 (FIG. 2 (e)),
The shift of 18 is corrected by the SiO ₂ film 16. Subsequently, using the intermediate layer 18 and the SiO ₂ film 16 remaining on the side walls as a mask, the planarization layer 12 is etched to the end by reactive ion etching of oxygen (FIG. 2 (f)).

As described above, according to the present embodiment, the shift amount of the intermediate layer due to the etching of the flattening layer can be corrected by the SiO ₂ film to form a pattern as designed.

The present invention is not limited to the above embodiment, and various modifications are possible.

For example, in the above-described embodiment, the resistance layer is formed of the SiO ₂ layer, but another material layer such as a PSG film may be used as long as the layer has resistance to the etching gas for the flattening layer.

In addition, since the flattening layer is thick, if the mask is scraped and shifted even when the flattening layer is etched using the resist layer on the mask layer and the side wall as a mask, the etching of the flattening layer is stopped halfway, A second resistant layer is formed on the entire surface, corrected by the second resistant layer left on the side wall by anisotropic etching, and the planarization layer is etched using the mask layer and the second resistant layer on the side wall as a mask. You may do so.

[Effects of the Invention] As described above, according to the present invention, an etching target layer having a step can be etched in a pattern according to design dimensions without shifting.

[Brief description of the drawings]

FIG. 1 is a process diagram of a method of manufacturing a semiconductor device according to one embodiment of the present invention, FIG. 2 is a process diagram of a method of manufacturing a semiconductor device according to another embodiment of the present invention, and FIG. It is a process drawing of a manufacturing method. In the figure, 10 ... layer to be etched 12 ... planarization layer 14 ... resist layer 16 ... SiO ₂ film 18 ... intermediate layer 20 ... resist layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/302

Claims (1)

(57) [Claims] A first step of forming a flattening layer for flattening a layer to be etched; a second step of forming a mask layer patterned into a predetermined shape on the flattening layer; and masking the mask layer. A third step of partially etching the flattening layer, a fourth step of depositing a resistance layer having a resistance to an etching gas for the flattening layer over the entire surface, and forming the resistance layer by anisotropic etching. A fourth step of recovering and correcting the loss of the mask layer shaved in the third step by leaving it on the side wall of the flattening layer; and using the resist layer on the side wall of the mask layer and the flattening layer as a mask. Etching the flattening layer. A method for manufacturing a semiconductor device, comprising: