JP2612357B2 - Method of manufacturing gate electrode of transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a method for manufacturing a gate electrode of a transistor, and particularly to a method of manufacturing an enhancement mode field effect transistor (hereinafter referred to as FET) using a compound semiconductor or the like. The present invention relates to a method for manufacturing an electrode.

(Prior Art) Conventionally, there are, for example, the following techniques in such a field.

FIG. 2 is a sectional view showing a manufacturing process of a gate electrode of such a conventional transistor.

First, a lower resist layer 12 is formed on a base 10, as shown in FIG. In addition, 14 is a channel region.

Next, as shown in FIG. 2B, a lower resist pattern 16 is formed on the channel region 14 of the underlayer 10 by using the photolithography technique.

Next, as shown in FIG. 2C, an upper resist pattern 18 is formed. Therefore, first, an upper resist layer is formed by coating, and then, on the lower resist pattern 16,
A pattern layer 18 having a first opening 20 exposing a part of the surface and a second opening 22 for forming a gate pad or a pad for wiring connection is formed.

Next, as shown in FIG. 2 (d), an appropriate metal, for example, Al (aluminum) is directionally vapor-deposited on the upper layer from the surface side of the resist pattern 18 with an inclination of θ with respect to the normal to the underlying surface. The metal deposition layer 24 (24a, 24b, 24c) is formed. In this case, the deposition direction θ is determined according to the design depending on how the gate length of the gate electrode formed in a later step is determined. By this directional deposition, the metal deposition layers 24a and 24b are formed on the upper surface of the upper resist pattern 18, the exposed surface of the lower resist pattern 16 in the first opening 20, and the exposed surface of the base 10 in the second opening 22. And 24c are formed respectively. In this case, as is well known, a metal deposition layer
The width of the channel 24b in the channel direction is determined by the above-described vapor deposition direction θ and the position of the vapor deposition surface and the upper surface edge portion of the upper resist pattern 18 on the first opening 20 side.

Next, as shown in FIG. 2 (e), a third opening 26 is formed in the lower resist pattern 16. In this case, the third opening 26 is formed by performing dry etching with an appropriate ion species using the metal deposition layer 24 as a mask, and the surface of the base 10 is partially exposed. By this etching,
The lower portions of the metal deposition layer 24b and the edge portions of the upper resist pattern 18 are also under-etched.

Next, in FIG. 2 (f), the exposed surface of the base 10 is etched to form a first groove (recess) 28 for forming a gate electrode and a second groove (recess) 30 for forming a pad portion. Provided simultaneously or sequentially. Therefore, first, the metal deposition layer 24a on the upper surface of the upper resist pattern 18, the metal deposition layer 24b temporarily provided in the first opening 20, and the metal deposition layer 24c in the second opening 22 are removed. Is performed by either dry etching or wet etching or a combination of both.

Subsequently, in FIG. 2 (g), an appropriate gate electrode material is deposited, and a gate electrode 32 is formed in the first groove 28 and a pad portion 34 is formed in the second groove 30 at the same time. As is well known, the width of the gate electrode 32 in this case in the channel direction (gate length)
W ₁ is determined by the width between the edge of the lower resist pattern 16 that is in contact with the base 10 and the edge of the upper surface of the upper resist pattern 18 forming the wall of the first opening 20, and the channel of the pad 34 is The width W _{2 in the} direction is determined by the width between the edges of the upper surface on both sides of the upper resist pattern 18 forming the wall of the second opening 22.

The other vapor-deposited layer 36 (formed on the lower resist pattern 16) and the vapor-deposited layer 38 (formed on the upper resist pattern 18) formed by this vapor deposition are usually different from the gate electrode 32 and the pad portion 34. Are formed apart from each other without being continuous.

Next, in FIG. 2 (h), when the lower resist pattern 16 and the upper resist pattern 18 on the base 10 are removed by so-called lift-off, the first groove 28 of the base 10 has a gate electrode 32 having a narrow width in the channel direction. Is formed, and a pad portion 34 whose width in the channel direction is wider than the gate electrode 32 remains in the second groove 30.

As described above, according to the above-described conventional technique, it is possible to form a gate electrode of a transistor which is narrower to a certain extent and exceeds the resolution of a resist.

(Problems to be Solved by the Invention) However, in the case of the above-described conventional method for forming a gate electrode of a transistor, in the step shown in FIG. After removing the deposited metal layer 24b and the deposited metal layer 24c in the second opening 22, the first groove 28 for forming the gate electrode and the second groove 30 for forming the pad portion are provided by wet etching. Then, the first groove 28 is exposed on both sides of the formed gate electrode 32.

Therefore, the FET in the enhancement mode (the drain current does not flow when the gate voltage is zero and the drain current increases as the gate voltage increases)
In the fabrication of the device, since the channel layer in that portion becomes thin, the resistance increases, and the various characteristics of the FET deteriorate.

Therefore, when the etching for providing the first groove 28 and the second groove 30 is performed by anisotropic dry etching, the selectivity between the upper resist pattern 18, the lower resist pattern 16 and the base (substrate) 10 cannot be obtained. spread, is not reproduced gate length W ₁ designed by deposition direction θ set in the step shown in FIG. 2 (d). Lift-off cannot be performed in the step shown in FIG.

According to the present invention, in the above-described conventional method for manufacturing a gate electrode of a transistor, the process shown in FIG.
When the first groove 28 is formed by dry etching after removing the metal deposition layer 24b temporarily formed in the first opening 20, the gate length is increased. Although problems such as the inability to lift off can occur, the above problems are solved by performing dry etching prior to removing the temporarily provided metal deposition layer 24b in order to remove the problem.
A method of manufacturing a gate electrode of a transistor that can obtain an enhancement mode FET having excellent characteristics by combining wet etching with dry etching before or after removal of the temporarily provided metal deposition layer 24b. The purpose is to provide.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for manufacturing a gate electrode of a transistor, comprising the steps of: providing a lower resist pattern on an underlying channel region; Providing an upper resist pattern having a first opening for providing a partial exposed surface and a second opening for providing a partial exposed surface of the base, an exposed surface of the lower resist pattern, and an exposed surface of the base And a step of providing a metal deposition layer on the upper surface of the upper resist pattern using a directional vapor deposition technique, and using the metal deposition layer as a mask, etching the lower resist pattern to expose the underlying surface to the lower resist pattern. Providing a third opening, and using the metal deposition layer as a mask, anisotropic dry etching with respect to the exposed surfaces exposed to the second and third openings. Providing a first groove for forming a gate electrode and a second groove for forming a pad portion on a base by performing etching, a step of removing the metal deposition film, and a step of performing isotropic etching; A step of depositing a metal in the first and second grooves to provide a gate electrode and a pad metal layer at the same time, and a step of removing the lower resist pattern and the upper resist pattern are performed.

Further, the isotropic etching may be performed before performing the anisotropic dry etching, and then the anisotropic dry etching may be performed. In that case, after the anisotropic dry etching, isotropic etching is further performed to remove the damaged layer.

(Operation) According to the present invention, since the gate electrode is configured as described above, a gate electrode having a structure in which the side of the gate electrode does not spread can be formed, and an enhancement-mode FET having excellent characteristics without increasing resistance can be provided. Can be made.

After the recess is formed by anisotropic etching, the damaged layer is removed by wet etching so as to form a recess having good characteristics.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view illustrating a process of manufacturing a gate electrode of a transistor according to an embodiment of the present invention. Each cross-sectional view shown here shows a cross section orthogonal to the base and parallel to the channel direction. Also, in this figure, the same components as those shown in FIG. 2 are denoted by the same reference numerals unless otherwise specified, and detailed description thereof will be omitted.

First, the cross-sectional view of FIG. 1 (a) corresponds to FIG. 2 (e) described above. That is, FIG.
FIG. 2E is applied. Here, Ga is used as the base 10.
It is formed of a compound semiconductor such as As, Si (silicon), or another material used as a normal substrate.
In addition, a region required for a semiconductor element may or may not be formed in advance on base 10. Here, a GaAs substrate on which the channel region 14 and the n ⁺ layer 15 are formed is used.

The material for forming the lower resist pattern 16 is, for example,
ODUR (trade name) manufactured by Tokyo Ohka Co., Ltd. The material for forming the upper resist pattern 18 is, for example, LMRF22 manufactured by Fuji Pharmaceutical Co., Ltd.
(Product No.) However, these two resist materials are not limited to the above, as long as the combination can form the upper resist pattern without mutual reaction between the resists. Use other materials. Can be. Metal deposition layer
24 (24a, 24b, and 24c) is, for example, Al (aluminum)
However, any material can be used as long as it can be used as a mask for various types of etching in the subsequent steps. The direction θ may be appropriately set according to the width of the gate electrode to be formed along the channel direction.

In this way, after obtaining the structure as shown in FIG. 1A, anisotropic dry etching is performed as shown in FIG. Transitional second groove
Get 30 '. At this time, since the anisotropic dry etching is performed with the metal deposition film 24 (24a, 24b, 24c) left as it is, the reduction of the resist film due to the dry etching is prevented. In this embodiment, due to the Cl ₂ ECR (Electron C
yclotron Resonance) Etching is performed under anisotropic dry etching conditions.

Subsequently, as shown in FIG. 1 (c), the metal deposition film 24 (24
a, 24b, 24c). Since this GaAs substrate has the n ⁺ layer 15 as the upper layer, if the gate is lifted off by evaporation as it is,
Since the gate rises to the n ⁺ layer 15, n ⁺
Layer 15 must be kept away from the gate metal electrode by isotropic etching. Therefore, as shown in FIG. 1 (d), wet etching is performed to finally form the first groove.
28 "and a final second groove 30" are formed.

Next, as shown in FIG. 1 (e), a gate electrode material is deposited to form a gate electrode 32 'and a pad portion 34' as in the conventional process.

Next, as shown in FIG. 1 (f), lift-off is performed to form a gate electrode 32 'and a pad portion 34'.

In this embodiment, the gate electrode can be formed in the first groove (recess) having a shape in which the gate does not rise on the n ⁺ layer 15 and has no side of the gate.

FIG. 3 is a cross-sectional view showing a process of manufacturing a gate electrode of a transistor according to another embodiment of the present invention.

First, FIG. 3 (a) corresponds to FIG. 1 (a).

Next, as shown in FIG. 3 (b), the metal deposition film 24 (24
While leaving a, 24b, and 24c), wet etching is performed to form the initial first groove 40 and the initial second groove 41.

Subsequently, as shown in FIG.
Anisotropic dry etching is performed while leaving (24a, 24b, 24c) to form an intermediate first groove 42 and an intermediate second groove 43. At this time, since the anisotropic dry etching is performed while the metal deposition film 24 (24a, 24b, 24c) is left,
Resist thinning due to dry etching is prevented.

Next, as shown in FIG. 3D, the metal deposition film 24 (24
a, 24b, 24c), wet etching is again performed to remove the damaged layer on the surface etched by dry etching, thereby forming the final first groove 44 and the final second groove 45. I do.

Next, as shown in FIG. 3 (e), a gate electrode material is deposited in the same manner as in the conventional process to form a gate electrode 32 'and a pad portion 34'.

Next, as shown in FIG. 3 (f), lift-off is performed to form a gate electrode 32 '.

FIG. 4 shows an n ⁺ layer 15 produced according to the present invention as an upper layer.
Transconductance value for threshold voltage (V) of FET [m
S a (milli Siemens) / mm] characteristic diagram, in a FET having an n ⁺ layer 15 manufactured according to the invention the upper layer (I), FET having an n ⁺ layer produced by the conventional gate electrode forming method as an upper layer To (I
I).

As is clear from this figure, the FE manufactured by the conventional method was used.
As for T, the transconductance value starts to decrease when the threshold voltage is around -0.5 V, and when the threshold voltage is around 0 V, a high transconductance value can no longer be obtained.

On the other hand, the FET manufactured by the method according to the present invention has a sufficient transconductance value even when the threshold voltage is near 0 V, and the characteristics do not deteriorate when the enhancement mode FET is manufactured.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible based on the gist of the present invention.
They are not excluded from the scope of the present invention.

(Effects of the Invention) As described above in detail, according to the present invention, when a gate electrode and a pad portion are simultaneously formed in the same vapor deposition step, a gate electrode having a structure in which the side of the gate electrode does not spread is formed. can do.

After the recess is formed by anisotropic etching, the damaged layer is removed by wet etching, so that a recess having good characteristics can be formed.

Therefore, enhancement mode FET with good characteristics
Can be produced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a manufacturing process of a gate electrode of a transistor showing an embodiment of the present invention, FIG. 2 is a cross-sectional view of a manufacturing process of a gate electrode of a conventional transistor, and FIG. 3 shows another embodiment of the present invention. Manufacturing process cross-sectional view of the gate electrode of the transistor
FIG. 4 is a diagram showing a threshold voltage vs. transconductance characteristic of a transistor. 10 ... underlying, 16 ... lower resist pattern, 18 ... upper resist pattern, 20 ... first opening, 22 ... second opening, 24 (24a, 24b, 24c) ... metal deposition layer, 26 ... Third opening, 28 ′ Transient first groove, 28 ″ First groove, 30 ′
... Transitional second groove, 30 ″ second groove, 32 ′ gate electrode, 34 ′ pad portion, 40 first initial groove, 41
Initial second groove, 42 ... Intermediate first groove, 43 ... Intermediate second groove, 44 ... Final first groove, 45 ... Final second
groove.

Claims (3)

(57) [Claims] 1. A step of: (a) providing a lower resist pattern on an underlying channel region; and (b) a first opening for providing a partially exposed surface of the lower resist pattern, and a partially exposed surface of the underlying resist pattern. Give the second
(C) providing a metal deposition layer on the exposed surface of the lower resist pattern, the exposed surface of the base, and the upper surface of the upper resist pattern using a directional deposition technique; (D) etching the lower resist pattern using the metal deposition layer as a mask to provide a third opening exposing a base surface in the lower resist pattern; and (e) removing the metal deposition layer. The second and third masks are used as masks.
Performing anisotropic dry etching on the exposed surface exposed to the opening to provide a first groove for forming a gate electrode and a second groove for forming a pad portion on the underlayer; (G) a step of performing isotropic etching; (h) a step of depositing a metal in the first and second grooves to simultaneously provide a gate electrode and a pad metal layer; (I) removing the lower resist pattern and the upper resist pattern. (A) providing a lower resist pattern on the underlying channel region; and (b) a first opening for providing a partially exposed surface of the lower resist pattern and a partially exposed surface of the underlying resist pattern. Give the second
(C) providing a metal deposition layer on the exposed surface of the lower resist pattern, the exposed surface of the base, and the upper surface of the upper resist pattern using a directional deposition technique; (D) etching the lower-layer resist pattern using the metal-deposited layer as a mask to provide a third opening exposing a base surface in the lower-layer resist pattern; and (e) performing isotropic etching. And (f) using the metal-deposited layer as a mask,
(G) forming a first groove for forming a gate electrode and a second groove for forming a pad portion on an underlayer by performing anisotropic dry etching on the exposed surface exposed to the opening; (H) depositing a metal in the first and second grooves to simultaneously provide a gate electrode and a pad metal layer; and (i) removing the lower resist pattern and the upper resist pattern. Removing the gate electrode. 3. A step of: (a) providing a lower resist pattern on an underlying channel region; and (b) a first opening for providing a partially exposed surface of the lower resist pattern, and a partially exposed surface of the underlying resist pattern. Give the second
(C) providing a metal deposition layer on the exposed surface of the lower resist pattern, the exposed surface of the base, and the upper surface of the upper resist pattern using a directional deposition technique; (D) etching the lower resist pattern using the metal deposition layer as a mask to provide a third opening exposing a base surface in the lower resist pattern; and (e) performing isotropic etching. And (f) using the metal-deposited layer as a mask,
(G) forming a first groove for forming a gate electrode and a second groove for forming a pad portion on a base by performing anisotropic dry etching on the exposed surface exposed to the opening; (H) further performing isotropic etching to remove a damaged layer on the surface of the first groove and the second groove; and (i) removing the damaged layer from the first and second grooves. A method for forming a gate electrode, comprising: depositing a metal to simultaneously provide a gate electrode and a pad metal layer; and (j) removing the lower resist pattern and the upper resist pattern.