JPH0336302B2 - - Google Patents
Info
- Publication number
- JPH0336302B2 JPH0336302B2 JP56198934A JP19893481A JPH0336302B2 JP H0336302 B2 JPH0336302 B2 JP H0336302B2 JP 56198934 A JP56198934 A JP 56198934A JP 19893481 A JP19893481 A JP 19893481A JP H0336302 B2 JPH0336302 B2 JP H0336302B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon nitride
- silicon
- nitride film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 39
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 38
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 38
- 238000002955 isolation Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000009740 moulding (composite fabrication) Methods 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- 230000003647 oxidation Effects 0.000 description 18
- 238000007254 oxidation reaction Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Description
【発明の詳細な説明】
この発明は酸化膜分離構造を有する半導体装置
の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having an oxide film isolation structure.
半導体装置に酸化膜分離構造を形成する方法と
して、選択酸化法が従来より広く用いられてい
る。 A selective oxidation method has been widely used as a method for forming an oxide film isolation structure in a semiconductor device.
第１図ＡないしＤは、前記方法により酸化膜分
離構造を有する半導体装置を製造する場合の工程
手段を示しており、次のようにして製造される。 FIGS. 1A to 1D show process means for manufacturing a semiconductor device having an oxide film isolation structure by the method described above, and the semiconductor device is manufactured in the following manner.
(1) シリコン基板１の上に下地シリコン酸化膜２
およびシリコン窒化膜３を形成した後、レジス
ト４を島領域形成箇所に残して部分的に開口す
る（第１図Ａ）。(1) Base silicon oxide film 2 on silicon substrate 1
After forming the silicon nitride film 3, a partial opening is made leaving the resist 4 at the location where the island region is to be formed (FIG. 1A).
(2) ついで、レジスト４をマスクとしてシリコン
窒化膜３をプラズマエツチングにより除去し、
さらに下地シリコン酸化膜２をフツ素系のエツ
チング液でエツチング除去する（同図Ｂ）。(2) Next, using the resist 4 as a mask, the silicon nitride film 3 is removed by plasma etching,
Further, the underlying silicon oxide film 2 is removed by etching with a fluorine-based etching solution (FIG. 3B).
(3) 続いて、異方性ドライエツチングによりシリ
コン基板１を所望の深さだけエツチングする
（同図Ｃ）。(3) Next, the silicon substrate 1 is etched to a desired depth by anisotropic dry etching (FIG. 3C).
(4) レジスト４を除去した後、シリコン窒化膜３
をマスクとして選択酸化を行い、分離酸化膜５
を形成する。しかる後、分離酸化膜形成にさい
し成長したシリコン酸化膜を除去し、さらにシ
リコン窒化膜３を除去することにより酸化膜分
離構造を完成する（同図Ｄ）。(4) After removing the resist 4, remove the silicon nitride film 3.
Selective oxidation is performed using the mask as a mask to form the isolation oxide film 5.
form. Thereafter, the silicon oxide film grown during the formation of the isolation oxide film is removed, and the silicon nitride film 3 is further removed to complete the oxide film isolation structure (FIG. 3D).
しかしながら、このようにして形成された分離
酸化膜は、シリコン基板開口部より下地シリコン
酸化膜を通じて横方向の酸化が進み、素子形成さ
れるべき島領域の面積がマスク設計に対して減少
するという欠点を有する。 However, the isolation oxide film formed in this way has the drawback that oxidation progresses in the lateral direction through the underlying silicon oxide film from the silicon substrate opening, and the area of the island region where the device is to be formed is reduced relative to the mask design. has.
そして、このような欠点のために、素子寸法を
正確に設定できないという問題点が生じるばかり
でなく、島領域に形成された素子の電気的特性が
横方向の酸化の入り込みにより影響を受けるとい
う問題がある。また、横方向の酸化の入り込みが
下地シリコン酸化膜の膜厚に依存するため、マス
ク設計において一様性に欠ける。 These drawbacks not only cause the problem that the device dimensions cannot be set accurately, but also the problem that the electrical characteristics of the device formed in the island region are affected by the penetration of oxidation in the lateral direction. There is. Furthermore, since the penetration of oxidation in the lateral direction depends on the thickness of the underlying silicon oxide film, uniformity is lacking in mask design.
一方、下地シリコン酸化膜の膜厚を薄くして横
方向の酸化を防止しようとすると、分離酸化膜形
成時に結晶欠陥が誘起されやすくなるという欠点
が生じる。 On the other hand, if an attempt is made to prevent lateral oxidation by reducing the thickness of the underlying silicon oxide film, a drawback arises in that crystal defects are more likely to be induced when forming the isolation oxide film.
したがつて、この発明の目的は、横方向への酸
化の入り込みがなく寸法精度が高く結晶欠陥のな
い酸化膜分離構造を有する半導体装置の製造方法
を提供することである。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device having an oxide film isolation structure that is free from lateral oxidation, has high dimensional accuracy, and is free from crystal defects.
この発明の一実施例を第２図に示す。 An embodiment of this invention is shown in FIG.
(1) まず、シリコン基板６の上に順次下地シリコ
ン酸化膜８ａおよび第１シリコン窒化膜９ａを
積層形成した後、レジスト１０を島領域形成予
定箇所に残して部分的に開口する（第２図Ａ）。(1) First, a base silicon oxide film 8a and a first silicon nitride film 9a are sequentially laminated on a silicon substrate 6, and then a partial opening is made, leaving a resist 10 at a location where an island region is to be formed (see FIG. A).
(2) ついで、レジスト１０をマスクとして第１シ
リコン窒化膜９ａをプラズマエツチングにより
除去し、さらに下地シリコン酸化膜８ａをエツ
チング除去する（同図Ｂ）。(2) Next, using the resist 10 as a mask, the first silicon nitride film 9a is removed by plasma etching, and the base silicon oxide film 8a is further etched away (FIG. B).
(3) 続いて、異方性ドライエツチングによりシリ
コン基板６を所望の深さだけエツチングする
（同図Ｃ）。(3) Next, the silicon substrate 6 is etched to a desired depth by anisotropic dry etching (FIG. C).
(4) レジスト１０を除去した後、下地シリコン酸
化膜８ａの上に形成された第１シリコン窒化膜
９ａが前記下地シリコン酸化膜８ａの開口側面
より内方にひさし状に出るように、下地シリコ
ン酸化膜８ａをフツ酸系エツチヤントにより島
領域側にサイドエツチングする（同図Ｄ）。(4) After removing the resist 10, remove the base silicon oxide film 8a so that the first silicon nitride film 9a formed on the base silicon oxide film 8a protrudes inward from the opening side surface of the base silicon oxide film 8a. The oxide film 8a is side-etched toward the island region using a hydrofluoric acid etchant (D in the same figure).
(5) 続いて、第２シリコン酸化膜８ｂおよび第２
シリコン窒化膜９ｂを形成する（同図Ｅ）。(5) Next, the second silicon oxide film 8b and the second
A silicon nitride film 9b is formed (FIG. E).
(6) 異方性ドライエツチングにより、第２シリコ
ン窒化膜９ｂをその膜厚だけエツチング除去
し、島領域の側面にのみ第２シリコン窒化膜９
ｂを残す（同図Ｆ）。(6) By anisotropic dry etching, the second silicon nitride film 9b is etched away by the thickness thereof, and the second silicon nitride film 9b is removed only on the side surfaces of the island region.
b (Figure F).
(7) 続いて、島領域の表面および側面の第１シリ
コン窒化膜９ａおよび第２シリコン窒化膜９ｂ
をマスクとして選択酸化を行ない、分離酸化膜
７を形成する（同図Ｇ）。この後、分離酸化膜
形成に際し成長したシリコン酸化膜を除去し、
さらにシリコン窒化膜を除去することにより酸
化膜分離構造を完成する。(7) Next, the first silicon nitride film 9a and the second silicon nitride film 9b are formed on the surface and side surfaces of the island region.
Selective oxidation is performed using as a mask to form isolation oxide film 7 (G in the same figure). After this, the silicon oxide film grown during the formation of the isolation oxide film is removed,
Furthermore, the silicon nitride film is removed to complete the oxide film isolation structure.
このようにして形成された分離酸化膜は、シリ
コン基板６の島領域となる部分の表面および側面
にシリコン窒化膜９ａ，９ｂを被着させた構造よ
り形成されているため、従来問題となつていた横
方向の酸化の入り込みを防止することができ、寸
法精度の良い酸化膜分離構造とすることができ
る。 The isolation oxide film thus formed has a structure in which the silicon nitride films 9a and 9b are deposited on the surface and side surfaces of the island region of the silicon substrate 6, which has caused problems in the past. It is possible to prevent oxidation from entering in the lateral direction, and it is possible to obtain an oxide film isolation structure with good dimensional accuracy.
また横方向の酸化の入り込みは、下地シリコン
酸化膜８ａおよび第２シリコン酸化膜８ｂの膜厚
に関係なく防止できるので、十分な酸化膜厚まで
形成して分離酸化膜形成時の結晶欠陥の発生を防
止できるという効果を得ることができる。 In addition, the penetration of oxidation in the lateral direction can be prevented regardless of the film thickness of the base silicon oxide film 8a and the second silicon oxide film 8b, so that the oxide film can be formed to a sufficient thickness to prevent crystal defects when forming the isolation oxide film. The effect of preventing this can be obtained.
さらに、第２図Ｄのように下地シリコン酸化膜
８ａをサイドエツチングし、第１シリコン窒化膜
９ａの開口縁が下地シリコン酸化膜８ａの開口側
面に対してひさし状に張り出した構造に形成する
ことにより、以後側面に第２シリコン窒化膜９ｂ
を形成するに際し、十分な耐酸化性をもつた膜厚
に形成できるという効果を得ることができる。 Furthermore, as shown in FIG. 2D, the base silicon oxide film 8a is side-etched to form a structure in which the edge of the opening of the first silicon nitride film 9a extends over the side surface of the opening of the base silicon oxide film 8a. Thereafter, a second silicon nitride film 9b is formed on the side surface.
When forming the film, it is possible to obtain the effect that the film can be formed to a thickness with sufficient oxidation resistance.
第３図Ａ，Ｂは、前記の効果を説明する図であ
る。同図Ａは下地シリコン酸化膜８ａをサイドエ
ツチングしないで第２シリコン酸化膜８ｂおよび
第２シリコン窒化膜９ｂを被着した後、異方性ド
ライエツチングにより側面に第２シリコン窒化膜
９ｂを限定形成した図で、同図Ｂはそれに対し
て、下地シリコン酸化膜８ａをサイドエツチング
したあと側面に第２シリコン窒化膜９ｂを形成し
た図である。下地シリコン酸化膜８ａをサイドエ
ツチングした場合、同じ膜厚の第２シリコン酸化
膜８ｂを形成する際、下地シリコン酸化膜８ａと
の境界でシリコン酸化膜の膜厚の約半分程の段差
が生じる。その結果、第３図Ａ，Ｂからわかるよ
うに、下地シリコン酸化膜８ａをサイドエツチン
グした場合の方が、サイドエツチングしない場合
に比べて側面ｂの部分での第２シリコン窒化膜９
ｂの残りが多いことがわかる。 FIGS. 3A and 3B are diagrams illustrating the above effect. In Figure A, after a second silicon oxide film 8b and a second silicon nitride film 9b are deposited without side-etching the base silicon oxide film 8a, a second silicon nitride film 9b is formed in a limited manner on the side surface by anisotropic dry etching. On the other hand, Figure B is a diagram in which a second silicon nitride film 9b is formed on the side surface after side-etching the underlying silicon oxide film 8a. When the base silicon oxide film 8a is side-etched, when forming the second silicon oxide film 8b of the same thickness, a step approximately half the thickness of the silicon oxide film is generated at the boundary with the base silicon oxide film 8a. As a result, as can be seen from FIGS. 3A and 3B, when the base silicon oxide film 8a is side-etched, the second silicon nitride film 9 on the side surface b is better when the base silicon oxide film 8a is side-etched than when the side-etching is not performed.
It can be seen that there is a large amount of b remaining.
窒化膜９ａ，９ｂの膜厚の薄い部分が一箇所で
もあれば、選択酸化の途中で窒化膜の耐酸化マス
ク性がなくなり、その部分から酸化が進行する。
例えば、表面の第１シリコン窒化膜９ａ、側面の
第２シリコン窒化膜９ｂの膜厚を1000Å、下地シ
リコン酸化膜８ａ、第２シリコン酸化膜８ｂの膜
厚を300Åとし、約1.5μmの厚さの分離酸化膜を
形成すると、第３図Ａの構造では、酸化の途中で
シリコン窒化膜９ａ，９ｂの角部ｂの所より酸化
が始まり、横方向の酸化が進行したのに対し、第
３図Ｂの構造では、横方向の酸化はなかつた。 If there is even one thin portion of the nitride films 9a, 9b, the oxidation masking properties of the nitride film will be lost during selective oxidation, and oxidation will proceed from that portion.
For example, the thickness of the first silicon nitride film 9a on the front surface and the second silicon nitride film 9b on the side surfaces is 1000 Å, the thickness of the base silicon oxide film 8a and the second silicon oxide film 8b is 300 Å, and the thickness is approximately 1.5 μm. When an isolation oxide film is formed, in the structure shown in FIG. In the structure of Figure B, there was no lateral oxidation.
以上のように、この発明の半導体装置の製造方
法は、シリコン基板上に順次下地シリコン酸化膜
および第１シリコン窒化膜を積層形成し島領域を
残して前記第１シリコン窒化膜、下地シリコン酸
化膜およびシリコン基板の一部をドライエツチン
グ法によりエツチング除去し開口部を形成する工
程と、前記第１シリコン窒化膜の開口縁が前記下
地シリコン酸化膜の開口側面より内方にひさし状
に張り出すように前記下地シリコン酸化膜の開口
側面をサイドエツチングする工程と、シリコン基
板上に第２シリコン窒化膜を堆積形成するととも
に異方性ドライエツチング法により前記開口部の
底面に堆積した第２シリコン窒化膜をエツチング
除去して島領域の表面および側面に第２シリコン
窒化膜を形成する工程と、前記第１、第２シリコ
ン窒化膜をマスクとして前記開口部を選択酸化し
分離酸化膜を形成する工程とを含むものであるた
め、横方向の酸化の入り込みがなく、かつ十分な
耐酸化マスク性を有することにより、寸法精度が
高く、信頼性の高い酸化膜分離構造の形成を正確
かつ容易に行うことができるという効果を有す
る。 As described above, in the method of manufacturing a semiconductor device of the present invention, a base silicon oxide film and a first silicon nitride film are sequentially stacked on a silicon substrate, and the first silicon nitride film and the base silicon oxide film are stacked, leaving an island region. and a step of etching away a part of the silicon substrate by a dry etching method to form an opening, such that the edge of the opening of the first silicon nitride film extends inward from the side surface of the opening of the base silicon oxide film in a canopy shape. a second silicon nitride film is deposited on the silicon substrate, and a second silicon nitride film is deposited on the bottom surface of the opening by an anisotropic dry etching method. forming a second silicon nitride film on the surface and side surfaces of the island region; and selectively oxidizing the opening using the first and second silicon nitride films as a mask to form an isolation oxide film. Because it contains no oxidation in the lateral direction and has sufficient oxidation masking properties, it is possible to accurately and easily form a highly reliable oxide film isolation structure with high dimensional accuracy. It has this effect.
第１図ＡないしＤは従来の半導体装置の製造方
法を示す工程説明図、第２図ＡないしＧはこの発
明の一実施例の半導体装置の製造方法を示す工程
説明図、第３図ＡおよびＢはそれぞれ従来例と実
施例とを比較して示す効果の説明図である。
６…シリコン基板（半導体基板）、６ａ…島領
域、６ｂ…段差部、７…分離酸化膜、８…シリコ
ン酸化膜、８ａ，８′ａ…下地シリコン酸化膜、
８ｂ，８′ｂ…第２シリコン酸化膜、９…シリコ
ン窒化膜（耐酸化性膜）、９ａ，９′ａ…第１シリ
コン窒化膜、９ｂ，９′ｂ…第２シリコン窒化膜、
１０…レジスト。
1 A to D are process explanatory diagrams showing a conventional method for manufacturing a semiconductor device, FIGS. 2 A to G are process explanatory diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. B is an explanatory diagram of effects comparing the conventional example and the example. 6... Silicon substrate (semiconductor substrate), 6a... Island region, 6b... Step portion, 7... Isolation oxide film, 8... Silicon oxide film, 8a, 8'a... Base silicon oxide film,
8b, 8'b... second silicon oxide film, 9... silicon nitride film (oxidation resistant film), 9a, 9'a... first silicon nitride film, 9b, 9'b... second silicon nitride film,
10...Resist.
Claims (1)
よび第１シリコン窒化膜を積層形成し島領域を残
して前記第１シリコン窒化膜、下地シリコン酸化
膜およびシリコン基板の一部をドライエツチング
法によりエツチング除去し開口部を形成する工程
と、前記第１シリコン窒化膜の開口縁が前記下地
シリコン酸化膜の開口側面より内方にひさし状に
張り出すように前記下地シリコン酸化膜の開口側
面を湿式エツチング法によりサイドエツチングす
る工程と、シリコン基板上全面に第２シリコン窒
化膜を堆積形成するとともに異方性ドライエツチ
ング法により前記開口部の底面に堆積した第２シ
リコン窒化膜をエツチング除去して島領域の側面
に第２シリコン窒化膜を選択的に残存させる工程
と、前記第１、第２シリコン窒化膜をマスクとし
て前記開口部を選択酸化し分離酸化膜を形成する
工程とを含む半導体装置の製造方法。1. A base silicon oxide film and a first silicon nitride film are sequentially stacked on a silicon substrate, and a part of the first silicon nitride film, base silicon oxide film, and silicon substrate are removed by dry etching, leaving an island region. forming an opening, and wet-etching the opening side surface of the base silicon oxide film so that the edge of the opening of the first silicon nitride film extends inward from the opening side surface of the base silicon oxide film in a canopy shape. A step of side etching, depositing and forming a second silicon nitride film on the entire surface of the silicon substrate, and etching away the second silicon nitride film deposited on the bottom surface of the opening by an anisotropic dry etching method to form a side surface of the island region. A method for manufacturing a semiconductor device, comprising the steps of: selectively leaving a second silicon nitride film; and selectively oxidizing the opening using the first and second silicon nitride films as a mask to form an isolation oxide film.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19893481A JPS5898944A (en) | 1981-12-08 | 1981-12-08 | Semiconductor device and manufacture thereof |
| US06/660,255 US4563227A (en) | 1981-12-08 | 1984-10-12 | Method for manufacturing a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19893481A JPS5898944A (en) | 1981-12-08 | 1981-12-08 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5898944A JPS5898944A (en) | 1983-06-13 |
| JPH0336302B2 true JPH0336302B2 (en) | 1991-05-31 |
Family
ID=16399393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19893481A Granted JPS5898944A (en) | 1981-12-08 | 1981-12-08 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5898944A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4538343A (en) * | 1984-06-15 | 1985-09-03 | Texas Instruments Incorporated | Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking |
| US4561172A (en) * | 1984-06-15 | 1985-12-31 | Texas Instruments Incorporated | Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions |
| US4580330A (en) * | 1984-06-15 | 1986-04-08 | Texas Instruments Incorporated | Integrated circuit isolation |
| JPS6148934A (en) * | 1984-08-16 | 1986-03-10 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| US5182227A (en) * | 1986-04-25 | 1993-01-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| BE1007588A3 (en) * | 1993-09-23 | 1995-08-16 | Philips Electronics Nv | Process for the production of a semiconductor device having a semiconductor body with field isolation regions FORMED BY by an insulating material filled grooves. |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53120289A (en) * | 1977-03-30 | 1978-10-20 | Toshiba Corp | Manufacture of semiconductor device |
-
1981
- 1981-12-08 JP JP19893481A patent/JPS5898944A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53120289A (en) * | 1977-03-30 | 1978-10-20 | Toshiba Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5898944A (en) | 1983-06-13 |
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