JPH05109729A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05109729A JPH05109729A JP27115991A JP27115991A JPH05109729A JP H05109729 A JPH05109729 A JP H05109729A JP 27115991 A JP27115991 A JP 27115991A JP 27115991 A JP27115991 A JP 27115991A JP H05109729 A JPH05109729 A JP H05109729A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- wiring layer
- wiring
- layer
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の配線構造に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure for a semiconductor device.
【０００２】[0002]
【従来の技術】現在、半導体集積回路（ＩＣ，ＬＳＩ）
配線材料としては、拡散層、ポリシリコンおよびアルミ
ニュウムの３種類がおもに使われている。2. Description of the Related Art Currently, semiconductor integrated circuits (IC, LSI)
Three types of wiring materials are mainly used: diffusion layer, polysilicon, and aluminum.
【０００３】このような配線材料をもちいた半導体装置
の構造としては、図１のようものがある。図１において
第１導電型の不純物を含む半導体基板上に、第１絶縁膜
２を形成し、前記第１絶縁膜上にスハッタリングで堆積
させたアルミニュウムをフォトレジストをもちいパター
ニングし、ドライエッチングする事によりＡｌ配線層３
を形成する。前記Ａｌ配線層上に、ＣＶＤ法で形成した
シリコン窒化膜の第２絶縁膜層４を形成する。ここで素
子を微細化しようとして、図１の示すように、隣接した
前記Ａｌ配線層３が前記第２絶縁膜４の膜厚に対して十
分な距離がなくなると、前記第２絶縁膜層４の形状は図
１中に示すように、前記第２絶縁膜がＡｌ配線層間上部
で接触し、絶縁膜中に空洞５を残すような形状になる。A structure of a semiconductor device using such a wiring material is shown in FIG. In FIG. 1, a first insulating film 2 is formed on a semiconductor substrate containing impurities of the first conductivity type, and aluminum deposited by sputtering on the first insulating film is patterned using a photoresist and dry-etched. By Al wiring layer 3
To form. A second insulating film layer 4 of a silicon nitride film formed by a CVD method is formed on the Al wiring layer. Here, when the adjacent Al wiring layer 3 is not sufficiently separated from the film thickness of the second insulating film 4 as shown in FIG. 1 in an attempt to miniaturize the device, the second insulating film layer 4 is formed. 1, the second insulating film is in contact with the upper part of the Al wiring layer, leaving a cavity 5 in the insulating film.
【０００４】また前記Ａｌ配線層３側面の、前記第２絶
縁膜層４の縦方向への膜の付きまわりは、図１に示すよ
うに下方にいくほど細くなる。In addition, the attachment of the film on the side surface of the Al wiring layer 3 in the vertical direction of the second insulating film layer 4 becomes thinner as it goes downward as shown in FIG.
【０００５】[0005]
【発明が解決しようとする課題】前記のような絶縁膜中
に空洞５を残した構造においては、前記絶縁膜層２上に
フォトレジストを塗布しパターニングする場合、パター
ニング後の前記フォトレジストのベーク工程において前
記空洞５内のガスが熱膨張による圧力により、前記絶縁
膜層４の上部の膜の接触していない部分で、パターニン
グされた前記フォトレジストを吹き飛ばしてしまい、前
記フォトレジストをマスクにしエッチングした場合、前
記フォトレジストの吹き飛ばされた部分の前記絶縁膜層
４をエッチングしてしまい不良を起こす原因となる。In the structure in which the cavity 5 is left in the insulating film as described above, when the photoresist is applied on the insulating film layer 2 and patterned, the baking of the photoresist after patterning is performed. In the step, the gas in the cavity 5 is blown by the pressure due to the thermal expansion to blow off the patterned photoresist in a portion of the insulating film layer 4 which is not in contact with the film, and the photoresist is used as a mask for etching. In that case, the insulating film layer 4 in the blown-off portion of the photoresist is etched, which causes a defect.
【０００６】また前記の様に、前記第２絶縁膜層４の縦
方向の膜の付きまわりが悪いので、耐湿性が悪くなり水
分の進入による不良を起こす原因ともなる。Further, as described above, since the film adhesion in the vertical direction of the second insulating film layer 4 is poor, the moisture resistance is deteriorated, which may cause a defect due to the penetration of moisture.
【０００７】前記のような問題について、解決する一つ
の方法としてＡｌ配線層間の距離を前記Ａｌ配線上の絶
縁膜層４が接触しないだけの距離だけ離すという方法が
考えられる。しかし前記のような方法でこの問題を解決
しようとした場合、半導体装置の集積度を低下させてし
まう。As a method for solving the above problems, a method of separating the distance between Al wiring layers by a distance such that the insulating film layer 4 on the Al wiring does not contact can be considered. However, if an attempt is made to solve this problem by the method described above, the degree of integration of the semiconductor device will be reduced.
【０００８】そこで本発明は、Ａｌ配線層間の距離を変
えることなく前記Ａｌ配線層３上に形成される第２絶縁
膜層４の空洞部分をなくし、また前記Ａｌ配線層３側面
の前記第２絶縁膜層４の縦方向の膜の付きまわりを良く
することにある。Therefore, according to the present invention, the cavity portion of the second insulating film layer 4 formed on the Al wiring layer 3 is eliminated without changing the distance between the Al wiring layers, and the second side surface of the Al wiring layer 3 is eliminated. The purpose is to improve the coverage of the insulating film layer 4 in the vertical direction.
【０００９】[0009]
【課題を解決するための手段】半導体基板上に形成され
た第１絶縁膜、前記第１絶縁膜上に形成された第１導電
膜からなる配線層、前記第１導電膜からなる配線層上に
形成された第２絶縁膜層を有する半導体装置において、
前記１導電膜からなる配線層の形状が凸型であることを
特徴とする。A first insulating film formed on a semiconductor substrate, a wiring layer made of a first conductive film formed on the first insulating film, and a wiring layer made of the first conductive film. In a semiconductor device having a second insulating film layer formed on
It is characterized in that the wiring layer made of the one conductive film has a convex shape.
【００１０】[0010]
【実施例】以下、本発明のＡｌ配線層の形成方法の１実
施例を図面とともに説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for forming an Al wiring layer according to the present invention will be described below with reference to the drawings.
【００１１】図２は本発明を適用して形成したＡｌ配線
層および上記Ａｌ配線層上に形成される絶縁膜の断面図
を示す。 また図３（ａ）〜図３（ｅ）までは、図２中
の前記Ａｌ配線層を凸型に形成する過程の断面図を示し
たものである。FIG. 2 shows a sectional view of an Al wiring layer formed by applying the present invention and an insulating film formed on the Al wiring layer. 3 (a) to 3 (e) are sectional views showing a process of forming the Al wiring layer in FIG. 2 in a convex shape.
【００１２】なお図中の符号について、１は半導体基
板、２は第１絶縁膜、３はＡＬ配線層、４は第２絶縁膜
層、５は空洞部分、６はサイドウォール、７はフォトレ
ジストである。In the figures, 1 is a semiconductor substrate, 2 is a first insulating film, 3 is an AL wiring layer, 4 is a second insulating film layer, 5 is a cavity portion, 6 is a sidewall, and 7 is a photoresist. Is.
【００１３】以下図２の示す実施例を図３（ａ）〜図３
（ｅ）をもちい詳しく説明する。Hereinafter, the embodiment shown in FIG. 2 will be described with reference to FIGS.
A detailed description will be given using (e).
【００１４】図３（ａ）の示すように半導体基板上にＣ
ＶＤ法でシリコン酸化膜２を形成し、前記シリコン酸化
膜２上にスパッタリングで１６０００ÅのＡｌを堆積さ
せる。次に図３（ｂ）に示すように、前記Ａｌ上にフォ
トレジストを塗布し、投影露光法をもちいレジストをＡ
ｌ配線層で凸型になる部分にパターニングする。前記の
レジストパターニングを終えた後に、図３（ｃ）に示す
ように例えばＢＣｌ3−Ｃｌ2など塩素系のエッチングガ
スをもちい、Ａｌを１００００Åドライエッチングす
る。ドライエッチングを終えた後にフォトレジストを除
去し、再度フォトレジストを塗布し、前記塗布したフォ
トレジストを、ＣＨＦ3−Ｃ2Ｆ6などの弗素系エッチン
グガスをもちい異方性ドライエッチングで全面エッチバ
ックする事により、図３（ｄ）に示すように凸型に残し
たＡｌの側面にサイドウォールを形成する。この時、前
記フォトレジストの代わりにシリコン酸化膜を用いてサ
イドウォールを形成してもよい。As shown in FIG. 3A, C is formed on the semiconductor substrate.
A silicon oxide film 2 is formed by the VD method, and 16000Å Al is deposited on the silicon oxide film 2 by sputtering. Next, as shown in FIG. 3 (b), a photoresist is applied on the Al, and a resist is formed by using a projection exposure method.
Patterning is performed on the convex portion of the l wiring layer. After the resist patterning is completed, as shown in FIG. 3C, a chlorine-based etching gas such as BCl 3 —Cl 2 is used to dry etch Al by 10000Å. After the dry etching is finished, the photoresist is removed, the photoresist is coated again, and the coated photoresist is fully etched back by anisotropic dry etching using a fluorine-based etching gas such as CHF 3 -C 2 F 6. By doing so, a sidewall is formed on the side surface of the Al that is left in a convex shape as shown in FIG. At this time, a sidewall may be formed by using a silicon oxide film instead of the photoresist.
【００１５】その後、前記サイドウォールをマスクにし
て、前記Ａｌを前記塩素系のエッチングガスで前記サイ
ドウォール６に挟まれた凸型上部と、前記サイドウォー
ル６によるマスクのない凸型下部を同時に６０００Åド
ライエッチングする。最後にマスクとして用いた前記フ
ォトレジストを、硫酸剥離で除去することにより図３
（ｅ）に示すようなＡｌ配線層３を形成する。Thereafter, using the sidewall as a mask, a convex upper portion in which the Al is sandwiched between the sidewalls 6 by the chlorine-based etching gas and a maskless convex lower portion by the sidewall 6 are simultaneously 6000 Å. Dry etching. Finally, the photoresist used as a mask is removed by stripping with sulfuric acid.
The Al wiring layer 3 as shown in (e) is formed.
【００１６】前記のような工程でＡＬ配線層３を形成し
た後に、プラズマＣＶＤ法でシランとアンモニアを窒素
希釈したガスをもちい３００℃、０．９気圧の条件で１
００００Å堆積させたシリコン窒化膜の第２絶縁膜層４
を形成すると、ＡＬ配線層間上部の前記第２絶縁膜が接
触する事がなく図２の示すように、図１中に見られるよ
うな空洞５が形成されることはない。After the AL wiring layer 3 is formed by the above-mentioned process, a gas obtained by diluting silane and ammonia with nitrogen is used by plasma CVD method at 300 ° C. and 0.9 atm.
0000Å second insulating film layer 4 of deposited silicon nitride film
2 is formed, the second insulating film on the upper portion of the AL wiring layer does not come into contact with each other, and the cavity 5 as shown in FIG. 1 is not formed as shown in FIG.
【００１７】また前記ＡＬ配線層３を凸型に形成するこ
とにより、前記Ａｌ配線層３上に形成される前記第２絶
縁膜４にも段差ができるために前記Ａｌ配線層上部から
第１絶縁膜２までの縦方向の前記第２絶縁膜４の膜の付
きまわりが良くなる。Further, by forming the AL wiring layer 3 in a convex shape, a step can be formed also in the second insulating film 4 formed on the Al wiring layer 3, so that the first insulation is formed from the upper portion of the Al wiring layer. The coverage of the film of the second insulating film 4 in the vertical direction up to the film 2 is improved.
【００１８】また本発明では、配線層にＡＬ配線層の場
合について記載しているが、前記配線層がＡＬ配線層下
にＴｉＮなどの高融点金属化合物をもちいたバリアメタ
ル配線の場合や、ポリシリコン配線や、前記ポリシリコ
ン配線にＴｉ，Ｍｏなどの高融点金属化合物をもちいた
ポリサイド配線などでもよい、また前記第２絶縁膜２が
シリコン窒化膜の場合について記載されているが、シリ
コン酸化膜でもよい。また本発明では前記配線層がＡＬ
１層の場合について記載しているが、多層配線型の半導
体装置においても広く適用される。In the present invention, the case where the wiring layer is the AL wiring layer is described. However, when the wiring layer is a barrier metal wiring using a refractory metal compound such as TiN under the AL wiring layer, It may be a silicon wiring or a polycide wiring in which a refractory metal compound such as Ti or Mo is used for the polysilicon wiring. Further, the case where the second insulating film 2 is a silicon nitride film is described. But it's okay. In the present invention, the wiring layer is AL
Although the case of one layer is described, it is widely applied to a multi-layer wiring type semiconductor device.
【００１９】[0019]
【発明の効果】上述のような、本発明の第１導電膜から
なる配線層の形成方法によれば、前記第１導電膜からな
る配線層の形状を凸型にする事で、配線層間での絶縁膜
中の空洞の形成を防止することができるため、前記絶縁
膜層２上にフォトレジストを塗布しパターニングする場
合、パターニング後の前記フォトレジストのベーク工程
において、前記空洞５内のガスが熱膨張による圧力によ
り、前記絶縁膜層２の上部の膜の接触していない部分
で、パターニングされた前記フォトレジストを吹き飛ば
してしまい、前記フォトレジストをマスクにしエッチン
グした場合、前記フォトレジストの吹き飛ばされた部分
の前記絶縁膜層４をエッチングしてしまい不良を起こす
ことはない。As described above, according to the method of forming the wiring layer made of the first conductive film of the present invention, the wiring layer made of the first conductive film is formed into a convex shape so that the wiring layers are Since it is possible to prevent the formation of cavities in the insulating film, when the photoresist is applied on the insulating film layer 2 and patterned, in the baking process of the photoresist after patterning, the gas in the cavities 5 is Due to the pressure due to thermal expansion, the patterned photoresist is blown off at a portion of the insulating film layer 2 which is not in contact with the film, and when the photoresist is used as a mask for etching, the photoresist is blown off. There is no possibility that the insulating film layer 4 in the other part is etched and a defect is caused.
【００２０】また、前記第１導電膜からなる配線層上に
形成される、前記第２絶縁膜層の付まわりが良くなるた
めに耐湿性に優れた半導体装置を供給することができ
る。Further, since the second insulating film layer formed on the wiring layer formed of the first conductive film is well attached to the wiring layer, a semiconductor device having excellent moisture resistance can be supplied.
【００２１】また高集積化が進められて配線層間の距離
が微細化された段階でも応用できるという効果がある。Further, there is an effect that it can be applied even at a stage where the distance between wiring layers is miniaturized due to the progress of high integration.
【図１】 従来の半導体装置のＡＬ配線および絶縁膜構
造を示す縦断側面図。FIG. 1 is a vertical sectional side view showing an AL wiring and an insulating film structure of a conventional semiconductor device.
【図２】 本発明の実施例を示す縦断側面図。FIG. 2 is a vertical sectional side view showing an embodiment of the present invention.
【図３】 （ａ）〜（ｅ） 第１導電膜からなる配線層
を凸型に形成する過程を示す縦断断面図。3A to 3E are vertical cross-sectional views showing a process of forming a wiring layer made of a first conductive film in a convex shape.
１・・・・半導体基板 ２・・・・第１絶縁膜 ３・・・・ＡＬ配線層 ４・・・・第２絶縁膜 ５・・・・空洞部分 ６・・・・サイドウオール ７・・・・フォトレジスト 1 ... Semiconductor substrate 2 ... 1st insulating film 3 ... AL wiring layer 4 ... 2nd insulating film 5 ... Cavity part 6 ... Sidewall 7 ... ..Photoresist
Claims (1)
記第１絶縁膜上に形成された第１導電膜からなる配線
層、前記第１導電膜からなる配線層上に形成された第２
絶縁膜層を有する半導体装置において、前記第１導電膜
からなる配線層の形状が凸型であることを特徴とする半
導体装置。1. A first insulating film formed on a semiconductor substrate, a wiring layer made of a first conductive film formed on the first insulating film, and a wiring layer made of the first conductive film. Second
A semiconductor device having an insulating film layer, wherein the wiring layer made of the first conductive film has a convex shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27115991A JPH05109729A (en) | 1991-10-18 | 1991-10-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27115991A JPH05109729A (en) | 1991-10-18 | 1991-10-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05109729A true JPH05109729A (en) | 1993-04-30 |
Family
ID=17496163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27115991A Pending JPH05109729A (en) | 1991-10-18 | 1991-10-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05109729A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877095A (en) * | 1994-09-30 | 1999-03-02 | Nippondenso Co., Ltd. | Method of fabricating a semiconductor device having a silicon nitride film made of silane, ammonia and nitrogen |
-
1991
- 1991-10-18 JP JP27115991A patent/JPH05109729A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877095A (en) * | 1994-09-30 | 1999-03-02 | Nippondenso Co., Ltd. | Method of fabricating a semiconductor device having a silicon nitride film made of silane, ammonia and nitrogen |
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