JPH05109709A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05109709A
JPH05109709A JP27116091A JP27116091A JPH05109709A JP H05109709 A JPH05109709 A JP H05109709A JP 27116091 A JP27116091 A JP 27116091A JP 27116091 A JP27116091 A JP 27116091A JP H05109709 A JPH05109709 A JP H05109709A
Authority
JP
Japan
Prior art keywords
wiring layer
tungsten
wiring
layer
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27116091A
Other languages
Japanese (ja)
Inventor
Tatsuo Mizuno
達夫 水野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP27116091A priority Critical patent/JPH05109709A/en
Publication of JPH05109709A publication Critical patent/JPH05109709A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the operation speed by forming a wiring layer composed of a first conducting film in a T-type. CONSTITUTION:Tungsten is deposited to be 5000Angstrom thick by a sputtering method; photo resist is spread; the photo resist is patterned by using a projection alignment method; the photo resist is used as a mask, and patterning is so performed that the wiring width is 1.5mum and the wiring becomes T-shaped. After that, dry etching is performed by using chlorine based etching gas like BCl2-Cl2, and the photo resist which has been used as the mask is eliminated by sulfuric acid peeling. Thus a tungsten wiring layer 4 is formed. Thereby a semiconductor device of high operation speed can be supplied.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の配線構造に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure for a semiconductor device.

【0002】[0002]

【従来の技術】現在半導体集積回路(IC,LSI)配
線材料としては、拡散層、ポリシリコン及びアルミニュ
ウム等の金属の3種類がおもに使われている。
2. Description of the Related Art At present, three kinds of metals, such as diffusion layers, polysilicon, and aluminum, are mainly used as wiring materials for semiconductor integrated circuits (IC, LSI).

【0003】このような配線材料を用いた半導体装置と
しては、図1のようなものがある。図1に於て第1導電
型の不純物を含む半導体基板1上に、フォトレジストを
マスクとして第2導電型の不純物をイオン打ち込み法に
より不純物を注入し、熱拡散させることで拡散層2を形
成する。次に前記フォトレジストを硫酸剥離により除去
し、CVD法でタングステンを堆積させ前記タングステ
ンをフォトレジストを用いパターニングしドライエッチ
ングする事により、前記拡散層2上にタングステン配線
層を形成する。
A semiconductor device using such a wiring material is shown in FIG. In FIG. 1, a diffusion layer 2 is formed on a semiconductor substrate 1 containing impurities of the first conductivity type by implanting the impurities of the second conductivity type by an ion implantation method using a photoresist as a mask and thermally diffusing the impurities. To do. Next, the photoresist is removed by stripping with sulfuric acid, tungsten is deposited by the CVD method, and the tungsten is patterned using the photoresist and dry-etched to form a tungsten wiring layer on the diffusion layer 2.

【0004】[0004]

【発明が解決しようとする課題】しかしながら前記のよ
うな構造を持つ半導体装置に於て、素子を微細化しよう
とした場合、前記タングステン配線層4の幅を小さくす
る必要がある。しかし、前記タングステン配線層4の幅
を小さくしても配線中を流れる電流は変わらないため、
配線中の電流密度は増加する。前記配線中の電流密度が
増加すると素子の信頼性を低下させてしまう。また図1
のように前記タングステン配線層4が前記拡散層2上に
ある場合、前記タングステン配線層4と前記拡散層2の
間の層か容量により素子の動作速度を低下させてしま
う。
However, in the semiconductor device having the above structure, when the element is to be miniaturized, it is necessary to reduce the width of the tungsten wiring layer 4. However, even if the width of the tungsten wiring layer 4 is reduced, the current flowing in the wiring does not change,
The current density in the wiring increases. If the current density in the wiring increases, the reliability of the device will deteriorate. See also FIG.
When the tungsten wiring layer 4 is on the diffusion layer 2 as described above, the operating speed of the device is reduced due to the capacitance between the tungsten wiring layer 4 and the diffusion layer 2.

【0005】前述のような問題を解決するためには、
電流密度の減少のため、前記タングステン配線層4の幅
を変えずに配線層の厚さを増やすことで断面積を増加さ
せる、層間容量の減少のために、前記拡散層2上に前
記タングステン配線層4を形成しない等の方法が考えら
れる。 しかしのような方法では、タングステン配線
4と第1絶縁膜層3との接触面積が同じなのに対して、
前記タングステン配線層4の厚さが厚くなるので、配線
層がエッチング後のフォトレジスト除去のための硫酸剥
離や、洗浄工程などで接触面が剥離して配線層が倒れて
しまうという不良の原因となる等の問題がある。また仮
にの問題が解決された場合でも、のような方法で
は、素子の微細化という観点から考えると、配線位置を
選択的に形成する方法はふさわしくない。
In order to solve the above problems,
The cross-sectional area is increased by increasing the thickness of the wiring layer without changing the width of the tungsten wiring layer 4 to reduce the current density, and the tungsten wiring is formed on the diffusion layer 2 to reduce the interlayer capacitance. A method such as not forming the layer 4 is conceivable. However, in such a method, the contact area between the tungsten wiring 4 and the first insulating film layer 3 is the same,
Since the tungsten wiring layer 4 becomes thicker, it causes a defect such as sulfuric acid peeling for removing the photoresist after the wiring layer is etched, or a contact surface is peeled off in a cleaning process to collapse the wiring layer. There is a problem such as becoming. Even if the problem is solved, such a method is not suitable for selectively forming wiring positions from the viewpoint of device miniaturization.

【0006】そこで本発明の目的は、素子の集積度を低
下することなく、しかも配線層の信頼性を損なわず、な
おかつ層間容量を減少させることで動作速度を速くする
ことにある。
Therefore, an object of the present invention is to speed up the operation speed by reducing the degree of integration of the device, the reliability of the wiring layer, and the interlayer capacitance.

【0007】[0007]

【課題を解決するための手段】半導体基板上に形成され
た第1絶縁膜、前記第1絶縁膜上に形成された第1導電
膜からなる配線層を有する半導体装置に於て、前記第1
導電膜からなる配線層の形状をT字型であることをを特
徴とする半導体装置。
A semiconductor device having a wiring layer formed of a first insulating film formed on a semiconductor substrate and a first conductive film formed on the first insulating film,
A semiconductor device having a T-shaped wiring layer formed of a conductive film.

【0008】[0008]

【実施例】以下、本発明のタングステン配線層の形成方
法の1実施例を図面と共に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for forming a tungsten wiring layer according to the present invention will be described below with reference to the drawings.

【0009】図2は本発明を適用して形成したタングス
テン配線層の縦断側面図を示したものである。また図3
(a)〜図3(c)までは、図2中の前記タングステン
配線層4をT形に形成する過程を示した縦断側面図であ
る。
FIG. 2 is a vertical side view of a tungsten wiring layer formed by applying the present invention. See also FIG.
FIGS. 3A to 3C are vertical cross-sectional side views showing a process of forming the tungsten wiring layer 4 in FIG. 2 into a T shape.

【0010】なお図中の符号について、1は半導体基
板、2は拡散層、3は第1絶縁膜、4はタングステン配
線層である。
In the figures, 1 is a semiconductor substrate, 2 is a diffusion layer, 3 is a first insulating film, and 4 is a tungsten wiring layer.

【0011】以下図2の示す実施例を図3(a)〜図3
(c)を用い詳しく説明する。
Hereinafter, the embodiment shown in FIG. 2 will be described with reference to FIGS.
A detailed description will be given using (c).

【0012】図3(a)に示すように、第1導電型の不
純物半導体基板1上にフォトレジストを塗布し、投影露
光法を用い前記フォトレジストをパターニングした後
に、第2導電型の不純物をイオン打ち込み法を用い前記
半導体基板上1に注入し、前記半導体基板を窒素雰囲気
中で、1000゜C、30分アニールする事により拡散層
2を形成する。次に前記フォトレジストを硫酸剥離で除
去した後に、CVD法で4000Åのシリコン酸化膜を
堆積させ、第1絶縁膜層3を形成する。
As shown in FIG. 3A, a photoresist is coated on the impurity semiconductor substrate 1 of the first conductivity type, the photoresist is patterned by a projection exposure method, and then impurities of the second conductivity type are removed. Implantation is performed on the semiconductor substrate 1 by using an ion implantation method, and the semiconductor substrate is annealed in a nitrogen atmosphere at 1000 ° C. for 30 minutes to form a diffusion layer 2. Next, the photoresist is removed by stripping with sulfuric acid, and then a 4000 Å silicon oxide film is deposited by a CVD method to form a first insulating film layer 3.

【0013】その後フォトレジストを塗布し、投影露光
法を用い前記フォトレジストをパターニングした後に前
記フォトレジストをマスクにして、CHF3−C26
の弗素系のエッチングガスを用い、幅0.5μm、深さ
2000∂ドライエッチングする。そして硫酸剥離でマ
スクに用いた上記フォトレジストを除去した後を図3
(b)に示す。
After that, a photoresist is applied, and the photoresist is patterned by a projection exposure method. After that, the photoresist is used as a mask, and a fluorine-based etching gas such as CHF 3 --C 2 F 6 is used to form a photoresist film having a width of 0. 5 μm, depth 2000 ∂ dry etching. Then, after removing the photoresist used for the mask by sulfuric acid stripping, FIG.
It shows in (b).

【0014】次に、図3(c)に示すように、スパッタ
リング法でタングステンを5000Å堆積させ、その後
フォトレジストを塗布し、投影露光法を用い前記フォト
レジストをパターニングした後に前記フォトレジストを
マスクにして、配線幅1.5μmで、配線形状がT字に
なるようにパターニングする。その後BCl2−Cl2
の塩素系のエッチングガスを用いドライエッチングし、
マスクに用いた前記フォトレジストを硫酸剥離で除去す
ることにより、図2に示すような前記タングステン配線
層4を形成する。
Next, as shown in FIG. 3C, 5000 Å of tungsten is deposited by a sputtering method, a photoresist is applied thereafter, and the photoresist is patterned by a projection exposure method. Then, the photoresist is used as a mask. Then, patterning is performed so that the wiring shape has a T shape with a wiring width of 1.5 μm. After that, dry etching is performed using a chlorine-based etching gas such as BCl 2 —Cl 2 ,
By removing the photoresist used as the mask by sulfuric acid peeling, the tungsten wiring layer 4 as shown in FIG. 2 is formed.

【0015】前記のような工程で、T字型タングステン
配線層4を形成した場合、図1に示すような従来の長方
形のタングステン配線幅が、本発明に実施例と同じ1.
5μmで、また第1絶縁膜層の膜厚が2000Åとして
考えると、前記タングステン配線層4と前記拡散層2の
間に生ずる層間容量は、前記タングステン配線層4をT
字型に形成した場合、従来の2/3に減少する。さらに
前記タングステン配線層4をT字型に形成することによ
り、断面積は、7.5μm2 から8.5μm2に増加す
ることにより、前記タングステン配線層4に同一の電流
を流した場合電流密度は15/17倍に減少する。
When the T-shaped tungsten wiring layer 4 is formed by the above steps, the conventional rectangular tungsten wiring width as shown in FIG.
Assuming that the thickness of the first insulating film layer is 5 μm and the thickness of the first insulating film layer is 2000 Å, the interlayer capacitance generated between the tungsten wiring layer 4 and the diffusion layer 2 is T
When it is formed in a letter shape, it is reduced to 2/3 of the conventional one. Further, by forming the tungsten wiring layer 4 into a T-shape, the cross-sectional area is increased from 7.5 μm 2 to 8.5 μm 2 , so that the same current density is obtained when the same current is applied to the tungsten wiring layer 4. Is reduced by 15/17 times.

【0016】また本発明では前記タングステン配線層4
が、前記第1絶縁膜3中に埋め込まれた形で形成されて
いるため、エッチング後のフォトレジスト除去のための
硫酸剥離や洗浄の工程で、前記タングステン配線層4が
前記第1絶縁膜3との接触面が剥離して、倒れてしまう
ことは言うまでもない。
In the present invention, the tungsten wiring layer 4 is also used.
However, since the tungsten wiring layer 4 is formed so as to be embedded in the first insulating film 3, the tungsten wiring layer 4 is removed from the first insulating film 3 in a step of removing sulfuric acid for cleaning the photoresist after etching and cleaning. It goes without saying that the contact surface with and peels off and falls.

【0017】また本発明では配線層にタングステンを用
いた場合について記載しているが、ポリシリコン配線や
Al配線、ポリシリコン上にMoや、W,Ti等の高融
点金属化合物を堆積させ900゜Cから1000゜C程度の
高温でシリサイド化させた配線でもよい。
Further, although the present invention describes the case where tungsten is used for the wiring layer, a high melting point metal compound such as Mo, W, or Ti is deposited on polysilicon wiring, Al wiring, or polysilicon to 900 °. The wiring may be silicided at a high temperature of about C to 1000 ° C.

【0018】また本発明では、タングステン配線層4下
の導電膜を半導体基板上に形成した拡散層2を用い説明
したが、前記配線4下にさらに配線が存在する多層配線
型の半導体装置に於いても広く適用される。
In the present invention, the diffusion layer 2 in which the conductive film under the tungsten wiring layer 4 is formed on the semiconductor substrate has been described. However, in a multi-layer wiring type semiconductor device in which wiring is further present under the wiring 4. Widely applied.

【0019】[0019]

【発明の効果】このような、本発明の第1導電膜からな
る配線層の形成方法によれば、前記第1導電膜の形をT
字型に形成することで第1導電膜幅を変えることなく、
配線層の信頼性を損なわず、前記第1導電膜からなる配
線層の電流密度を減少させ、なおかつ層間容量を減少さ
せることで動作速度の速い半導体装置を供給することが
できる。
According to the method of forming the wiring layer made of the first conductive film of the present invention, the shape of the first conductive film is T.
By forming it in the shape of a letter, without changing the width of the first conductive film,
By reducing the current density of the wiring layer formed of the first conductive film and reducing the interlayer capacitance without impairing the reliability of the wiring layer, a semiconductor device having a high operating speed can be supplied.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の半導体装置のタングステン配線構造を示
す縦断側面図。
FIG. 1 is a vertical cross-sectional side view showing a tungsten wiring structure of a conventional semiconductor device.

【図2】本発明の実施例を示す縦断側面図。FIG. 2 is a vertical sectional side view showing an embodiment of the present invention.

【図3】(a)〜(c) 第1導電膜からなる配線層を
T字型に形成する工程を示す縦断断面図。
3A to 3C are vertical cross-sectional views showing a process of forming a wiring layer made of a first conductive film into a T-shape.

【符号の説明】[Explanation of symbols]

1・・・・・半導体基板 2・・・・・拡散層 3・・・・・第1絶縁膜層 4・・・・・タングステン配線層 5・・・・・フォトレジスト 1-semiconductor substrate 2--diffusion layer 3--first insulating film layer 4--tungsten wiring layer 5--photoresist

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に形成された第1絶縁膜、前
記第1絶縁膜上に形成された第1導電膜からなる配線層
を有する半導体装置に於て、前記第1導電膜からなる配
線層の形状がT字型であることを特徴とする半導体装
置。
1. A semiconductor device having a first insulating film formed on a semiconductor substrate and a wiring layer made of a first conductive film formed on the first insulating film, wherein the semiconductor device is made of the first conductive film. A semiconductor device having a T-shaped wiring layer.
JP27116091A 1991-10-18 1991-10-18 Semiconductor device Pending JPH05109709A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27116091A JPH05109709A (en) 1991-10-18 1991-10-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27116091A JPH05109709A (en) 1991-10-18 1991-10-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05109709A true JPH05109709A (en) 1993-04-30

Family

ID=17496178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27116091A Pending JPH05109709A (en) 1991-10-18 1991-10-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05109709A (en)

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