JP2004158821A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-precision hole and trench fabrication process in organic siloxane insulating film that gives no damage by an asher to the organic siloxane insulating film and causes none of problems of shape deterioration or foreign matter. <P>SOLUTION: On the organic siloxane insulating film, a 2nd insulating film and an inorganic thin film soluble in a solution are formed. This organic thin film is used as a hard mask to process the organic siloxane insulating film. The hard mask is removed with a dissolving solution after the processing. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for high-speed operation and low power consumption.
[0002]
[Prior art]
With the miniaturization of semiconductor elements, the parasitic capacitance of the Cu wiring becomes equal to the input / output capacitance of the transistor itself, which is a rate-determining factor for element operation. Therefore, studies for introducing an insulating film having a lower relative dielectric constant than conventional silicon oxide (relative dielectric constant of 〜4) have been actively conducted.
[0003]
An organic siloxane-based insulating film is mainly studied as a low dielectric constant film. The organic siloxane-based insulating film is a film having a Si-R bond (R is an organic group) and a Si-O-Si bond as main components. It is formed by chemical vapor deposition (CVD) or spin coating. R is CH, which has excellent heat resistance. ₃ Is generally used. Other components may include Si-H and Si-C-Si. The relative dielectric constant of the organosiloxane insulating film is usually about 2.8 to 3.3, but the relative dielectric constant can be reduced to 2.5 or less by making the film porous.
[0004]
As a Cu wiring forming method, a damascene method is generally used. In the damascene method, first, grooves and hole patterns corresponding to wirings and connection holes are formed in an insulating film, then barrier metal and Cu are embedded in the pattern, and unnecessary barrier metal and Cu outside the pattern are chemically mechanically polished (CMP). Is a way to get rid of it. In the damascene method, a method of simultaneously burying Cu in both the wiring and the pattern of the connection hole is called a dual damascene method.
[0005]
In order to apply an organic siloxane-based insulating film to a Cu wiring, it is necessary to process the above-mentioned groove or hole pattern. There are the following two methods for processing a slot pattern on an organic siloxane-based insulating film. First, there is a resist mask method in which an organic siloxane-based insulating film is directly processed using a resist pattern as a mask. The second is a hard mask method in which a resist pattern is once transferred to a hard mask, the resist is removed, and then the underlying organic siloxane-based insulating film is processed using the hard mask.
[0006]
As the hard mask, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or a stacked film thereof is generally studied. Patent Document 1 below discloses a method of using aluminum oxide as a hard mask, and Patent Document 2 below discloses metals such as Al, Ta, and Ti, and oxide films, nitride films, and carbonized films thereof. A method of using a film as a hard mask is disclosed.
[0007]
Further, a method is disclosed in which a soluble thin film is formed below a hard mask, and after processing the organic siloxane-based insulating film, the soluble thin film is dissolved using a dissolving solution, and the hard mask is lifted off and removed (for example, disclosed). , Patent Document 3). Examples of the hard mask include Si, W, Al, Ni, Ti, Ca, and aluminum oxide, and examples of the soluble thin film include tungsten oxide and aluminum oxide.
[0008]
[Patent Document 1]
JP 2000-208444 A
[Patent Document 2]
JP-A-2000-150463
[Patent Document 3]
JP 2001-15479 A
[0009]
[Problems to be solved by the invention]
The resist mask method has the following two problems.
The first is the deterioration of the organic siloxane-based insulating film when the resist is removed. In the resist mask method, organic components in the organic siloxane-based insulating film are decomposed by an asher treatment (oxygen plasma treatment) for removing the resist. As a result, problems such as an increase in relative permittivity and deterioration in breakdown voltage occur. In the case of an organic siloxane-based insulating film having a relative dielectric constant of about 2.8 to 3.3, the oxidizing power of the plasma can be reduced by lowering the pressure of the asher treatment or the ammonia plasma treatment to reduce the damage. is there.
[0010]
However, in the case of a porous film having a relative dielectric constant of 2.5 or less, the plasma does not easily penetrate into the film, so that damage is not reduced. The second problem is the dry etching resistance of the resist for ArF lithography used at the 90 nm node and beyond. The resist for ArF lithography generally has low fluorine plasma resistance. However, in the resist mask method, the resist is exposed to a fluorine-based plasma while the organic siloxane-based insulating film is being etched. As a result, the shape of the resist is deteriorated, and the shape is transferred to the organic siloxane-based insulating film.
[0011]
On the other hand, in the hard mask method, since the organic siloxane-based insulating film is not exposed to the asher treatment, there is no problem of damage. The problem depends on the hard mask material.
In a hard mask material (such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbonitride) which is generally studied, the selectivity with the organic siloxane-based insulating film is at most about 2 to 6, Precise processing is not possible.
[0012]
With a metal hard mask, the selectivity is sufficiently high. The first problem is that the base cannot be seen due to the reflection of the metal surface, and positioning cannot be performed in the lithography process. Second, the shape may be deteriorated when the metal hard mask is removed after processing to prevent a short circuit between adjacent wirings.
[0013]
Even with a hard mask of metal oxide, nitride, or the like, the selectivity is sufficiently high. The first problem is that it is necessary to remove a metal oxide having a high dielectric constant in order to reduce the wiring capacitance. Patent Literature 1 does not remove the hard mask, and Patent Literature 2 does not disclose a specific method for removing the hard mask. Patent Literature 3 discloses a method of removing a hard mask by lift-off. However, since the hard mask itself does not dissolve by lift-off, the residue is likely to become a foreign substance and adhere again, which is not practical. The second problem is the selectivity of the hard mask when processing the base. Since a metal oxide or the like is difficult to be etched, a high bias is required for the etching. As disclosed in Patent Literature 1 and Patent Literature 2, when the base of the hard mask is an organic siloxane-based insulating film, the selectivity to metal oxide or the like is 0.5 or less. In particular, the selection ratio of a porous material is low, and a deep groove is formed due to overetching of the hard mask processing, which causes a problem of damage similar to that when using a resist mask when removing the resist.
[0014]
An object of the present invention is to provide a highly accurate hole groove processing process for an organic siloxane-based insulating film, which does not damage the organic siloxane-based insulating film due to asher, and does not cause a problem of shape deterioration or foreign matter. It is in.
[0015]
[Means for Solving the Problems]
The object is to form a second insulating film on an organic siloxane insulating film, form a soluble inorganic thin film soluble in a solution on the second insulating film, and use the soluble thin film as a hard mask to form the organic siloxane insulating film. It can be solved by processing. After the processing of the organic siloxane-based insulating film, the hard mask is removed with a solution without causing shape deterioration.
[0016]
If the soluble inorganic thin film is a metal oxide film, an oxynitride film, or a nitride film, a sufficiently high selectivity to the organic siloxane-based insulating film can be obtained. Among them, aluminum oxide and aluminum oxynitride are desirable. These can be formed by a coating method, but are preferably formed by a sputtering method or a reactive sputtering method in order to obtain a higher selectivity. In addition, since aluminum oxynitride has an ultraviolet absorbing property, there is an advantage that an antireflection film in a lithography step can be eliminated by adjusting the film thickness.
[0017]
Aluminum oxide and aluminum oxynitride are soluble in a solution containing fluorine, such as dilute hydrofluoric acid and ammonium fluoride. In order to obtain a practical dissolution (removal) rate without affecting the underlying Cu or the organic siloxane-based insulating film, the fluorine concentration of the solution is desirably 0.0005% or more and 0.5% or less.
[0018]
The second insulating film is any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbonitride that has an etching selectivity higher than that of the organic siloxane-based insulating film while processing the hard mask. Is desirable. Among them, silicon oxide has the highest selectivity. On the other hand, silicon carbide has the highest adhesiveness to the underlying organic siloxane-based insulating film. Therefore, a stacked film in which silicon oxide is formed on silicon carbide is more desirable.
[0019]
In addition, when forming an organic siloxane-based insulating film, if a Cu wiring or a connection hole is exposed on the base, Cu diffusion barrier property is set so that Cu and the organic siloxane-based insulating film are not in direct contact with each other and a reliability problem does not occur. After forming any of silicon nitride, silicon oxynitride, silicon carbide, and silicon carbonitride, it is desirable to form an organic siloxane-based insulating film.
[0020]
Further, for processing the hard mask, Cl is used. ₂ Or BCl ₃ For example, it is desirable to use a gas containing at least chlorine. In particular, a resist for ArF lithography has a strong chlorine plasma resistance, so that deterioration in the shape of the resist can be suppressed.
[0021]
It is desirable to remove the hard mask before embedding a metal such as Cu in the pattern. This is because if a metal is buried and CMP is performed in a state where the hard mask is present, and then the hard mask is removed with a solution, a step is generated. Although it is possible to remove the hard mask by CMP itself, a step called dishing or erosion occurs due to an increase in the CMP time.
[0022]
When using a dual damascene method in which Cu is simultaneously buried in both the upper wiring pattern and the connection hole pattern after the formation, the respective patterns are formed on the soluble inorganic thin film and the sacrificial film formed thereon to remove the resist. In advance, this laminated film pattern may be transferred onto the organic siloxane-based insulating film. Wiring and connection holes can be formed by a dual damascene method without exposing the organic siloxane-based insulating film to ashing at all.
[0023]
This sacrificial film needs to be removed at the same time as the organic siloxane-based insulating film is being patterned. For this purpose, a film containing 10% or more of Si is desirable. In addition, the sacrificial film needs to have a small dimensional change due to shrinkage when ashing is performed. For this purpose, a hydrogenated siloxane-based material having a smaller shrinkage than an organic siloxane such as methylsiloxane is desirable.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a specific description will be given using examples.
<Example 1>
A Cu multilayer wiring of a semiconductor device was formed by a single damascene method.
First, an on-gate interlayer insulating film 1 and a contact 2 were formed on a semiconductor substrate 0 on which a transistor was formed (FIGS. 1 and 2). Then, an organic siloxane-based insulating film 112 having a relative dielectric constant of 2.9 and a silicon oxide film 113 were formed to a thickness of 250 nm and a silicon oxide film 113 by a plasma CVD method, and an aluminum oxide film 121 was formed to a thickness of 30 nm by a reactive sputtering method. Further, an antireflection film 122 and an ArF resist 123 were formed, and a lower layer wiring pattern 132 was formed by ArF lithography (FIG. 3). The antireflection film 122 and the aluminum oxide 121 were processed using the resist 123 as a mask (FIG. 4). For processing aluminum oxide, BCl ₃ Dry etching using a mixed gas of Ar and Ar was used. The shape deterioration of the ArF resist was small. The depression of the silicon oxide 113 due to overetching was 15 nm or less, and the underlying organic siloxane-based insulating film 112 was not exposed. Ashing was performed using oxygen plasma to remove the antireflection film 122 and the ArF resist 123 (FIG. 5). Using aluminum oxide 121 as a hard mask, silicon oxide 113 and organosiloxane insulating film 112 were processed (FIG. 6). CHF for etching ₃ And N ₂ Was used. The selectivity between the organic siloxane-based insulating film 112 and the aluminum oxide 121 was 20. Further commercially available NH ₄ Post-cleaning was performed using an F-containing acidic cleaning solution, and aluminum oxide 121 was dissolved and removed together with the etching residue (FIG. 7). The removal rate of aluminum oxide 121 with this cleaning solution was 8 nm / min. Next, a barrier metal 143 and Cu 144 were formed in the pattern by a damascene method in which a directional sputtering method, a plating method, and a CMP method were combined to form a lower wiring (FIG. 8). FIG. 9 shows a top view in this state. The cross-sectional view between AB corresponds to FIG.
[0025]
Further, a silicon insulating film 211 having a thickness of 20 nm, an organic siloxane insulating film 212 having a thickness of 250 nm and a silicon oxide film 213 having a thickness of 80 nm were formed by a plasma CVD method, and an aluminum oxide film 221 was formed to have a thickness of 30 nm by a reactive sputtering method. (FIG. 10). A connection hole pattern 231 was formed by the same method as described above, and a barrier metal 241 and Cu 242 were formed in the pattern by a damascene method to form an interlayer connection (FIGS. 11 to 15). FIG. 16 shows a top view in this state. A cross-sectional view between AB corresponds to FIG.
[0026]
Further, 20 nm of a silicon insulating film 214 of a barrier insulating film, 250 nm of an organic siloxane insulating film 215 and 80 nm of a silicon oxide film 216 were formed by a plasma CVD method, and an aluminum oxide film of 30 nm was formed by a reactive sputtering method. An upper layer wiring pattern was formed by the same method as described above, and a barrier metal 243 and Cu 244 were formed in the pattern by a damascene method to form an upper layer wiring (FIG. 17). FIG. 18 shows a top view in this state. A cross-sectional view taken along the line AB corresponds to FIG.
The electrical characteristics between adjacent wirings were evaluated, but no increase in dielectric constant or deterioration in breakdown voltage due to damage to the organic siloxane insulating film was found.
[0027]
In this example, a two-layer wiring was prototyped again on the substrate by replacing the silicon carbonitrides 214 and 211 of the barrier insulating film with silicon nitride, silicon oxynitride, and silicon carbide.
[0028]
<Example 2>
In Example 1 described above, a dilute hydrofluoric acid solution was used instead of the solution used for removing aluminum oxide. FIG. 19 shows the relationship between the concentration of dilute hydrofluoric acid and the removal rate of aluminum oxide. At a fluorine concentration of 0.0005% or more, a practical removal rate of 3 nm / min or more was obtained. Further, when the fluorine concentration is higher than 0.5%, the underlying Cu is roughened, and the interface between Cu and the barrier insulating film or the barrier metal is etched. The wiring to which the diluted hydrofluoric acid solution of 0.0005% or more and 0.5% or less showed characteristics equivalent to those of the first embodiment. A diluted hydrofluoric acid solution was used instead of the solution used for removing aluminum oxide. The electrical characteristics between adjacent wirings of the formed wiring were evaluated, but no increase in dielectric constant or deterioration in breakdown voltage due to damage to the organic siloxane-based insulating film was found.
[0029]
<Example 3>
In Example 1, the organic siloxane-based insulating film was changed to a porous organic siloxane-based insulating film having a relative dielectric constant of 2.5, and a two-layer wiring was similarly produced on a trial basis. At this time, a 0.005% diluted hydrofluoric acid solution was applied. The electrical characteristics between adjacent wirings of the formed wiring were evaluated, but no increase in dielectric constant or deterioration in breakdown voltage due to damage to the organic siloxane-based insulating film was found.
[0030]
<Example 4>
A Cu multilayer wiring of a semiconductor device was formed by a dual damascene method.
First, on the lower wiring of FIG. 8, 20 nm of silicon carbide nitride 211 as a barrier insulating film, 500 nm of an organic siloxane insulating film 212 having a relative dielectric constant of 2.9, and 80 nm of a silicon oxide film 213 are formed by a plasma CVD method. Then, an aluminum oxide film 211 having a thickness of 30 nm was formed by a reactive sputtering method. Further, an antireflection film 222 and an ArF resist 223 were formed, and a connection hole pattern 231 was formed by ArF lithography (FIG. 20). The antireflection film 222 and the aluminum oxide 221 were processed using the resist 223 as a mask (FIG. 21). For processing aluminum oxide, BCl ₃ Dry etching using a mixed gas of Ar and Ar was used. The shape deterioration of the ArF resist was small. The depression of the silicon oxide 213 due to overetching was 15 nm or less, and the underlying organic siloxane-based insulating film 212 was not exposed. Ashing was performed using oxygen plasma to remove the antireflection film 222 and the ArF resist 223 (FIG. 22). Using the aluminum oxide 221 as a hard mask, the silicon oxide 213 and part of the organic siloxane-based insulating film 212 were processed (FIG. 23). CHF for etching ₃ And N ₂ Was used. The selectivity between the organic siloxane-based insulating film 212 and the aluminum oxide 221 was 20.
[0031]
Next, an antireflection film 224 and an ArF resist 225 were formed, and an upper layer wiring pattern 232 was formed by ArF lithography (FIG. 24). The antireflection film 224 and the aluminum oxide 221 were processed using the resist 225 as a mask (FIG. 25). Ashing was performed to remove the antireflection film 224 and the ArF resist 225 (FIG. 26). In this ashing, low-pressure oxygen plasma of 10 mTorr was used to minimize damage to the organic siloxane-based insulating film 212. Using aluminum 221 as a hard mask, silicon oxide 213, organic siloxane-based insulating film 212, and silicon carbonitride film 211 were processed (FIG. 27). CHF for etching ₃ And N ₂ Was used. The selectivity between the organic siloxane-based insulating film 212 and the aluminum oxide 221 was 20. Further commercially available NH ₄ Post-cleaning was performed using an acidic cleaning solution containing F, and aluminum oxide 221 was dissolved and removed together with the etching residue (FIG. 28). The removal rate of aluminum oxide 221 with this cleaning solution was 8 nm / min. Next, a barrier metal 241 and a Cu 242 were formed in the pattern by a damascene method in which a directional sputtering method, a plating method, and a CMP method were combined to form upper layer wirings and interlayer connections (FIG. 29).
The electrical characteristics between adjacent wirings were evaluated, but no increase in dielectric constant or deterioration in breakdown voltage due to damage to the organic siloxane insulating film was found.
[0032]
In this example, a two-layer wiring was prototyped again on the substrate, replacing the silicon carbonitride 211 of the barrier insulating film with silicon nitride, silicon oxynitride, and silicon carbide.
[0033]
<Example 5>
A Cu multilayer wiring of a semiconductor device was formed by a dual damascene method.
First, on the lower wiring of FIG. 8, a silicon insulating film 211 having a barrier insulating film of 20 nm, an organic siloxane-based insulating film 212 having a relative dielectric constant of 2.9, and a silicon oxide film 213 are formed by plasma CVD. Then, an aluminum oxide film 211 having a thickness of 30 nm was formed by a reactive sputtering method. Further, an antireflection film 224 and an ArF resist 225 were formed, and an upper layer pattern 232 was formed by ArF lithography (FIG. 30). The antireflection film 224 and the aluminum oxide 221 were processed using the resist 225 as a mask (FIG. 31). For processing aluminum oxide, BCl ₃ Dry etching using a mixed gas of Ar and Ar was used. The shape deterioration of the ArF resist was small. The depression of the silicon oxide 213 due to overetching was 15 nm or less, and the underlying organic siloxane-based insulating film 212 was not exposed. Ashing was performed using oxygen plasma to remove the antireflection film 224 and the ArF resist 225 (FIG. 32).
[0034]
Next, an antireflection film 222 and an ArF resist 223 are formed, and a connection hole pattern 231 is formed by ArF lithography (FIG. 33). The part was processed (FIG. 34). Further ashing was performed to remove the antireflection film 222 and the ArF resist 223 (FIG. 35). In this ashing, low-pressure oxygen plasma of 10 mTorr was used to minimize damage to the organic siloxane-based insulating film 212. Using aluminum oxide 221 as a hard mask, silicon oxide 213, organic siloxane-based insulating film 212, and silicon carbonitride film 211 were processed (FIG. 36). CHF for etching ₃ And N ₂ Was used. The selectivity between the organic siloxane-based insulating film 212 and the aluminum oxide 221 was 20. Further commercially available NH ₄ Post-cleaning was performed using an F-containing acidic cleaning solution, and aluminum oxide 221 was dissolved and removed together with the etching residue (FIG. 37). The removal rate of aluminum oxide 221 with this cleaning solution was 8 nm / min. Next, a barrier metal 241 and a Cu 242 were formed in the pattern by a damascene method in which a directional sputtering method, a plating method, and a CMP method were combined, thereby forming an upper wiring and an interlayer connection (FIG. 38).
The electrical characteristics between adjacent wirings were evaluated, but no increase in dielectric constant or deterioration in breakdown voltage due to damage to the organic siloxane insulating film was found.
[0035]
In this example, a two-layer wiring was prototyped again on the substrate, replacing the silicon carbonitride 211 of the barrier insulating film with silicon nitride, silicon oxynitride, and silicon carbide.
[0036]
Further, in this example, the organic siloxane-based insulating film 212 was changed to a porous organic siloxane-based insulating film having a relative dielectric constant of 2.5, and a two-layer wiring was similarly produced on a trial basis. At this time, a 0.005% diluted hydrofluoric acid solution was applied. After FIG. 34, instead of further ashing, CF ₄ Etching was performed using a mixed gas of Ar and Ar. Under these conditions, the etching selectivity of the porous organosiloxane insulating film to aluminum oxide was 50. The etching selectivity of the resist, the antireflection film, and the silicon oxide film to the porous organic siloxane-based insulating film was 0.5. Using these conditions, the removal of the resist 223 and the antireflection film 222 and the processing of the silicon oxide film 213 and the porous organic siloxane-based insulating film 212 can be simultaneously performed using the aluminum oxide 221 as a hard mask. 36, it was possible to go directly to the state of FIG. Since the porous organic siloxane-based insulating film was not exposed to ashing, no increase in dielectric constant or deterioration in breakdown voltage due to damage to the porous organic siloxane-based insulating film was observed.
[0037]
In this embodiment, the hydrogenated siloxane-based coating film (OCD-Type 12 manufactured by Tokyo Ohka) used as the sacrificial film 226 contains 25% of Si. Even if this sacrificial film 226 was changed to another hydrogenated siloxane-based coating film containing 20% of Si, a two-layer wiring could be prototyped without any problem. When the sacrificial film 226 is changed to an organic siloxane film obtained by a CVD method or a coating method containing 10%, 15%, or 20% of Si, when the sacrificial film 226 is a hydrogenated siloxane-based coating film, Although the dimensional change due to shrinkage was 5% more than that of, a two-layer wiring could be prototyped without any practical problem. On the other hand, if the sacrificial film 226 is changed to a film containing 1% or 5% of Si, the sacrificial film 226 is sacrificed when the silicon oxide 213, the organic siloxane-based insulating film 212, and the silicon carbonitride film 211 are processed (FIG. 36). The problem that the film remains remains. This is because when the amount of Si contained in the sacrificial film 226 decreases, the etching rate decreases.
[0038]
<Example 6>
A Cu multilayer wiring of a semiconductor device was formed by a dual damascene method.
First, in the same manner as in Example 5, an interlayer insulating film (211, 212, 213) and an aluminum oxide film 221 were formed on the lower wiring, and the upper wiring pattern 232 was transferred to the aluminum oxide thin film 221 (FIG. 32).
Next, after a siloxane hydride coating film (OCD-Type12 (registered trademark) manufactured by Tokyo Ohka) is applied as the sacrificial film 226, an antireflection film 222 and an ArF resist 223 are formed, and a connection hole pattern 231 is formed by ArF lithography. (FIG. 39). Next, the antireflection film 222 and the sacrificial film 226 were processed using the resist 223 as a mask (FIG. 40). At this time, if the aluminum oxide film 221 was exposed in the connection hole pattern 231 due to misalignment, the aluminum oxide film was also removed. Further, ashing was performed to remove the antireflection film 222 and the ArF resist 223 (FIG. 41). In order to prevent the sacrificial film 226 from shrinking during the assembling and the pattern size from fluctuating, low pressure oxygen plasma of 10 mTorr was used for ashing.
[0039]
Next, using the sacrificial film 226 and the aluminum oxide film 221 as a hard mask, the silicon oxide 213, the organic siloxane-based insulating film 212, and the silicon carbonitride film 211 were processed (FIG. 36). CHF for etching ₃ And N ₂ Was used. The selectivity between the organic siloxane insulating film 212 and the sacrificial film 226 was 1, and the selectivity between the organic siloxane insulating film 212 and the aluminum oxide 221 was 20. Further commercially available NH ₄ Post-cleaning was performed using an F-containing acidic cleaning solution, and aluminum oxide 221 was dissolved and removed together with the etching residue (FIG. 37). The removal rate of aluminum oxide 221 with this cleaning solution was 8 nm / min. Next, a barrier metal 241 and a Cu 242 were formed in the pattern by a damascene method in which a directional sputtering method, a plating method, and a CMP method were combined, thereby forming an upper wiring and an interlayer connection (FIG. 38).
[0040]
In this example, since the organosiloxane insulating film was not exposed to ashing, no increase in dielectric constant or deterioration in breakdown voltage was observed even when the electrical characteristics between adjacent wirings were evaluated.
In this example, a two-layer wiring was prototyped again on the substrate, replacing the silicon carbonitride 211 of the barrier insulating film with silicon nitride, silicon oxynitride, and silicon carbide.
Further, in this example, the organic siloxane-based insulating film 212 was changed to a porous organic siloxane-based insulating film having a relative dielectric constant of 2.5, and a two-layer wiring was similarly produced on a trial basis. At this time, a 0.005% diluted hydrofluoric acid solution was applied. Since the porous organic siloxane-based insulating film was not exposed to ashing, no increase in dielectric constant or deterioration in breakdown voltage due to damage to the porous organic siloxane-based insulating film was observed.
[0041]
【The invention's effect】
According to the present invention, there is provided a highly accurate hole groove forming process for an organic siloxane-based insulating film, which does not cause damage to the organic siloxane-based insulating film by asher, and does not cause a problem of shape deterioration or foreign matter. A Cu multilayer wiring can be formed by a single damascene method or a dual damascene method.
[Brief description of the drawings]
FIG. 1 is a process explanatory view of Example 1 of the present invention.
FIG. 2 is a process explanatory view of the first embodiment of the present invention.
FIG. 3 is a process explanatory view of the first embodiment of the present invention.
FIG. 4 is a process explanatory view of the first embodiment of the present invention.
FIG. 5 is a process explanatory view of the first embodiment of the present invention.
FIG. 6 is a process explanatory view of the first embodiment of the present invention.
FIG. 7 is a process explanatory view of the first embodiment of the present invention.
FIG. 8 is a process explanatory view of the first embodiment of the present invention.
FIG. 9 is a process explanatory view of the first embodiment of the present invention.
FIG. 10 is a process explanatory view of the first embodiment of the present invention.
FIG. 11 is a process explanatory view of the first embodiment of the present invention.
FIG. 12 is a process explanatory view of the first embodiment of the present invention.
FIG. 13 is a process explanatory view of the first embodiment of the present invention.
FIG. 14 is an explanatory view of a step in Example 1 of the present invention.
FIG. 15 is an explanatory diagram of a step in Example 1 of the present invention.
FIG. 16 is a process explanatory view of the first embodiment of the present invention.
FIG. 17 is a process explanatory view of the first embodiment of the present invention.
FIG. 18 is a process explanatory view of the first embodiment of the present invention.
FIG. 19 shows the dissolution rate of aluminum oxide in a diluted hydrofluoric acid solution.
FIG. 20 is an explanatory view of a step in Example 4 of the present invention.
FIG. 21 is an explanatory view of a step in Example 4 of the present invention.
FIG. 22 is an explanatory view of a step in Example 4 of the present invention.
FIG. 23 is an explanatory view of a step in Example 4 of the present invention.
FIG. 24 is an explanatory view showing a step in the fourth embodiment of the present invention.
FIG. 25 is an explanatory diagram of a step in Example 4 of the present invention.
FIG. 26 is a process explanatory view of the fourth embodiment of the present invention.
FIG. 27 is a process explanatory view of the fourth embodiment of the present invention.
FIG. 28 is an explanatory view of a step in Example 4 of the present invention.
FIG. 29 is a process explanatory view of the fourth embodiment of the present invention.
FIG. 30 is a process explanatory view of the fifth embodiment of the present invention.
FIG. 31 is a process explanatory view of the fifth embodiment of the present invention.
FIG. 32 is a process explanatory view of the fifth embodiment of the present invention.
FIG. 33 is an explanatory diagram of a step in Example 5 of the present invention.
FIG. 34 is an explanatory diagram of a step in Example 5 of the present invention.
FIG. 35 is an explanatory view of a step in Example 5 of the present invention.
FIG. 36 is a process explanatory view of the fifth embodiment of the present invention.
FIG. 37 is a process explanatory view of the fifth embodiment of the present invention.
FIG. 38 is an explanatory diagram of a process according to the fifth embodiment of the present invention.
FIG. 39 is a process explanatory view of the sixth embodiment of the present invention.
FIG. 40 is an explanatory diagram showing a step in the sixth embodiment of the present invention.
FIG. 41 is an explanatory view of a step in Example 6 of the present invention.
[Explanation of symbols]
0 ... semiconductor substrate, 1 ... interlayer insulating film on gate, 2 ... contact electrode,
112, 212 ... organosiloxane insulating film,
113, 213 ... silicon oxide film,
211 ... silicon carbonitride film,
121, 221 ... aluminum oxide film,
122, 222, 224 ... antireflection film,
123, 223, 225 ... resist,
231, a connection hole pattern,
132, 232 ... wiring pattern,
141, 241 ... barrier metal,
142, 242 ... copper,
226 ... Sacrificial film.

Claims (25)

Forming a first insulating film;
Forming a second insulating film on the first insulating film;
Forming an inorganic thin film soluble in a solution on the second insulating film;
Forming a resist pattern on the inorganic thin film,
Transferring the resist pattern to the inorganic thin film by dry etching,
Removing the resist pattern;
Transferring the pattern of the inorganic thin film to the first insulating film and the second insulating film by dry etching;
Removing the inorganic thin film by dissolving it in a solution. Forming a first insulating film;
Forming a second insulating film on the first insulating film;
Forming an inorganic thin film on the second insulating film, forming a first resist pattern on the inorganic thin film,
Transferring the first resist pattern to the inorganic thin film by dry etching;
Removing the first resist pattern;
Forming a second resist pattern on the inorganic thin film;
Transferring the second resist pattern to at least the second insulating film by dry etching;
Removing the inorganic thin film by dissolving it in a solution. 3. The method according to claim 2, wherein the first resist pattern is a wiring pattern, and the second resist pattern is a connection hole pattern. 3. The method according to claim 2, wherein the first resist pattern is a connection hole pattern, and the second resist pattern is a wiring pattern. The method according to claim 1, wherein the inorganic thin film is a metal oxide or a metal oxynitride. 6. The method according to claim 1, wherein the inorganic thin film is made of aluminum oxide or aluminum oxynitride. The method according to claim 1, wherein the inorganic thin film is formed by a sputtering method or a reactive sputtering method. The method for manufacturing a semiconductor device according to claim 1, wherein the solution contains at least fluorine. 9. The method according to claim 1, wherein the concentration of fluorine in the solution is not less than 0.0005% and not more than 0.5%. The method according to claim 1, wherein the second insulating film is any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbonitride. . The method according to claim 1, wherein the second insulating film is a stacked film in which silicon oxide is formed on silicon carbide. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is an organic siloxane-based insulating film. 13. The method according to claim 1, wherein the first insulating film is a laminated film in which an organic siloxane-based insulating film is formed on one of silicon nitride, silicon oxynitride, silicon carbide, and silicon carbonitride. A method for manufacturing a semiconductor device according to any one of the above. 14. The method of manufacturing a semiconductor device according to claim 1, wherein the step of transferring the resist pattern onto the soluble thin film uses dry etching with a gas containing at least chlorine. The resist pattern dry etching gas in the step of transferring the method of producing a semiconductor device according to any one of claims 1 to 14, characterized in that it comprises at least Cl ₂ or BCl ₃ in the soluble film. 16. The method according to claim 1, wherein ArF lithography is used in the step of forming the resist pattern. 17. The method according to claim 1, wherein a metal film containing at least Cu is formed after removing the inorganic thin film. Forming a first insulating film made of any of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbonitride on the organic siloxane-based insulating film;
Forming an inorganic thin film made of aluminum oxide or aluminum oxynitride on the first insulating film;
A method of manufacturing a semiconductor device, comprising a step of removing a part of the inorganic thin film and exposing the first insulating film without exposing the organic siloxane-based insulating film. Forming a first insulating film made of a stacked film of silicon oxide and silicon carbide on the organic siloxane-based insulating film;
Forming an inorganic thin film made of aluminum oxide or aluminum oxynitride on the first insulating film;
A method of manufacturing a semiconductor device, comprising a step of removing a part of the inorganic thin film and exposing the first insulating film without exposing the organic siloxane-based insulating film. A method for manufacturing a semiconductor device, comprising selectively removing aluminum oxide or aluminum oxynitride from at least a structure where Cu is exposed using a liquid having a fluorine concentration of 0.0005% or more and 0.5% or less. . 21. The method according to claim 20, wherein a metal film containing at least Cu is formed after removing aluminum oxide or aluminum oxynitride. Forming a first insulating film made of any of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride on the organic siloxane insulating film;
Forming an inorganic thin film made of aluminum oxide or aluminum oxynitride on the first insulating film;
Exposing the first insulating film by removing a part of the inorganic thin film without exposing the organic siloxane-based insulating film;
Forming a sacrificial film containing at least 10% or more of Si so as to cover the exposed first insulating film and the inorganic thin film;
Removing the portion of the sacrificial film without exposing the organic siloxane-based insulating film to expose the first insulating film. Forming a first insulating film made of a stacked film of silicon oxide and silicon carbide on the organic siloxane-based insulating film;
Forming an inorganic thin film made of aluminum oxide or aluminum oxynitride on the first insulating film;
Exposing the first insulating film by removing a part of the inorganic thin film without exposing the organic siloxane-based insulating film;
Forming a sacrificial film containing at least 10% or more of Si so as to cover the exposed first insulating film and the inorganic thin film;
Removing the portion of the sacrificial film without exposing the organic siloxane-based insulating film to expose the first insulating film. 24. The method according to claim 22, wherein the sacrificial film is a hydrogen siloxane-based insulating film. 24. The method according to claim 22, wherein the sacrificial film is a hydrogen siloxane-based insulating film containing 10% or more of Si.

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