JP3466796B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOS transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art As semiconductor LSIs become faster and more highly integrated, semiconductor elements and wirings are becoming finer. In such an LSI, it is difficult to pattern the upper layer wiring due to a step due to a semiconductor element such as a MOS transistor. Therefore, it is necessary to flatten the step for stable wiring formation. Techniques such as resist etch back and CMP (Chemical Mechanical Polishing) have been proposed and practiced as the method.

FIG. 3 is a cross-sectional view of a part of a semiconductor device in which a step is flattened. In FIG. 3, 411 is a P-type semiconductor substrate (silicon substrate). Reference numeral 412 is an element isolation region (SiO ₂ ) and 413 is an N-type diffusion layer region. 414
Is a polycrystalline silicon film, 415 is a tungsten silicide film, 416 is an oxide film, and the multilayer structure of these forms the gate electrode wiring 420. 417 is an oxide film as an interlayer insulating film, 418 is a metal wiring connected to the N-type diffusion layer region 413, and 418 'is a tungsten silicide film 4.
It is a metal wiring connected to 15.

However, due to this flattening, FIG.
As shown in, the depth Y of the contact hole 419 to be formed on the N-type diffusion layer region 413 and the contact hole 41 to be formed on the gate electrode wiring 420 on the element isolation region 412.
This causes the result that the depth X of 9'is significantly different. Therefore, the contact holes 419, 4 with different depths are formed.
The problem is how to form 19 '.

As a first method for solving this problem, as shown in FIG. 5, a gate electrode wiring 420 is provided.
This is a method in which two masks are combined, the upper mask for contact formation and the mask for contact formation on the diffusion layer. Hereinafter, a method for manufacturing the semiconductor device will be described with reference to the drawings. First, as shown in FIG. 5A, a gate electrode wiring 624 having a multilayer structure of an element isolation region 612, an N-type diffusion layer region 613, a polycrystalline silicon film 614, a tungsten silicide film 615, and an insulating film 616.
After depositing the oxide film 617 on the P-type semiconductor substrate (silicon substrate) 611 on which the and are formed, the upper surface of the oxide film 617 is
Planarization is performed by using an etch back method or a CMP method.

Next, as shown in FIG. 5B, using the photoresist 618 as a mask, an arbitrary diffusion layer region 613 is formed.
An opening is provided only above, and the oxide film 6 is formed by a thickness of about the level difference between the surface of the diffusion layer region 613 and the upper surface of the gate electrode wiring 624.
17 is etched to form a contact hole 619.
Next, as shown in FIG. 5C, the photoresist 620
With the mask as a mask, an opening is provided on an arbitrary diffusion layer region 613 (formation portion of the contact hole 619) and on the gate electrode wiring 624, and the diffusion region 613 and the gate electrode wiring 624 are formed.
The tungsten silicide film 615 and the oxide film 617 are etched to contact holes 621, 621 '.
To form.

Next, as shown in FIG. 5D, the contact holes 621 and 621 'are filled with metal films 623 and 623', and upper layer metal wirings 622 and 622 'are formed to complete the process. The contact holes 621 and 621 'having different depths can be easily formed by using the above method.

As a second method, when the oxide film 617 is etched, the selection ratio between the oxide film 617 and the gate electrode wiring 624 is increased to increase the gate electrode wiring 6
By preventing 24 from being etched so much, two types of contact holes 621, 62 having different depths are formed.
This is a method of forming 1'at the same time. Therefore, a high-density plasma etching technique with a high selection ratio has been developed.

[0009]

However, in the first method described above, the number of masks increases by one and the alignment accuracy between the two masks becomes a problem, which leads to miniaturization and high integration of semiconductor devices. Not suitable. Further, in the second method, although the selection ratio is large, since a considerable amount of overetching is applied to the gate electrode wiring, damage to the gate oxide film due to the antenna effect or the like becomes a problem. In particular, with the miniaturization of elements, the gate oxide film has become thinner and is now 7 nm or less, so that there is a problem that the gate oxide film is completely destroyed.

Here, the antenna effect will be described.
The antenna effect is a phenomenon in which, when a long wiring is connected to the gate electrode of a MOS transistor, electric charges generated in the wiring due to etching plasma damage at the time of forming the wiring (during contact formation) change the potential of the gate electrode. Is. The potential difference generated at this time damages or destroys the gate oxide film.
The degree of damage to the gate oxide film depends on the amount of electric charges generated in the wiring, and therefore increases as the etching time increases.

Therefore, the present invention has been made paying attention to the fact that damage to the gate oxide film can be suppressed by absorbing the contact overetch in the insulating film on the gate electrode wiring. An object of the present invention is to provide a semiconductor device which requires only one mask for forming contact holes having different depths, has no problem of mask alignment accuracy, and can be miniaturized and highly integrated, and a manufacturing method thereof. It is to be.

Another object of the present invention is to provide a semiconductor device which has contact holes having different depths and whose gate oxide film is not damaged. Still another object of the present invention is to provide a method of manufacturing a semiconductor device, which can form contact holes having different depths without damaging the gate oxide film.

[0013]

According to the present invention, a polycrystalline silicon film having a high selection ratio to an insulating film is formed in an interlayer insulating film on a diffusion layer region where it is desired to open contact holes having different depths and on a gate electrode wiring. By interposing a conductive film such as the above, the conductive film acts as an etching stopper at the time of etching the upper insulating film, and absorbs the difference in thickness of the upper insulating film. is there.

[0014]

[0015]

A method of manufacturing a semiconductor device according to claim 1 is
After forming a diffusion layer region and a gate electrode wiring and sequentially depositing a first oxide film, a conductor film and a second oxide film on a semiconductor substrate having a step on the surface, the surface of the second oxide film is flattened. Turn into. Then, the second oxide film is etched on the diffusion layer region and on the gate electrode wiring to reach the conductor film by using the photoresist as a mask to open the first and second contact holes. Then, the conductor films on the bottom surfaces of the first and second contact holes are etched respectively, and the first and second contact holes are formed until the bottom surfaces of the first and second contact holes reach the first oxide film, respectively. deepen. Then, the first oxide films on the bottom surfaces of the first and second contact holes are etched using the photoresist as a mask, until the bottom surfaces of the first and second contact holes reach the diffusion layer region and the gate electrode wiring, respectively. Deepen the first and second contact holes. Then, after removing the photoresist, the exposed portions of the conductor film on the inner peripheral surfaces of the first and second contact holes are oxidized to form third and fourth oxide films, respectively. Next, the first and second contact holes are filled with the first and second conductors, respectively, and upper layer wirings connected to the first and second conductors are formed on the second oxide film.

According to this structure, etching is performed for forming the first and second contact holes in the second oxide film by using the conductor film as an etching stopper, which is thick on the diffusion layer region and the gate. Second thin on electrode wiring
The difference in the film thickness of the oxide film can be absorbed. Then, after etching the conductor film, the first oxide film having a substantially uniform thickness is etched so that the first and second oxides having different depths are formed.
Contact hole is formed, overetching to the gate electrode wiring is minimized, and damage to the gate oxide film can be minimized. Further, only one mask is required for forming the first and second contact holes, and only one mask is required for forming contact holes having different depths, and there is no problem in mask alignment accuracy, and there is no need for a fine mask. And high integration are possible.

A method of manufacturing a semiconductor device according to claim 2 is
A first oxide film, a conductor film, and a second oxide film are formed on a semiconductor substrate having a step on the surface by forming a diffusion layer region and a gate electrode wiring.
After sequentially depositing the oxide film of, the surface of the second oxide film is flattened. Then, the second oxide film is etched on the diffusion layer region and the gate electrode wiring to reach the conductor film by using the photoresist as a mask, and the first and second oxide films are etched.
Open the contact hole. Then, after removing the photoresist, portions of the conductor film exposed on the bottom surfaces of the first and second contact holes and their peripheral portions are oxidized to form third and fourth oxide films. Then, using anisotropic etching, the upper surface of the second oxide film,
The third and fourth oxide films and the first oxide film are etched to form the first and second contact holes until the bottom surfaces of the first and second contact holes reach the diffusion layer region and the gate electrode wiring, respectively. deepen. Next, the first and second contact holes are filled with the first and second conductors, respectively, and upper layer wirings connected to the first and second conductors are formed on the second oxide film.

According to this structure, etching is performed for forming the first and second contact holes in the second oxide film using the conductor film as an etching stopper. Second thin on electrode wiring
The difference in the film thickness of the oxide film can be absorbed. Then, after etching the conductor film, the first oxide film having a substantially uniform thickness is etched so that the first and second oxides having different depths are formed.
Contact hole is formed, overetching to the gate electrode wiring is minimized, and damage to the gate oxide film can be minimized. Further, only one mask is required for forming the first and second contact holes, and only one mask is required for forming contact holes having different depths, and there is no problem in mask alignment accuracy, and there is no need for a fine mask. And high integration are possible.

A method of manufacturing a semiconductor device according to claim 3 is
In the method of manufacturing a semiconductor device according to claim 1 or 2 , the conductor film is a polycrystalline silicon film.

[0021]

DETAILED DESCRIPTION OF THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings. 1A to 1D are sectional views in order of the steps, showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

First, as shown in FIG. 1A, an element isolation region (SiO ₂ ) 112, an N type diffusion layer region 113, a polycrystalline silicon film 114, a tungsten silicide film 115 and an oxide film (SiO ₂ film) 116 are formed. A first oxide film (SiO 2) for interlayer insulation is formed on a P-type semiconductor substrate (silicon substrate) 111 on which a gate electrode wiring 126 having a multilayer structure is formed.
₍₂ film) 117 is deposited, and then a polycrystalline silicon film 118 which is a conductor film is deposited. Next, after depositing a _second oxide film (SiO ₂ film) 119 for interlayer insulation, the upper surface thereof is flattened by an etch back method or a CMP (chemical mechanical polishing) method. The first oxide film 117, the polycrystalline silicon film 118, and the second oxide film 119 are continuously deposited.

Next, as shown in FIG. 1B, a second layer is formed on an arbitrary diffusion layer region 113 and gate electrode wiring 126.
The oxide film 119 is etched using the photoresist 120 as a mask to reach the polycrystalline silicon film 118 to open the first and second contact holes 121 and 121 '. Next, as shown in FIG. 1C, the polycrystalline silicon films 118 on the bottom surfaces of the first and second contact holes 121 and 121 'shown in FIG. The first and second contact holes 121, 121 'are deepened until the bottoms of the contact holes 121, 121' reach the first oxide film 117, respectively.

Next, as shown in FIG.
(C) First and second contact holes 121, 12
The first oxide film 117 on the bottom surface of 1'is formed on the photoresist 1
20 is used as a mask to etch the N-type diffusion layer region 113 and the tungsten silicide film 115 of the gate electrode wiring 126 down to the bottoms of the first and second contact holes 121 and 121 ', respectively. The first and second contact holes 12 up to the tungsten silicide film 115 of the wiring 126.
Deepen 1,121 '. Next, the photoresist 120
Then, the portions of the polycrystalline silicon film 118 exposed on the inner peripheral surfaces of the first and second contact holes 121, 121 'are thermally oxidized to form the third and fourth oxide films 124, 124'. Form.

Next, as shown in FIG. 1E, the first and second contact holes 121 and 121 'are filled with the first and second metal films 123 and 123' which are conductors, and the upper layer metal is formed. Wirings 125 and 125 'are formed and completed. The effect of the method of manufacturing the semiconductor device configured as described above will be described below with reference to FIGS. 1, 3, and 4.

First, in FIG. 1B, dry etching of CHF ₃ and CF ₄ gases is used as an etching method to secure an etching selection ratio of 30 or more between the second oxide film 119 and the polycrystalline silicon film 118. be able to. Therefore, the second oxide film 11 in the formation region of the first and second contact holes 121, 121 'in the figure
The steps of 9 can be absorbed by the polycrystalline silicon film 118 serving as an etching stopper.

Further, in FIG. 1C, by using dry etching of HBr and Cl ₂ gas,
It is possible to secure an etching selection ratio of 50 or more between the polycrystalline silicon film 118 and the first oxide film 117. Therefore, in addition to the contact hole etching step shown in FIG. 1B, the first and second contact holes 121, 1 shown in FIG.
Both bottom surfaces of 21 'can be aligned with the bottom surface of the polycrystalline silicon film 118, that is, the surface of the first insulating film 117. The polycrystalline silicon film 118 is the first oxide film 11
Immediately after the deposition of No. 7, the deposition is performed without performing the planarization process. Therefore, on the N-type diffusion layer region 113 and the gate electrode wiring 12
6 and the oxide film 117 under the polycrystalline silicon film 118 has almost the same film thickness. Therefore, in the step shown in FIG. 1D, the first and second contact holes 121 reaching the N-type diffusion layer region 113 and the gate electrode wiring 126,
The formation of 121 'can be performed in approximately the same processing time.

FIG. 3 shows an optional semiconductor integrated circuit device of the prior art.
4 is a cross-sectional view at the location of FIG.
And a method according to an embodiment of the present invention.
Then, the oxide film of the MOS capacitor in the semiconductor integrated circuit device
Indicates withstand voltage (applied voltage vs. gate-substrate leakage current characteristics)
The solid line X₁In the case of the embodiment of FIG.
₂Is the case of the conventional example.

As shown in FIG. 3, when the interlayer insulating film 417 is completely flattened, the oxide film thickness X on the gate electrode wiring 420 and the oxide film thickness Y on the N-type diffusion layer region 413 are greatly different. Therefore, the contact hole 419 'on the gate electrode wiring 420 having a small film thickness is first opened, and the diffusion layer region 4 is formed.
The process until the contact hole 419 to the hole 13 is opened acts as over-etching on the gate electrode wiring 420. Therefore, damage is applied to the gate electrode wiring 420. Therefore, MOS
The gate oxide film of the capacitor was damaged, and the solid line X in FIG.
It will be destroyed as shown in ₂ . However, in the embodiment of the present invention, this overetching can be absorbed by polycrystalline silicon film 118, and therefore gate electrode wiring 126
Does not damage. Therefore, as indicated by the solid line X ₁ in FIG. 4, the gate oxide film exhibits excellent withstand voltage characteristics.

As described above, according to this embodiment,
The polycrystalline silicon film 1 is formed in the interlayer insulating film (117, 119).
By embedding 18, that is, the first oxide film 11
7 has a three-layer structure in which a conductor film 118 is stacked on top of the second oxide film 119, and a second oxide film 119 is stacked on top of the conductor film 118, and only the uppermost second oxide film 119 is flattened. The film thickness difference caused by the complete flattening of the interlayer insulating film is
This can be absorbed when the first and second contact holes 121 and 121 'are opened, overetching to the gate electrode wiring 126 can be reduced, and damage to the gate oxide film can be suppressed. That is, the first and second oxide films 119 are formed on the second oxide film 119 using the conductor film 118 as an etching stopper.
Etching is performed to form the contact holes 121 and 121 ′ of the second oxide film 119, which is thick on the diffusion layer region 113 and thin on the gate electrode wiring 126.
The difference in the film thickness can be absorbed. After etching the conductor film 118, the first oxide film 117 having a substantially uniform thickness is formed.
By etching, the first and second contact holes 121 and 121 'having different depths are formed, and the overetching to the gate electrode wiring 126 is suppressed to the minimum, so that the damage to the gate oxide film is prevented. Can be kept to a minimum. Further, the mask for forming the first and second contact holes 121, 121 'is 1
Only one mask is required for forming the contact holes having different depths, there is no problem of mask alignment accuracy, and miniaturization and high integration are possible.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings. 2A to 2D are sectional views in order of the steps, showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention. First, as shown in FIG. 2A, an element isolation region (SiO ₂ )
212, N-type diffusion layer region 213, and polycrystalline silicon film 21.
4, tungsten silicide film 215 and oxide film (S
gate electrode wiring 2 having a multilayer structure of iO ₂ film) 216
P-type semiconductor substrate (silicon substrate) 211 on which 26 is formed
After depositing a first oxide film (SiO ₂ film) 217 for interlayer insulation on it, a polycrystalline silicon film 218 which is a conductor film is deposited. Next, a second oxide film (SiO 2) for interlayer insulation is formed.
₍₂ film) 219 is deposited, and then the upper surface thereof is flattened by an etch back method or a CMP method.

Next, as shown in FIG. 2B, a second layer is formed on an arbitrary diffusion layer region 213 and a gate electrode wiring 226.
The oxide film 219 is etched to reach the polycrystalline silicon film 218 using the photoresist 220 as a mask to open the first and second contact holes 221 and 221 '. Next, as shown in FIG. 2C, after removing the photoresist 220, the first and second contact holes 22 shown in FIG. 2B are formed in the polycrystalline silicon film 218.
The exposed portions of the bottom surfaces of the first and second 221 'and their peripheral portions are thermally oxidized to form third and fourth oxide films (SiO.sub.2).
₂ films) 222, 222 'are formed.

Next, as shown in FIG. 2D, the upper surface of the second oxide film 219, the third and fourth oxide films 222, 222 'and the first oxide film are anisotropically etched. The first and second contact holes 22 are etched until the bottom surfaces of the first and second contact holes 221 and 221 'reach the N-type diffusion layer region 213 and the tungsten silicide film 215 of the gate electrode wiring 226 by etching 217.
Deepen 1,221 '.

Next, as shown in FIG. 2 (e), the first and second contact holes 221 and 221 'are filled with the first and second metal films 225 and 225', which are conductors, and the upper layer metal is formed. Wirings 224 and 224 'are formed and completed. The effects of the method of manufacturing a semiconductor device configured as described above will be described. First, in FIG. 2B, dry etching with a gas of CHF ₃ and CF ₄ is used as an etching method to secure an etching selection ratio of 30 or more between the second oxide film 219 and the polycrystalline silicon film 218. The second contact holes 221 and 221 'are opened. At this time, the second oxide film 219 in the formation regions of the first and second contact holes 2221 and 221 'in the figure is formed.
Can be absorbed by the polycrystalline silicon film 218 serving as an etching stopper.

Further, in FIG. 2C, the polycrystalline silicon film 218 exposed on the bottom surfaces of the first and second contact holes 221 and 221 'is oxidized to form the structure shown in FIG.
As shown in (d), the contact holes 221 and 221 ′ reaching the N-type diffusion layer region 113 and the gate electrode wiring 126.
Can be formed by one etching. Also in this step, since the oxide film thicknesses on the gate electrode wiring 226 and the N-type diffusion layer region 213 are almost the same, the amount of overetching to the gate electrode wiring 226 is suppressed and the gate oxide film is damaged. There is no.

The effects of this embodiment are as follows:
Of the polycrystalline silicon film 218 exposed on the bottom surfaces of the contact holes 221 and 221 ′ of the above are converted into third and fourth oxide films, thereby forming holes in the second oxide film and removing the polycrystalline silicon film 218. In the second embodiment, the contact hole 22 is required to be etched three times for the opening and the first oxide film.
This embodiment is the same as the above-described first embodiment except that the number of times of etching for forming the first and second parts 221 'is only two and the process is simplified. Also in this case, the oxide film breakdown voltage as shown by the solid line X ₁ in FIG. 4 has good characteristics.

As described above, according to this embodiment,
The polycrystalline silicon film 2 is formed in the interlayer insulating film (217, 219).
By embedding 18, that is, the first oxide film 21
7 has a three-layer structure in which a conductor film 218 is stacked on top of the second oxide film 219, and a second oxide film 219 is stacked on top of the conductor film 218 to flatten only the uppermost second oxide film 219. The film thickness difference caused by the complete flattening of the interlayer insulating film is
It can be absorbed when the first and second contact holes 221 and 221 'are opened, overetching to the gate electrode wiring 226 can be reduced, and damage to the gate oxide film can be suppressed. That is, the first and second oxide films 219 are formed on the second oxide film 219 using the conductor film 218 as an etching stopper.
Etching is performed to form the contact holes 221 and 221 ′ of the second oxide film 219, which is thick on the diffusion layer region 213 and thin on the gate electrode wiring 226.
The difference in the film thickness can be absorbed. After etching the conductor film 218, the first oxide film 217 having a substantially uniform thickness is formed.
By etching, the first and second contact holes 221 and 221 'having different depths are formed, and the over-etching to the gate electrode wiring 226 is minimized, so that the damage to the gate oxide film is prevented. Can be kept to a minimum. Further, the mask for forming the first and second contact holes 221 and 221 'is 1
Only one mask is required for forming the contact holes having different depths, there is no problem of mask alignment accuracy, and miniaturization and high integration are possible. Moreover, the number of etching steps performed three times in the first embodiment can be reduced to two.

[0038]

According to the present invention, the interlayer insulating film has the sandwich structure of the first oxide film, the conductor film made of, for example, a polycrystalline silicon film, and the second oxide film, and thus the interlayer insulating film having different depths is formed. The first and second contact holes can be formed simultaneously without damaging the gate oxide film. Further, since the first and second contact holes can be formed with one mask, the semiconductor integrated circuit device can be highly integrated and highly integrated.

[Brief description of drawings]

FIG. 1 is a step-by-step cross-sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a step-by-step cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of the semiconductor integrated device at an arbitrary position.

FIG. 4 is a characteristic diagram showing a gate oxide film breakdown voltage characteristic showing effects by the manufacturing method of the semiconductor device according to the embodiment of the present invention and the conventional example.

5A to 5D are cross-sectional views in order of the processes, showing a conventional example of a method for manufacturing a semiconductor device.

[Explanation of symbols]

111 P type semiconductor substrate 112 element isolation region 113 N-type diffusion layer region 114 Polycrystalline silicon film 115 Tungsten silicide film 116 oxide film 117 First oxide film 118 Polycrystalline silicon film (conductor film) 119 Second oxide film 120 photoresist 121 First contact hole 121 'Second contact hole 123 First metal film 123 'Second metal film 124 Third oxide film 124 'Fourth oxide film 125 upper layer metal wiring 125 'upper layer metal wiring 126 Gate electrode wiring 211 P type semiconductor substrate 212 element isolation region 213 N-type diffusion layer region 214 Polycrystalline silicon film 215 Tungsten silicide film 216 oxide film 217 First oxide film 218 Polycrystalline silicon film (conductor film) 219 Second oxide film 220 photoresist 221 First contact hole 221 'Second contact hole 222 First oxide film 222 'Second oxide film 224 Upper layer metal wiring 224 'upper layer metal wiring 225 First metal film 225 'second metal film 411 P-type semiconductor substrate 412 element isolation region 413 N-type diffusion layer region 414 Polycrystalline silicon film 415 Tungsten silicide film 416 oxide film 417 oxide film 418 metal wiring 611 P-type semiconductor substrate 612 element isolation region 613 N-type diffusion layer region 614 Polycrystalline silicon film 615 Tungsten silicide film 616 oxide film 617 oxide film 618 photoresist 619 contact hole 620 photoresist 621 contact hole 621 'contact hole 622 upper layer metal wiring 622 'upper layer metal wiring 623 metal film 623 'metal film 624 gate electrode wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mizuki Segawa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-5-218340 (JP, A) JP-A-6- 314775 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768

Claims (3)

(57) [Claims] 1. A diffusion layer region and a gate electrode wiring are formed.
The first oxide film on the semiconductor substrate having a step on the surface,
After sequentially depositing a conductor film and a second oxide film,
Planarizing the surface of the second oxide film, the second oxide film on the diffusion layer region and the gate.
Using photoresist as a mask on each electrode wiring
First and second etching is performed to reach the conductor film.
And the step of opening the contact holes of the first and second contact holes.
The first contact and the second contact respectively etched.
Until the bottom surface of each hole reaches the first oxide film.
Deepening the first and second contact holes, and first oxidizing the bottom surfaces of the first and second contact holes
Etch each film using the photoresist as a mask
The bottom surfaces of the first and second contact holes.
Reach the diffusion layer region and the gate electrode wiring, respectively
To deepen the first and second contact holes
When, after removing the photoresist, the conductive film odor
Exposed on the inner peripheral surfaces of the first and second contact holes.
The third and fourth oxide films by oxidizing the
And forming the first and second contact holes in the first and second contact holes.
Each of the first and second conductors is filled with a conductor.
The upper layer wiring connected to the conductors of
A method of manufacturing a semiconductor device, the method comprising: 2. A diffusion layer region and a gate electrode wiring are formed.
The first oxide film on the semiconductor substrate having a step on the surface,
After sequentially depositing a conductor film and a second oxide film, the second oxide film is deposited.
A step of flattening the surface of an oxide film, and a step of forming the second oxide film on the diffusion layer region and the gate.
Using photoresist as a mask on each electrode wiring
First and second etching is performed to reach the conductor film.
The step of opening the contact hole in the above step, and after removing the photoresist,
Exposed on the bottom surface of the first and second contact holes.
To oxidize the part and its surrounding part respectively, and
A step of forming a fourth oxide film, and using anisotropic etching, an upper surface of the second oxide film,
The third and fourth oxide films and the first oxide film
Etching the first and second contact holes
Bottom surfaces of the diffusion layer region and the gate electrode, respectively.
Deepen the first and second contact holes to reach the wiring.
And a step of connecting the first and second contact holes to the first and second contact holes.
Each of the first and second conductors is filled with a conductor.
The upper layer wiring connected to the conductors of
A method of manufacturing a semiconductor device, the method comprising: 3. The conductor film is a polycrystalline silicon film.
A method of manufacturing a semiconductor device according to claim 1 or 2.