KR19990048154A - Semiconductor device having damascene bit line and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a semiconductor device having a damascene bit line and a method of manufacturing the same. An interlayer insulating film having a trench is formed on the semiconductor substrate. An insulating film is formed on the entire surface of the resultant to a desired thickness. Thereafter, a contact hole is formed in the trench, a conductive layer is filled in the contact hole, and the resultant is flattened to form a damascene bit line. The contact margin for forming the via hole exposing the conductive layer, that is, the bit line, is determined by the thickness of the insulating layer. As a result, the insulating layer increases the contact margin for misalignment in the process of forming the via hole. In addition, since the size of the trench is limited, the thickness of the insulating layer may be adjusted to form a bit line having a line width exceeding a limit of a photo process.

Description

A semiconductor device having a damascene bit line and a manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a damascene bit line and a method for manufacturing the same.

The damascene process is a method of forming a trench having a predetermined depth in the shape of a wiring to be formed in the insulating film, and then filling the trench with a conductive material layer to form a wiring having a desired shape. This damascene process is mainly applied to form bit lines.

However, as the semiconductor devices are highly integrated, it is necessary to pattern the bit lines more finely. However, it has become difficult to finely pattern the bit lines any more. Accordingly, the proposed method is a method using an anti-reflective layer. Specifically, an anti-reflection film is formed on the interlayer insulating film on which the bit line is formed by the damascene process. Subsequently, a damascene bit line is formed on the interlayer insulating film. However, this method has a problem that the process is complicated because the anti-reflection film must be removed after the damascene bit line is formed.

In addition, in the process of forming the via hole on the bit line after the damascene bit line is formed, the interlayer insulating layer surrounding the bit line is exposed and etched due to the lack of alignment margin.

This result can be easily seen with reference to FIG. 1. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device having a damascene bit line according to the related art, and a problem thereof.

Specifically, a gate electrode 17 made of a polysilicon layer 14 and a tungsten silicide layer (WSi) 16 on the semiconductor substrate 10 and a gate protection film 18 are formed on the gate electrode 17. . The spacer 20 is formed on side surfaces of the gate electrode 17 and the gate passivation layer 18. Subsequently, a first oxide film 22 is formed on the entire surface of the resultant, a trench is formed in the first oxide film 22, and a contact hole 24 is formed in the trench. A tungsten layer 26 is formed in the contact hole 24. The tungsten layer 26 is a damascene bit line. After forming the damascene bit line as described above, a second oxide layer 28 is formed on the entire surface of the resultant, and a via hole 30 exposing the tungsten layer 26 is formed on the second oxide layer 28.

However, in the semiconductor device manufacturing method according to the related art, when the semiconductor device is highly integrated, as shown in FIG. 1, there is no margin for alignment margin for the via hole contact. Accordingly, when the via hole contact is slightly beyond the bit line, the first interlayer dielectric layer is etched (32).

Accordingly, the technical problem to be achieved by the present invention is to solve the above-described problems of the prior art, and includes a damascene bit line which can simplify the process and increase the alignment margin of the via hole for contacting the bit line. The present invention provides a semiconductor device.

Another object of the present invention is to provide a method of manufacturing a semiconductor device including the damascene bit line.

1 is a cross-sectional view showing a damascene bit line forming method and a problem during a manufacturing process of a semiconductor device of a semiconductor device according to the prior art.

2 to 7 are cross-sectional views illustrating a step of forming a damascene bit line in a process of manufacturing a semiconductor device according to an embodiment of the present invention.

* Description of Signs of Major Parts of Drawings *

40: semiconductor substrate. 49: gate stack.

50: gate spacer. 52, 64: first and second interlayer insulating films.

54: Bitline trench. 56: insulating film.

58: contact hole. 60: conductive layer pattern.

64: Beer hall. d: insulation film thickness.

In order to achieve the above technical problem, the present invention provides a semiconductor substrate, a first interlayer insulating film formed on the semiconductor substrate, a trench formed in the first interlayer insulating film, a contact hole formed in the trench, a conductive layer filling the contact hole and the trench And a damascene bit line including a spacer between the conductive layer and the inner surface of the trench.

Here, the interlayer insulating film is an oxide film, and the conductive layer and the bit line spacer are a tungsten layer and a nitride film (SiN), respectively.

An interlayer insulating film including a via hole through which the conductive layer is exposed is further provided on the resultant product.

In order to achieve the above technical problem, the present invention provides a damascene bit line forming method of a semiconductor device manufacturing process comprising the following steps.

(a) A first interlayer insulating film is formed on a semiconductor substrate. (b) A trench is formed in the first interlayer insulating film. (c) An insulating film is formed over the entire surface of the first interlayer insulating film on which the trench is formed. (d) A bit line contact hole is formed in the trench. (e) Filling the trench with a conductive layer filling the contact hole.

A second interlayer insulating film is formed on the entire surface of the resultant, and a via hole exposing the conductive layer is formed on the second interlayer insulating film.

The conductive layer is formed of a tungsten layer. The insulating film is formed of a nitride film.

The contact hole is formed by etching the insulating film and the first interlayer insulating film using a first etchant.

An etchant having an etching selectivity equal to that of the insulating film and the first interlayer insulating film as the first agent, for example, an ethylene-added argon gas (Ar) and an oxygen gas (O 2) to a fluorocarbon gas having a low C / F ratio. use.

Here, the fluorocarbon gas having a low C / F ratio uses any one selected from the group consisting of CF4 and CHF3.

In addition, the via hole is formed by etching the second interlayer insulating film using a second etchant. In this case, the second etchant uses an etchant having a high etching selectivity relative to the nitride film, for example, an argon gas (Ar) and an oxygen gas (O2) added to a fluorocarbon gas having a high C / F ratio.

Here, the fluorocarbon gas having a high C / F ratio uses any one selected from the group consisting of C4F8, C3H8 and CH3F, CO.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a damascene bit line and a method of manufacturing the same, wherein an interlayer insulating film having a trench is formed on a semiconductor substrate, and then an insulating film for determining bit line contact margin is formed in the trench. Thereafter, a contact hole is formed in the trench, and a bit line is formed by filling a conductive layer in the contact hole. In this case, the insulating layer serves as a bit line spacer between the conductive layer and the trench. The contact margin of the via hole forming process for exposing the conductive layer, that is, the bit line, is determined by the thickness of the insulating layer. As described above, in the semiconductor device having the damascene bit line according to the present invention, it is possible to adjust the contact margin by adjusting the thickness of the insulating film between the bit line and the trench. Therefore, even if the mask alignment is misaligned to some extent in the process of forming the via hole, the interlayer insulating layer may be prevented from being etched. In addition, since the size of the trench is limited, a bit line having a line width smaller than the line width that can be formed by a photo process may be formed by adjusting the thickness of the insulating layer formed in the trench. In other words, it is possible to form a bit line having a line width beyond the limits of the photo process.

Hereinafter, a semiconductor device having a damascene bit line and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings, the thicknesses of layers or regions are prepared for clarity of specification. In the drawings like reference numerals refer to like elements. In addition, where a layer is described as being "top" of another layer or substrate, the layer may be directly on top of the other layer or substrate, with a third layer intervening therebetween.

2 to 7 are cross-sectional views sequentially illustrating a damascene bit line forming method during a manufacturing process of a semiconductor device according to an embodiment of the present invention.

First, a semiconductor device having a damascene bit line according to an embodiment of the present invention will be described with reference to FIG. 7.

Specifically, there is a gate stack 49 on the semiconductor substrate 40, and the gate spacer 50 surrounds the side surface thereof. The gate stack 49 includes a sequentially formed gate conductive layer 44, a gate silicide layer 46, and a passivation layer 48 for protecting an upper portion of the gate electrode. The gate conductive layer 44 and the gate silicide layer 46 are polysilicon layers and tungsten silicide layers, respectively. A gate oxide layer 42 exists between the gate stack 49 and the semiconductor substrate 40. Although not shown, impurity layers in which conductive impurities are injected are formed at the left and right sides of the semiconductor substrate 40 around the gate stack 49. One of the impurity layers is a source region and the other is a drain region. The first interlayer insulating film 52 is covered on the semiconductor substrate 40 on which the transistor is formed. The first interlayer insulating film 52 is an oxide film. A trench 54 is formed at a predetermined depth in an upper layer portion of the first interlayer insulating layer 52. A bit line contact hole 58 is formed at the bottom of the trench 54 to expose the semiconductor substrate 40 between the gate stacks. The trench 54 is filled with a conductive layer pattern 60 filling the bit line contact hole 58. The conductive layer pattern 60 is a bit line as a tungsten layer. The cross section of the conductive layer pattern 60 is an English tee (T) type as shown in the figure. However, an insulating layer pattern 56a that surrounds a portion of the conductive layer pattern 60 in the trench 54 exists between the trench inner surface and the conductive layer pattern 60. Therefore, the insulating layer pattern 56a serves as a spacer between the inner surface of the trench 54 and the conductive layer pattern 60. In view of the fact that the conductive layer pattern 60 is a bit line, the insulating layer pattern 56a may be regarded as a bit line spacer. The insulating layer pattern 56a may be regarded as at least a part of the conductive layer pattern 60 to isolate the first interlayer insulating layer 52 from the portion formed in the trench 54. Therefore, as the thickness d of the insulating layer pattern 56a becomes thicker, the distance between the conductive layer pattern 60 and the first interlayer insulating layer 52 is further spaced apart. This lowers the possibility that the first interlayer insulating film 52 may be exposed by misalignment that may occur in the via hole forming process of exposing the conductive layer pattern 60. In other words, the presence of the insulating layer pattern 56a increases the contact margin when the via hole 64 is formed. The insulating film pattern 56a is a nitride film pattern.

Subsequently, a second interlayer insulating film 62 is formed on the resultant product. The second interlayer insulating film 62 is an oxide film. The via hole 64 exposing the conductive layer pattern 56a is formed in the second interlayer insulating layer 62. FIG. 7 illustrates a state in which the via hole 64 is misaligned, but the misalignment of the via hole 64 is caused by the contact margin increased by the thickness d of the insulating layer pattern 56a. It can be seen that the first interlayer insulating film surrounding the pattern 60 is not exposed.

Next, a method of manufacturing a semiconductor device having a damascene bit line having the above-described configuration according to an embodiment of the present invention will be described.

2 is a diagram illustrating a step of forming a first interlayer insulating film 52. Specifically, the semiconductor substrate 40 is limited to an active region and a field region. A field oxide film is formed in the field region in a conventional manner. A gate insulating layer 42 is formed on the active region of the semiconductor substrate 40. The gate stack 49 is sequentially formed on the gate insulating layer 42, and the gate spacer 50 is formed on the side of the gate stack 49. The gate stack 49 sequentially forms the gate conductive layer 44, the gate silicide layer 46, and the gate protection layer 48 on the gate insulating layer 42, and then sequentially the semiconductor substrate 40. It is formed by anisotropic etching until it is exposed. The gate conductive layer 44 is formed of a polysilicon layer. In addition, the gate silicide layer 46 is formed of a tungsten silicide layer WSi. A first interlayer insulating film 52 is formed on the entire surface of the resultant product. The first interlayer insulating film 52 is formed of an oxide film.

3 is a diagram illustrating a step of forming a trench 54 in the first interlayer insulating layer 52 to a predetermined depth.

Specifically, a photoresist film, such as a photoresist film, is coated on the entire surface of the first interlayer insulating film 52. The photoresist film is patterned to form a photoresist film pattern (not shown) that exposes the trench formation region of the first interlayer insulating film 52. Using the photoresist layer pattern as an etch mask, a trench 54 is formed at a predetermined depth in the exposed portion of the first interlayer dielectric layer 52. The trench 54 is a region where a damascene bit line is to be formed. Thereafter, the photoresist film pattern is removed.

4 is a diagram illustrating a step of forming an insulating film 56 on the entire surface of the first interlayer insulating film 52 on which the trench 54 is formed.

Specifically, a nitride film SiN is formed as an insulating film 56 on the entire surface of the first interlayer insulating film 52. In this case, the insulating layer 56 is preferably formed to have the same thickness at the side and bottom of the trench 54. The insulating film 56 plays two roles as follows.

First, the insulating film 56 enables the formation of bit lines with fine line widths beyond the limits of the photolithography process. That is, by adjusting the thickness of the insulating film 56, the bit line forming region in the trench 54 is reduced. Such a small area is hardly limited to the above photographic process. Accordingly, it is possible to form a bit line having a line width smaller than that of the bit line that can be formed by the photolithography process.

Second, the contact margin is determined in the via hole forming process after the damascene bit line is formed by the insulating layer 56. That is, the contact margin is increased or decreased by increasing or decreasing the thickness of the insulating film 56.

The two roles of the insulating film 56 are not independent but are related to each other. That is, when the insulating layer 56 is formed thick, the line width of the bit line becomes finer, while the contact margin is further increased. In the opposite case, the line width of the bit line approaches the diameter of the trench 54 and the contact margin is very small.

5 is a diagram illustrating a step of forming the bit line contact hole 58.

Specifically, a photoresist film, such as a photoresist film, is coated on the entire surface of the insulating film 56 (FIG. 4). The photoresist film is patterned to form a photoresist pattern (not shown) that defines an area in the trench 54 to form a bit line contact hole. Mask alignment for forming the photoresist film pattern is easily performed due to the step difference in the trench 54 forming portion of the insulating film 56. Using the photoresist layer pattern as an etch mask, portions exposed in the trench 54 of the insulating layer 56 and the first interlayer dielectric layer 52 thereunder are sequentially anisotropically etched. The anisotropic etching is performed until the semiconductor substrate 40 is exposed. Thereafter, the photoresist film pattern is removed. As a result, a bit line contact hole 58 is formed in the trench 54 of the first interlayer insulating layer 52. In the anisotropic etching for forming the bit line contact hole 58, a first etchant having an etch selectivity equal to that of the insulating film 56 and the first interlayer insulating film 52 is used. For example, in order to etch the insulating film 56 and the first interlayer insulating film 52, a fluorine carbon gas having a low carbon (C) / fluorine (F) ratio and argon gas (Ar) are used as the first etchant. An etchant added with oxygen gas (O2) is used. The fluorocarbon gas having a low C / F ratio is any one selected from the group consisting of CF4 and CHF3.

Thereafter, although not shown in the drawings, a barrier layer is formed on the entire surface of the resultant product. The adhesion layer is formed of a multilayer, for example, a titanium layer (Ti) / titanium nitride layer (TiN).

6 shows the step of forming the conductive layer pattern 60, i.e., the damascene bit line.

Specifically, a conductive layer (not shown) is formed on the insulating layer 56 to fill the bit line contact hole 58. The conductive layer is formed of a tungsten layer. The entire surface of the resultant is planarized until the interface of the first interlayer insulating film 52 is exposed. The first interlayer insulating film 52 is planarized by chemical mechanical polishing. By the planarization process, the insulating layer 56 and the conductive layer are removed in a region other than the trench 54 region of the first interlayer insulating layer 52. As a result, the conductive layer pattern 60 filling the contact hole 58 is formed. The conductive layer pattern 60 is a damascene bit line. In addition, an insulating layer pattern 56a is formed between the inner surface of the trench 54 and the conductive layer pattern 60. The insulating layer pattern 56a serves as a bit line spacer. A portion of the conductive layer pattern 60 formed in the trench is surrounded by the insulating layer pattern 56a.

7 is a step of forming a via hole 64 exposing the conductive layer pattern 60.

Specifically, the second interlayer insulating film 62 is formed on the entire surface of the resultant product of FIG. 6. The second interlayer insulating film 62 is formed of an oxide film. A photoresist pattern (eg, a photoresist layer) is coated on the entire surface of the second interlayer insulating layer 62 and then patterned to expose a region corresponding to the conductive layer pattern 60 of the second interlayer insulating layer 62. Not shown). At this time, the alignment margin of the mask for patterning the photoresist film is determined by the thickness of the insulating film pattern 56a as described above.

In general, the alignment of the mask for patterning the photoresist film becomes more precise as the semiconductor device becomes more integrated. Therefore, the misalignment that may appear in the alignment process is small. Therefore, the alignment margin secured by the insulating film pattern 56a can sufficiently correspond to the misalignment.

Using the photoresist pattern as an etching mask, the exposed portion of the second interlayer insulating layer 62 is anisotropically etched until the interface of the conductive layer pattern 60 is exposed. In this case, the second etchant used for the anisotropic etching is an etchant having a high etching selectivity with respect to the nitride film. For example, the second agent uses an etchant in which argon gas (Ar) and oxygen gas (O2) are added to a fluorocarbon gas having a high C / F ratio. The fluorocarbon gas having a high C / F ratio is any one selected from the group consisting of C4F8, C3H8 and CH3F, CO. Subsequently, when the photoresist film pattern is removed, a via hole 64 exposing the conductive layer pattern 60 is formed in the second interlayer insulating film 62.

Most preferably, only the surface of the conductive layer pattern 60 is exposed by the via hole 64, but a part of the insulating layer pattern 56a may be exposed by misalignment. However, the allowable misalignment is preferably smaller than the alignment margin, that is, the contact margin determined by the thickness d of the insulating film pattern 56a.

The present invention relates to a semiconductor device having a damascene bit line and a method of manufacturing the same, wherein an interlayer insulating film having a trench is formed on a semiconductor substrate, and then an insulating layer for determining a bit line contact margin is formed in the trench. do. Thereafter, a contact hole is formed in the trench, and a bit line is formed by filling a conductive layer in the contact hole. In this case, the insulating layer serves as a bit line spacer between the conductive layer and the trench. The contact margin of the via hole forming process for exposing the conductive layer, that is, the bit line, is determined by the thickness of the insulating layer. As described above, in the semiconductor device having the damascene bit line according to the present invention, it is possible to adjust the contact margin by adjusting the thickness of the insulating film between the bit line and the trench. Therefore, even if the mask alignment is misaligned to some extent in the process of forming the via hole, the interlayer insulating layer may be prevented from being etched. In addition, since the size of the trench is limited, a bit line having a line width smaller than the line width that can be formed by a photo process may be formed by adjusting the thickness of the insulating layer formed in the trench. In other words, it is possible to form a bit line having a line width beyond the limits of the photo process.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical idea of the present invention.

Claims (18)

Semiconductor substrates; A first interlayer insulating film formed on the semiconductor substrate; A trench formed in the first interlayer insulating film; A contact hole formed in the trench; A conductive layer filling the contact hole and a trench; And And a spacer between the conductive layer and the inner surface of the trench. The semiconductor device of claim 1, further comprising a second interlayer insulating layer including a via hole through which the conductive layer is exposed. 3. The semiconductor device according to claim 2, wherein the first and second interlayer insulating films are oxide films. The semiconductor device according to claim 1, wherein the conductive layer is a tungsten layer. 2. The semiconductor device of claim 1, wherein the spacer is a nitride film (SiN). (a) forming a first interlayer insulating film on the semiconductor substrate; (b) forming a trench in the first interlayer insulating film; (c) forming an insulating film on the entire surface of the first interlayer insulating film on which the trench is formed; (d) forming bit line contact holes in the trench; And (e) filling the trench with a conductive layer filling the contact hole; and manufacturing a semiconductor device having a damascene bit line. The method of claim 6, further comprising: forming a second interlayer insulating film on the entire surface of the resultant material; And forming a via hole exposing the conductive layer in the second interlayer insulating film. 8. The method of claim 7, wherein the first and second interlayer dielectric films are formed of oxide films. 8. The method of claim 7, wherein the conductive layer is formed of a tungsten layer. 8. The method of claim 6, wherein the insulating film is formed of a nitride film. 7. The method of claim 6, wherein the contact hole is formed by etching the insulating film and the first interlayer insulating film using a first etchant. 12. The method of manufacturing a semiconductor device with a damascene bit line according to claim 11, wherein an etchant having an etch selectivity equal to that of the insulating film and the first interlayer insulating film is used as the first etchant. 13. The damascene bit line according to claim 12, wherein an etchant in which argon gas (Ar) and oxygen gas (O2) are added to the fluorocarbon gas having a low C / F ratio is used as the first agent. The manufacturing method of the semiconductor device provided. The method of manufacturing a semiconductor device with a damascene bit line according to claim 13, wherein the fluorocarbon gas having a low C / F ratio uses any one selected from CF4 and CHF3. The method of claim 7, wherein the via hole is formed by etching the second interlayer dielectric layer using a second etchant. The method of manufacturing a semiconductor device with a damascene bit line according to claim 15, wherein an etchant having a high etching selectivity with respect to the nitride film is used as the second etchant. 17. The damascene bit line according to claim 16, wherein an etchant comprising argon gas (Ar) and oxygen gas (O2) added to the fluorocarbon gas having a high C / F ratio is used as the second agent. The manufacturing method of the semiconductor device provided. 18. The method of manufacturing a semiconductor device with a damascene bit line according to claim 17, wherein the fluorocarbon gas having a high C / F ratio uses any one selected from C4F8, C3H8, CH3F, and CO.