JPH08335633A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE: To provide a semiconductor device wherein the degree of freedom of a layout pattern at contact hole formation is improved without degrading reliability. CONSTITUTION: Relating to a semiconductor device provided with a bit line 40 which is formed on a side wall through a contact hole 38 having a side wall 39 and the first and the second gate electrode layers 34 and 35 which must be insulated from the bit line 40, a concave end face part 41 is provided to the first gate electrode layer 34, and the concave end face part 41 is provided on the extended plane of the side wall of the contact hole 38.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of improving the degree of freedom of a layout pattern when forming a contact hole and a method of manufacturing the semiconductor device.

[0002]

2. Description of the Related Art FIG. 23 is a sectional view showing the structure of a conventional semiconductor device. 28 is a top view of the cell structure portion of the semiconductor device shown in FIG. In the figure, 1 is a semiconductor substrate, 2 is an element isolation region formed on the semiconductor substrate 1, 3 is an impurity layer formed on the semiconductor substrate 1, and 4 is an active region surrounded by the element isolation region 2. A gate electrode layer which is formed so as to cross over the element isolation region 2 and serves as a gate electrode on the active region, for example, a doped polysilicon film 5 and a tungsten silicon film 6 are sequentially laminated. Reference numeral 7 denotes a gate sidewall formed on the gate electrode layer 4, which is made of, for example, an oxide film.

Reference numeral 8 is a gate electrode layer 4 and an element isolation region 2.
A first interlayer insulating film formed so as to cover the first interlayer insulating film, and a first contact hole formed by opening the first interlayer insulating film to reach the impurity layer of the semiconductor substrate.
Is a first side wall formed of, for example, an oxide film on the side wall of the first contact hole 9, and 11 is a first side wall.
The bit line formed through the contact hole 10 of FIG. 2 is formed by sequentially stacking, for example, a doped polysilicon film 12 and a tungsten silicon film 13.

Reference numeral 14 is a second interlayer insulating film formed so as to cover the bit line 11, and 15 is an opening of the first and second interlayer insulating films 8 and 14 until reaching the impurity layer 3 of the semiconductor substrate 1. The formed second contact hole, 16 is the second
Second sidewalls formed of, for example, an oxide film on the side walls of the contact hole 15, and lower electrodes 17 formed through the second contact hole 15 are formed of, for example, a polysilicon film. Reference numeral 18 is a dielectric film formed on the upper surface of the lower electrode 17, and 19 is an upper electrode formed so as to cover the dielectric film 18, which is made of, for example, a polysilicon film.

Reference numeral 20 is a capacitor composed of a lower electrode 17, a dielectric film 18 and an upper electrode 19, and 21 is an upper electrode 19.
A third interlayer insulating film formed so as to cover the first, second and third interlayer insulating films 8, 14 and 21 on the impurity layer 3 of the semiconductor substrate 1 or the second external wiring layer 30. 3rd contact hole formed by opening until reaching 2
Reference numeral 3 is a third sidewall formed on the side wall of the third contact hole 22, for example, an oxide film, and 24 is a plug film embedded in the third contact hole 22, for example, a tungsten film.

Reference numeral 25 is a first wiring film formed on the third interlayer insulating film 21 for electrically connecting to the plug film 24, and is made of, for example, an aluminum film. 26 is a fourth interlayer insulating film formed so as to cover the first wiring film 25,
Reference numeral 27 denotes a fourth contact hole formed by opening the fourth interlayer insulating film 26 until reaching the first wiring film 25.
Reference numeral 8 denotes a second wiring film formed through the fourth contact hole 27, which is made of, for example, an aluminum film. Two
Reference numeral 9 is a first external wiring layer formed outside the memory cell at the same time when the gate electrode layer 4 is formed, and reference numeral 30 is a second external wiring layer formed outside the memory cell at the same time when the bit line 11 is formed.

Next, a method of manufacturing the conventional semiconductor device having the above structure will be described with reference to FIGS. First, the element isolation region 2 is formed on the semiconductor substrate 1 (FIG. 29A). Next, the doped polysilicon film 5 and the tungsten silicon film 6 are sequentially stacked, and the gate electrode layer 4 is formed by etching leaving only a desired portion (FIG. 29B). Next, the impurity layer 3 is formed at a desired position in the active region surrounded by the element isolation region 2 of the semiconductor substrate 1.
To form. Next, the gate sidewall 7 is formed so as to cover the gate electrode layer 4. Next, the gate electrode layer 4
And the first interlayer insulating film 8 so as to cover the element isolation region 2
To form. Next, a first resist film 31 for contacting a bit line is formed on the first interlayer insulating film 8 (FIG. 24).
(A)).

Next, the first interlayer insulating film 8 is etched by using the first resist film 31 as a mask to form a first contact hole 9 reaching the upper surface of the impurity layer 3 (FIG. 29C). ). Next, the first resist film 31 is removed (FIG. 24B). At this time, for the purpose of high integration,
The first contact hole 9 is formed so that the end surface of the gate electrode layer 4 is present on the extended surface of the side wall of the first contact hole 9. Next, the first contact hole 9
The first sidewall 10 is formed on the sidewall of the. Then, the end surface of the gate electrode layer 4 exposed at the time of forming the first contact hole 9 is electrically insulated from other portions by the first sidewall 10 (FIG. 24C, FIG. 30A). )).

Next, the doped polysilicon 12 and the tungsten silicon film 13 are sequentially laminated and etched leaving only desired portions to form the bit line 11 and the second external wiring layer 30 (FIG. 30 (b)). . Next, the second interlayer insulating film 14 is formed so as to cover the bit line 11. Next, a second resist film 32 for lower electrode contact is formed on the second interlayer insulating film 14 (FIG. 24 (d)). Next, using the second resist film 32 as a mask, the first and second interlayer insulating films 8 and 14 are formed on the impurity layer 3 of the semiconductor substrate 1.
Etching is performed until the temperature reaches 10 .degree. To form the second contact hole 15 (FIGS. 25A and 30C). At this time, the end face of the gate electrode layer 4 is exposed at the time of forming the second contact hole 15 for the same reason as that at the time of forming the first contact hole 9.

Next, a second side wall 16 is formed on the side wall of the second contact hole 15 (FIG. 28). Then, the end surface of the gate electrode layer 4 exposed when the second contact hole 15 is formed is electrically insulated from other portions by the second sidewall 16 (FIG. 25).
(B)). Next, the lower electrode 17 is formed through the second contact hole 15 (FIG. 25C). Next, a dielectric film 18 and an upper electrode 19 are sequentially formed on the lower electrode 17 to form a capacitor 20 composed of the lower electrode 17, the dielectric film 18 and the upper electrode 19 (FIG. 26).
(A)).

Next, a third interlayer insulating film 21 is formed on the upper electrode 19. Next, a third resist film 33 for contact wiring is formed on the third interlayer insulating film 21 (FIG. 2).
6 (b)). Next, using the third resist film 33 as a mask, the first, second, and third interlayer insulating films 8, 14, and 21 are used as the impurity layer 3 of the semiconductor substrate 1 or the second external wiring layer 30.
Until the third contact hole 22 is reached, a third contact hole 22 is formed (FIG. 26C). At this time, for the same reason as when forming the first and second contact holes 9 and 15, the end faces of the first and second external wiring layers 29 and 30 are exposed when the third contact hole 22 is formed. are doing.

Next, a third side wall 23 is formed on the side wall of the third contact hole 22. The first and second portions exposed when the contact hole 22 is formed
The third end surfaces of the external wiring layers 29 and 30 are electrically insulated from other portions by the third sidewall 33 (FIG. 27A). Next, the plug film 24 is embedded in the third contact hole 22. Next, the first wiring film 24 is formed so as to be electrically connected to the plug film 24. next,
A fourth interlayer insulating film 26 is formed so as to cover the first wiring film 24 (FIG. 27B). Next, the fourth interlayer insulating film 2
6 is etched to reach the first wiring film 25 to form a fourth contact hole 27, and a second wiring film 28 is formed through the fourth contact hole 27 (FIG. 2).
3).

[0013]

The conventional semiconductor device is constructed as described above, and is arranged at the same position as the end faces of the gate electrode layer 4, the first and second external wiring layers 29, 30 for the purpose of high integration. Is formed so that the extended surfaces of the side walls of the first, second and third contact holes 9, 15, 22 come to
We have promoted miniaturization with higher integration. However, the first, second and third contact holes 9, 15, 22
First, second and third resist films 31, 3 during formation
When the mask displacements of Nos. 2 and 33 occur, the problem as shown in FIG. 32 occurs. As is clear from FIG. 32, when the mask displacement occurs and the exposed portion 4a of the gate electrode layer 4 is exposed in the first contact hole 9 (FIG. 31A), the first sidewall 10 is formed. Also the gate electrode layer 4
The film thickness t of the first sidewall 10 on the exposed portion is formed to be extremely thin (FIG. 31B), a sufficient breakdown voltage cannot be obtained, and the reliability of the semiconductor device decreases.

To solve the above problems, the gate electrode layer 4, the first and second external wiring layers 29 and 30 are formed at the positions where the first, second and third resist films 31, 32 and 3 are formed.
Although a method of forming with a margin corresponding to the mask deviation of No. 3 is conceivable, in that case, it is not possible to form the layout pattern as shown in FIG. 28, and eventually desired miniaturization can be promoted. become unable. Therefore, the flexibility of the layout pattern is also reduced.

The present invention has been made to solve the above problems, and a semiconductor device and a semiconductor device manufacturing which can improve the degree of freedom of a layout pattern without impairing reliability when forming a contact hole. It is about the method.

[0016]

Means for Solving the Problems Claim 1 according to the present invention.
In the method for manufacturing a semiconductor device, the second wiring layer to be electrically insulated from the first wiring layer is formed by etching a part or all of an exposed portion exposed in the contact hole, and then forming a side wall on the sidewall of the contact hole. A wall is formed.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein first and second wiring layers are formed on the same substrate, and an interlayer insulating film is formed so as to cover both wiring layers. In a method of manufacturing a semiconductor device, wherein an interlayer insulating film between both wiring layers is etched to reach a substrate to form a contact hole, a sidewall is formed on a sidewall of the contact hole, and a third wiring layer is formed in the contact hole. The sidewall is formed after etching a part or all of the exposed portion exposed in the contact hole of the first or second wiring layer at the time of forming the contact hole.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a first interlayer insulating film is formed on a semiconductor substrate and a first wiring layer is formed on the first interlayer insulating film. , First
A second interlayer insulating film is formed so as to cover the wiring layer of
And a second interlayer insulating film is etched to reach a semiconductor substrate to form a contact hole, a sidewall is formed on a sidewall of the contact hole, and a second wiring layer is formed in the contact hole. The side wall is formed after etching a part or all of the exposed portion of the first wiring layer exposed in the contact hole at the time of forming the contact hole.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, the first interlayer insulating film is formed so as to cover the first wiring layer, and the second interlayer insulating film is formed on the first interlayer insulating film. A wiring layer is formed, a second interlayer insulating film is formed so as to cover the second wiring layer, and the first and second interlayer insulating films are etched to reach the first wiring layer to form contact holes. In a method of manufacturing a semiconductor device in which a sidewall is formed on a side wall of a contact hole and a third wiring layer is formed in the contact hole, a second wiring layer is exposed in the contact hole during formation of the contact hole. The sidewall is formed after etching a part or the whole.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the second or third aspect, wherein a sidewall is formed on a side wall of the contact hole and then an impurity is injected into the substrate or the semiconductor substrate. It forms a layer.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein an element isolation region is formed on a semiconductor substrate,
A gate electrode layer is formed across the active region of the semiconductor substrate to reach the element isolation region, and a gate electrode layer to be a gate electrode is formed on the active region, and the interlayer insulating film and the element isolation region are etched until reaching the semiconductor substrate. A contact hole is formed, a sidewall is formed on the side wall of the contact hole, impurities are injected into the semiconductor substrate exposed in the contact hole using the sidewall of the contact hole as a mask to form an impurity layer, and the contact hole is formed. Form a bit line.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the sixth aspect, wherein after exposing a part or all of the exposed portion of the gate electrode layer exposed in the contact hole at the time of forming the contact hole. , To form sidewalls.

In the semiconductor device according to claim 8 of the present invention, the first wiring layer formed through the contact hole having the sidewall on the side wall should be electrically insulated from the first wiring layer. In a semiconductor device having a second wiring layer, the second wiring layer has a concave end surface, and the concave end surface is provided on an extended surface of a side wall of the contact hole.

According to a ninth aspect of the present invention, in a semiconductor device, a first wiring layer and a second wiring layer which are formed on the same substrate with a predetermined space, and first and second wiring layers are formed. An interlayer insulating film formed so as to cover the wiring layer, and the first and second
A contact hole formed by opening the interlayer insulating film between the wiring layers until reaching the substrate, a sidewall formed on the side wall of the contact hole, and first and second wirings formed through the contact hole. In a semiconductor device including a layer and a third wiring layer to be insulated, each of the first and second wiring layers has a concave end surface, and the concave end surface is provided on an extended surface of a side wall of the contact hole. It is a thing.

According to a tenth aspect of the present invention, in a semiconductor device, a semiconductor substrate, an element isolation region formed on the semiconductor substrate, and an active region of the semiconductor substrate are traversed to reach the element isolation region. Together with the gate electrode layer which will be the gate electrode on the active region, the interlayer insulating film formed so as to cover the gate electrode layer and the interlayer insulating film, and through the interlayer insulating film and the element isolation region to reach the semiconductor substrate. A contact hole formed by opening, a sidewall formed on the sidewall of the contact hole, an impurity layer formed by implanting impurities into the semiconductor substrate exposed in the contact hole, and a contact hole And a bit line.

A semiconductor device according to an eleventh aspect of the present invention is the semiconductor device according to the tenth aspect, wherein the gate electrode layer has a concave end face, and the concave end face is provided on an extended surface of a side wall of the contact hole. is there.

[0027]

In the method for manufacturing a semiconductor device according to the first aspect of the present invention, the second wiring layer, which is to be electrically insulated from the first wiring layer, is partially or wholly exposed in the contact hole. After that, since the sidewall is formed on the side wall of the contact hole, the first wiring layer and the second wiring layer are reliably electrically insulated by the sidewall in the contact hole.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, the first and second wiring layers are formed on the same substrate, and the interlayer insulating film is formed so as to cover both wiring layers.
The interlayer insulating film between both wiring layers is etched to reach the substrate to form a contact hole, a sidewall is formed on the side wall of the contact hole, and a third hole is formed in the contact hole.
In the method for manufacturing a semiconductor device in which the wiring layer is formed, the sidewall is formed after etching a part or all of the exposed portion exposed in the contact hole of the first or second wiring layer when forming the contact hole. , The side walls reliably insulate the first and second wiring layers and the third wiring layer formed on the same substrate in the contact holes.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, the first interlayer insulating film is formed on the semiconductor substrate, and the first wiring layer is formed on the first interlayer insulating film. A second interlayer insulating film is formed so as to cover the first wiring layer, the first and second interlayer insulating films are etched until reaching the semiconductor substrate to form a contact hole, and a sidewall is formed on a sidewall of the contact hole. In a method of manufacturing a semiconductor device, which comprises forming a second wiring layer in a contact hole, after etching a part or all of an exposed portion of the first wiring layer exposed in the contact hole during formation of the contact hole, Since the sidewall is formed, the first wiring layer and the second wiring layer are reliably electrically insulated by the sidewall in the contact hole.

In the method of manufacturing a semiconductor device according to a fourth aspect of the present invention, the first interlayer insulating film is formed so as to cover the first wiring layer, and the second wiring is formed on the first interlayer insulating film. A layer is formed, a second interlayer insulating film is formed so as to cover the second wiring layer, and the first and second interlayer insulating films are etched to reach the first wiring layer to form a contact hole, In a method of manufacturing a semiconductor device in which a sidewall is formed on a sidewall of a contact hole and a third wiring layer is formed in the contact hole, a second wiring layer is exposed in the contact hole during formation of the contact hole. Since the side wall is formed after etching a part or all, the first wiring layer and the second wiring layer are formed in the contact hole.
The wiring layer is surely electrically insulated from the side wall.

In the method of manufacturing a semiconductor device according to a fifth aspect of the present invention, since the side wall is formed on the side wall of the contact hole, impurities are injected into the substrate or the semiconductor substrate to form an impurity layer. An impurity layer is surely formed on the substrate or the semiconductor substrate.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the element isolation region is formed on the semiconductor substrate, and the element isolation region is formed across the active region of the semiconductor substrate and reaches the element isolation region. A gate electrode layer to be a gate electrode is formed on the region, the interlayer insulating film and the element isolation region are etched to reach the semiconductor substrate to form a contact hole, a sidewall is formed on a sidewall of the contact hole, and a contact hole is formed. Impurities are injected into the semiconductor substrate exposed in the contact holes using the sidewalls as masks to form impurity layers, and bit lines are formed through the contact holes, so that the bit lines are formed on the element isolation regions.

In the method of manufacturing a semiconductor device according to a seventh aspect of the present invention, the sidewall is formed after etching a part or all of the exposed portion of the gate electrode layer exposed in the contact hole when the contact hole is formed. Therefore, in the contact hole, the gate electrode layer and the bit line are reliably electrically insulated by the sidewall.

Further, in the semiconductor device according to the eighth aspect of the present invention, the first wiring layer and the second wiring layer are reliably electrically insulated from each other by the sidewall in the contact hole.

Further, in the semiconductor device according to claim 9 of the present invention, the first and second wiring layers and the third wiring layer are reliably electrically insulated from each other by the sidewalls in the contact holes.

In the semiconductor device according to the tenth aspect of the present invention, the contact hole for the bit line and the bit line are formed on the element isolation region.

Further, in the semiconductor device according to claim 11 of the present invention, the gate electrode layer and the bit line are surely electrically insulated by the sidewall in the contact hole.

[0038]

【Example】

Example 1. Embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a top view showing the configuration of the semiconductor device shown in FIG. In the figure, the same parts as those in the conventional case are designated by the same reference numerals, and the description thereof will be omitted. 34,
Reference numeral 35 denotes first and second gate electrode layers as first and second wiring layers which are formed by traversing the active region surrounded by the element isolation region 2 of the semiconductor substrate 1 and reaching the element isolation region 2. And the first and second gate electrode layers 34, 35
Are formed at predetermined intervals and serve as a gate electrode on the active region. 36 is the first and second gate electrode layers 34, 3
5 is a side wall for a gate that is formed so as to cover 5 and is made of an oxide film, for example.

37 is the first and second gate electrode layers 3
4, 35 and the upper surface of the semiconductor substrate 1 are flattened, and an interlayer insulating film made of, for example, an oxide film, 38 is an interlayer insulating film 37 between the first and second gate electrode layers 34, 35. A contact hole formed by opening to reach the impurity layer 3 of the semiconductor substrate 1, 39 is formed on a side wall of the contact hole 38, for example, a side wall made of an oxide film, and 40 is formed through the contact hole 38. 3 is a bit line as a wiring layer. Reference numeral 41 denotes a concave end surface portion of the first gate electrode layer 34, which is formed on the extended surface of the side wall of the contact hole 38.

Next, a method of manufacturing the semiconductor device of Example 1 configured as described above will be described with reference to FIGS. First, the element isolation region 2 is formed on the semiconductor substrate 1. Next, for example, a doped polysilicon film and a tungsten silicon film are sequentially laminated and etched leaving only desired portions to form first and second gate electrodes 34 and 35 (FIG. 5A). Next, impurities are implanted into the active region surrounded by the element isolation region 2 of the semiconductor substrate 1 using the first and second gate electrode layers 34 and 35 as masks,
The impurity layer 3 is formed. Next, both gate electrode layers 34, 3
Gate sidewalls 36 are formed so as to cover 5 respectively. Next, an interlayer insulating film 37 is laminated so as to cover both the gate electrode layers 34 and 35 and the semiconductor substrate 1 (FIG. 3).
(A)).

Next, a resist film 42 patterned for bit line contact is formed on the interlayer insulating film 37 (FIG. 3B). Next, using the resist film 42 as a mask, the interlayer insulating film 37 is etched to the upper surface of the semiconductor substrate 1 to form a contact hole 38. At this time, the exposed portion 3 of the first gate electrode layer 34 is formed in the contact hole 38.
4a is exposed (FIGS. 3 (c) and 5 (b)). Next, the resist film 42 is removed (FIG. 3D). As described above, in the etching process for forming the contact hole 38 and the removing process of the resist film 42, the exposed portion 34a is formed.
Are never removed.

Next, the exposed portion 34a is removed by, for example, anisotropic or isotropic etching to form a concave end face portion 41 (FIGS. 4 (a) and 5 (c)). At this time, the upper surface of the semiconductor substrate 1 exposed in the contact hole 38 is subjected to surface treatment, and the contact hole 3 is formed in this portion.
8. The deteriorated layer and the like attached during the formation are removed. Next, an oxide film 39a is laminated on the interlayer insulating film 37 (FIG. 4).
(B)). Next, etch back is performed to form sidewalls 39 on the sidewalls in the contact holes 38 (FIG. 4).
(C)). Next, for example, a doped polysilicon film and a tungsten silicon film are sequentially stacked on the interlayer insulating film 37, and etching is performed leaving only a desired portion to form a bit line 40 through the contact hole 38 (FIGS. 1 and 1). 2).

In the semiconductor device of Example 1 configured as described above, the sidewall 39 is formed after removing the exposed portion 34a exposed in the contact hole 38, so that in the contact hole 38. , The first gate electrode layer 3 as well as the second gate electrode layer 35.
4 and the bit line 40 can be reliably electrically insulated by the sidewall 39. Therefore, a margin for the mask shift of the resist film 42 is not required, so that the degree of freedom of the layout pattern can be improved without impairing the reliability.

When the exposed portion 34a is etched, the upper surface of the semiconductor substrate 1 exposed in the contact hole 38 is surface-treated to remove the altered layer and the like, so that the contact resistance between the semiconductor substrate 1 and the bit line 40 is reduced. Can be lowered.

Example 2. FIG. 6 is a sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention. FIG. 7 shows FIG.
3 is a top view showing the configuration of the semiconductor device shown in FIG. In the figure, the same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. Reference numerals 43 and 44 denote first and second gates as first and second wiring layers formed across the active region surrounded by the element isolation region 2 of the semiconductor substrate 1 and reaching the element isolation region 2. In the electrode layer, the first and second gate electrode layers 43 and 44 are formed at a predetermined interval and serve as gate electrodes on the active region. Reference numeral 45 is a sidewall for a gate formed on the sidewalls of the first and second gate electrode layers 43 and 44.

46 denotes the first and second gate electrode layers 4
3, 44 and an interlayer insulating film formed so as to cover the semiconductor substrate 1, 47 denotes first and second gate electrode layers 43, 4
4 is a contact hole formed by opening the interlayer insulating film 46 between 4 and 4 to reach the impurity layer 3 of the semiconductor substrate 1, 48 is a sidewall formed on the side wall of this contact hole 47, and 49 is a via the contact hole 47. It is a bit line as the formed third wiring layer. Reference numerals 50 and 51 denote concave end surface portions of the first and second gate electrode layers 43 and 44, which are formed on the extended surface of the side wall of the contact hole 47.

Next, a method of manufacturing the semiconductor device of the second embodiment having the above structure will be described with reference to FIGS. First, similarly to the first embodiment, after forming the element isolation region 2 on the semiconductor substrate 1, the first and second gate electrode layers 43 and 44 are formed, the impurity layer 3 is formed, and the gate side is formed. The wall 45 is formed. Next, an interlayer insulating film 46 is laminated so as to cover both the gate electrode layers 43 and 44 and the semiconductor substrate 1. Next, a resist film 52 patterned for bit line contact is formed on the interlayer insulating film 46 (FIG. 8A).

Next, the interlayer insulating film 46 is etched up to the upper surface of the semiconductor substrate 1 using the resist film 52 as a mask to form a contact hole 47. At this time, the first and second gate electrode layers 43 and 44 are formed in the contact hole 47.
The exposed portions 43a and 44a of the are exposed. Next, the resist film 52 is removed (FIGS. 8B and 9A). In this way, etching when forming the contact hole 47,
Alternatively, in the step of removing the resist film 52, the exposed portion 43
The a and 44a are not removed.

Next, the exposed portions 43a and 44a are removed by, for example, anisotropic or isotropic etching, and the concave end face portion 50,
51 is formed (FIG.8 (c), FIG.9 (b)). On this occasion,
Semiconductor substrate 1 exposed at contact hole 47
The upper surface of is subjected to a surface treatment, and an altered layer or the like attached to this portion when the contact hole 47 is formed is removed. Next, the sidewall 48 is formed on the sidewall of the contact hole 47 (FIG. 8D). Next, as in the first embodiment, the bit line 4 is inserted through the contact hole 47.
9 is formed (FIGS. 6 and 7).

In the semiconductor device of the second embodiment configured as described above, the sidewalls 48 are formed after removing the exposed portions 43a and 44a exposed in the contact holes 47, so the contact holes 47 are formed. Of the first and second gate electrode layers 43 and 44 and the bit line 49.
The sidewall 48 ensures reliable electrical insulation. Therefore, the same effect as that of the first embodiment can be obtained, and the interval between the first and second gate electrode layers 43 and 44 can be set regardless of the diameter of the contact hole 47, or the first and second gate electrode layers 43 and 44 can be formed. Since the diameter of the contact hole 47 can be determined without being influenced by the distance between the gate electrode layers 43 and 44, the degree of freedom of the layout pattern can be further improved.

The first and second gate electrode layers 43,
It goes without saying that 44 is formed within the range where the contact hole 47 is not broken.

Example 3. FIG. 10 is a sectional view showing the structure of the semiconductor device according to the third embodiment of the present invention. In the figure, the same parts as those in each of the above-described embodiments are designated by the same reference numerals and the description thereof will be omitted. 53 is a gate electrode layer, 54 is this gate electrode layer 5
3, a gate sidewall formed so as to cover 3
5 is a bit line, 56 is an interlayer insulating film formed so as to cover the bit line 55, 57 is a contact hole formed by opening the interlayer insulating film 56 to reach the semiconductor substrate 1, and 58 is this contact hole. A sidewall is formed on the side wall 57, 59 is a second impurity layer formed by implanting impurities using the sidewall 58 as a mask, 60 is a lower electrode for a capacitor formed through the contact hole 57, 61 Is a concave end surface portion of the gate electrode layer 53, and is formed on the extended surface of the side wall of the contact hole 57.

Next, a method of manufacturing the semiconductor device of the third embodiment having the above structure will be described with reference to FIGS. First, similarly to each of the above-described embodiments, after forming the element isolation region 2 on the semiconductor substrate 1, the gate electrode layer 53 is formed. Next, the gate electrode layer 53 and the element isolation region 2
Impurities are implanted using the as a mask to form an impurity layer 3.
Next, after forming the gate sidewall 54 so as to cover the gate electrode layer 53, the bit line 55 is formed.

Next, an interlayer insulating film 56 is formed so as to cover the bit lines 55, and a resist film 62 patterned for lower electrode contact is formed thereon (FIG. 11).
(A)). Next, using the resist film 62 as a mask, the interlayer insulating film 56 is etched to the upper surface of the semiconductor substrate 1 to form a contact hole 57. At this time, the exposed portion 53a of the gate electrode layer 53 is exposed in the contact hole 57. Next, the resist film 62 is removed (FIG. 11).
(B)). In this way, the exposed portion 53a is not removed in the etching when the contact hole 57 is formed or in the step of removing the resist film 62.

Next, the exposed portion 53a is removed by, for example, anisotropic or isotropic etching to form a concave end face portion 61 (FIG. 11C). Although a top view is not shown here, a concave end face portion 61 is formed in the gate electrode layer 53, and this portion is formed in the contact hole 5 as in the above embodiments.
It is clear from the figure that it is on the extended surface of the side wall of No. 7.
At this time, the upper surface of the semiconductor substrate 1 exposed in the contact holes 57 is subjected to a surface treatment, and the altered layer or the like attached to the contact holes 57 when the contact holes 57 are formed is removed.

Next, sidewalls 58 are formed on the sidewalls of the contact holes 57. Next, using the interlayer insulating film 56 and the sidewall 58 as a mask, the second impurity layer 59 having a shape self-aligned with the opening of the contact hole 57 is formed by implanting, for example, phosphorus as the impurity 63 into the semiconductor substrate 1. Are formed (FIG. 11D). By doing so, even if the contact hole 57 is formed so as to deviate from the impurity layer 3, the second impurity layer 59 is reliably formed on the semiconductor substrate 1 at the opening of the contact hole 57. Next, for example, polysilicon or doped polysilicon is laminated through the contact hole 57, and the lower electrode 60 is formed leaving only a desired portion (FIG. 10).

In the semiconductor device of the third embodiment having the above-described structure, the sidewall 58 is formed after removing the exposed portion 53a exposed in the contact hole 57, so that in the contact hole 57. , The gate electrode layer 53 and the lower electrode 60 are formed by the sidewall 58,
It can be reliably electrically insulated. Therefore, the same effect as that of each of the above-described embodiments can be obtained, and the impurity 63 is injected after the sidewall 58 is formed, and the second impurity layer 59 is formed.
Since the second impurity layer 59 is formed, the second impurity layer 59 is surely present at the position where the lower electrode 60 is in contact with the semiconductor substrate 1.

Example 4. 12 is a sectional view showing the structure of a semiconductor device according to a fourth embodiment of the present invention. In the figure, 6
Reference numeral 4 is a first wiring layer made of aluminum, 65 is a first interlayer insulating film formed so as to cover the first wiring layer 64, and 66 is formed on the first interlayer insulating film 65. For example, a second wiring layer made of aluminum, 67 is a second interlayer insulating film formed so as to cover the second wiring layer 66, and 68 is the first and second wiring layers until the upper surface of the first wiring layer 64 is reached. Contact holes formed by opening the second interlayer insulating films 65 and 67, and 69 are contact holes 6
8 is a side wall formed on the side wall, 70 is a third wiring layer formed of, for example, aluminum through the contact hole 68, and 71 is a concave end surface portion formed on the second wiring layer 66. It is formed on the extended surface of the side wall of the contact hole 68.

Then, Example 4 formed as described above
The method of manufacturing the semiconductor device of will be described with reference to FIGS. First, the first interlayer insulating film 65 is formed on the first wiring layer 64. Next, the first interlayer insulating film 65
A second wiring layer 66 is formed thereon, and a second interlayer insulating film 67 is formed thereon. Then, a patterned resist film 72 for the third wiring layer contact is formed on the second interlayer insulating film 67 (FIG. 13A). Next, using the resist film 72 as a mask, the first and second interlayer insulating films 6 are formed.
5, 67 are etched to the upper surface of the first wiring layer 64,
A contact hole 68 is formed. At this time, the exposed portion 66a of the second wiring layer 66 is exposed in the contact hole 68. Next, the resist film 72 is removed (FIG. 13).
(B)). In this way, the exposed portion 66a is not removed in the etching for forming the contact hole 68 or the step of removing the resist film 72.

Next, the exposed portion 66a is removed by, for example, isotropic etching to form a concave end surface portion 71 (FIG. 13).
(C)). At this time, the etching conditions are selected so that the upper surface of the first wiring layer 64 exposed in the contact hole 68 is not etched so much. Next, sidewalls 69 are formed on the sidewalls of the contact holes 68 (FIG. 13D). Next, the third wiring layer 70 is formed through the contact hole 68 (FIG. 12).

In the semiconductor device of the fourth embodiment having the above-described structure, the sidewall 69 is formed after removing the exposed portion 66a exposed in the contact hole 68. The second wiring layer 66 and the third wiring layer 70 can be reliably electrically insulated by the sidewall 69. Therefore, it is possible to obtain the same effect as that of each of the above embodiments.

Example 5. In the above-described fourth embodiment, the description has been made between the first and third wiring layers 64 and 70, but the following description will be made between the wiring layer and the semiconductor substrate with reference to FIGS. 14 and 15. A third resist film 33 is formed through the same steps as in the conventional case (FIG. 14A). Next, using the third resist film 33 as a mask, the first, second and third interlayer insulating films 8, 14 and 21 are etched until they reach the impurity layer of the semiconductor substrate 1 or the second external wiring layer 30. , Third contact hole 22 is formed.
At this time, the exposed portion 30a of the second external wiring layer 30 is exposed in the third contact hole 22 (FIG. 14).
(B)).

Next, the exposed portion 30a is removed by, for example, isotropic etching to form a concave end surface portion 73. The concave end surface portion 73 is formed on the extension surface of the side wall of the third contact hole 22 (FIG. 14C).
At this time, the etching conditions are selected so that the upper surface of the second external wiring layer 30 exposed in the third contact hole 22 is not etched much. next,
Similar to the conventional case, the third sidewall 23 is formed on the sidewall of the third contact hole 22 (FIG. 15).
(A)). Next, the plug film 24 is embedded in the third contact hole 22. Next, the first wiring film 24 is formed so as to be electrically connected to the plug film 24. Then the first
A fourth interlayer insulating film 26 is formed so as to cover the wiring film 24 (see FIG. 15B).

In the semiconductor device of Example 5 configured as described above, the exposed portion 30a exposed in the third contact hole 22 is removed, and then the third sidewall 23 is formed.
Therefore, in the third contact hole 22, the second external wiring layer 30 and the plug film 24 form the third contact hole 22.
With the side wall 23, it can be surely electrically insulated. Therefore, it is possible to obtain the same effect as that of each of the above embodiments. Needless to say, the second external wiring layer 30 at this time means the one formed at the right end on the paper surface of FIGS. 14 and 15 which must be electrically insulated from the plug film 24.

Example 6. 16 is a sectional view showing the structure of a semiconductor device according to a sixth embodiment of the present invention. FIG. 17 shows FIG.
3 is a top view of the semiconductor device shown in FIG. In the figure, the same parts as those in each of the above-described embodiments are designated by the same reference numerals and the description thereof will be omitted. A gate electrode layer 74 is formed so as to cross the active region of the semiconductor substrate 1 and reach the element isolation region 2. The gate electrode layer 74 serves as a gate electrode on the active region. 75 is a gate electrode layer 74
Sidewalls for gates formed so as to cover
Is an interlayer insulating film formed so as to cover the gate electrode layer 74 and the semiconductor substrate 1.

Reference numeral 77 is a contact hole formed by opening the interlayer insulating film 76 and the element isolation region 2 to reach the semiconductor substrate 1, 78 is a sidewall formed on the side wall of the contact hole 77, and 79 is this sidewall. Second formed by implanting impurities using 78 as a mask
Of the impurity layer, 80 is a bit line formed through the contact hole 77, and 81 is a concave end surface portion of the gate electrode layer 74, which is formed on the extended surface of the side wall of the contact hole 77.

Next, a method of manufacturing the semiconductor device of the sixth embodiment having the above structure will be described with reference to FIGS. First, similarly to each of the above-described embodiments, after forming the element isolation region 2 on the semiconductor substrate 1 (FIG. 19A), the gate electrode layer 74 is formed (FIG. 19B), and the gate sidewall is formed. Forming 75. Next, the interlayer insulating film 76 is laminated so as to cover the gate electrode layer 74 and the semiconductor substrate 1. Next, a resist film 82 patterned for bit line contact is formed on the interlayer insulating film 76 (FIG. 18).
(A)). Normally, the bit line contact is made in the active region surrounded by the element isolation region 2, but the resist film 82 is patterned so as to make the bit line contact on the element isolation region 2 here.

Next, using the resist film 82 as a mask, the interlayer insulating film 76 and the element isolation region 2 are etched up to the upper surface of the semiconductor substrate 1 to form a contact hole 77.
At this time, the exposed portion 74a of the gate electrode layer 74 is exposed in the contact hole 77. Next, the resist film 52 is removed (FIGS. 18B and 19C). As described above, the exposed portion 74a is not removed in the etching process for forming the contact hole 77 or the removing process of the resist film 82. Next, the exposed portion 74a is removed by, for example, anisotropic or isotropic etching to form a concave end face portion 81 (FIGS. 18C and 20A). At this time, the upper surface of the semiconductor substrate 1 exposed in the contact holes 77 is subjected to a surface treatment, and an altered layer or the like attached to the contact holes 77 when the contact holes 77 are formed is removed.

Next, sidewalls 78 are formed on the sidewalls of the contact holes 77 (FIG. 20B). Next, using the interlayer insulating film 76 and the sidewall 78 as a mask, arsenic, phosphorus, or the like, for example, is injected as the impurity 83 into the semiconductor substrate 1 having the element isolation region 2 formed on the upper surface to form a second impurity layer 79. (FIG.18 (d)). next,
The bit line 80 is formed through the contact hole 77 (FIGS. 16 and 17).

In the semiconductor device of Example 6 configured as described above, the sidewall 78 is formed after the exposed portion 74a exposed in the contact hole 77 is removed, so that the inside of the contact hole 77 is formed. , The gate electrode layer 74 and the bit line 80 are formed by the sidewall 78,
It can be reliably electrically insulated. Therefore, it goes without saying that the same effects as those of the above-described respective embodiments can be obtained.

Further, since the contact hole 77 is formed on the element isolation region 2, the exposed portion 74a of the gate electrode layer 74 exposed in the contact hole 77 does not form a gate electrode. Even if 74a is removed, it does not affect the gate electrode length.

Further, since the contact hole 77 is formed on the element isolation region 2, the following effects are produced. This will be described with reference to FIG. 21.
As shown in FIG. 1A, the active region 84 is formed, and the bit line contact hole 85 is formed on the active region 84. However, in this invention,
As shown in FIG. 21B, the active region 86 is formed,
A bit line contact hole 87 is formed on the element isolation region 2 outside the active region 86.

Here, the distance a between the active regions 84 and the distance a between the active regions 86 and the bit line contact holes 87.
On the other hand, the other distance b between the active regions 84 and the distance c between the active regions 86 are inevitably determined. Therefore, the present invention does not require a protrusion on the active region 84 itself for forming the bit line contact hole 85 on the active region 84 as in the conventional case. The distance c between the active regions 86 of the invention can necessarily be formed short. Therefore, the degree of freedom of the layout pattern can be further improved.

Example 7. In the sixth embodiment, the sidewalls 78 are formed after removing the exposed portions 74a formed in the contact holes 77, and the bit lines 80 are connected to the element isolation regions 2.
Although the example of forming the above is shown, it is needless to say that the degree of freedom of the layout pattern can be improved by forming the bit line on the element isolation region as described in the sixth embodiment.

Example 8. In each of the above-described embodiments, an example is shown in which all exposed portions of the wiring exposed in the contact hole are removed when the contact hole is formed, but the present invention is not limited to this, and as shown in FIG. Even if the sidewall 90 is formed by removing a part of the exposed portion 89a of the wiring 89 exposed in the contact hole 88 to form the exposed portion 89b, as shown in FIG.
It is prevented that the first side wall 10 is formed to be as thin as the film thickness t as in the conventional case shown in FIG. 1 (b), the side wall 90 is formed to be thick, and a sufficient breakdown voltage is obtained. be able to. Therefore, it is possible to obtain the same effect as that of each of the above embodiments. Further, by not completely removing the exposed portion 89a, it is effective when the portion 91 exposed in the contact hole 88 is difficult to have etching selectivity with the exposed portion 89a.
In this case as well, similarly to each of the above-described embodiments, the concave end surface portion 92 is formed on the wiring 89, and the concave end surface portion 92 is formed.
Needless to say, is formed on the extended surface of the side wall of the contact hole 88.

Example 9. In each of the above-described embodiments, other examples such as the gate electrode layer and the bit line have been described, but the present invention is not limited thereto. When forming the layer, after etching a part or all of the exposed portion exposed in the contact hole of the second wiring layer to be electrically insulated from the first wiring layer, the sidewall is formed. It goes without saying that this is applicable to all cases where the first wiring layer is formed.

[0077]

As described above, according to the first aspect of the present invention, a method of manufacturing a semiconductor device in which a sidewall is formed on a side wall of a contact hole and then a first wiring layer is formed through the contact hole. In order to form a sidewall on the side wall of the contact hole after etching a part or all of the exposed portion of the second wiring layer to be electrically insulated from the first wiring layer in the contact hole. Therefore, the first wiring layer and the second wiring layer are reliably electrically insulated from each other by the sidewalls in the contact hole, so that it is not necessary to take a margin when forming the contact hole, and reliability is impaired. Provided is a method for manufacturing a semiconductor device, which can improve the degree of freedom of a layout pattern without a need.

According to a second aspect of the present invention, the first and second wiring layers are formed on the same substrate, the interlayer insulating film is formed so as to cover both wiring layers, and the interlayers between both wiring layers are formed. In the method of manufacturing a semiconductor device, the insulating film is etched until reaching the substrate to form a contact hole, a sidewall is formed on a side wall of the contact hole, and a third wiring layer is formed in the contact hole. Since the side wall is formed after etching a part or all of the exposed portion exposed in the contact hole of the first or second wiring layer, the first side formed on the same substrate in the contact hole. Also, since the second wiring layer and the third wiring layer are reliably electrically insulated by the side wall, a margin is taken when forming the contact hole. Since there is no necessity to provide a method of manufacturing a semiconductor device which can improve the flexibility of the layout pattern without impairing reliability.

According to claim 3 of the present invention, the first interlayer insulating film is formed on the semiconductor substrate, the first wiring layer is formed on the first interlayer insulating film, and the first wiring is formed. A second interlayer insulating film is formed so as to cover the layer, the first and second interlayer insulating films are etched to reach the semiconductor substrate to form a contact hole, a sidewall is formed on a side wall of the contact hole, and a contact is formed. In a method of manufacturing a semiconductor device in which a second wiring layer is formed in a hole, a sidewall is formed after etching a part or all of an exposed portion of the first wiring layer exposed in the contact hole when forming the contact hole. Since the first wiring layer and the second wiring layer are reliably electrically insulated from each other in the contact hole by the sidewall, the mask is formed when the contact hole is formed. There is no need to take Jin, to provide a method of manufacturing a semiconductor device which can improve the flexibility of the layout pattern without impairing reliability.

According to the fourth aspect of the present invention, the first interlayer insulating film is formed so as to cover the first wiring layer, and the second wiring layer is formed on the first interlayer insulating film. A second interlayer insulating film is formed to cover the second wiring layer, and the first and second
In the method of manufacturing a semiconductor device, the interlayer insulating film is etched to reach the first wiring layer to form a contact hole, a sidewall is formed on a side wall of the contact hole, and a third wiring layer is formed in the contact hole. Since the second wiring layer etches a part or all of the exposed portion exposed in the contact hole at the time of forming the contact hole, the sidewall is formed, so that the first and second portions are formed in the contact hole. Wiring layer and third
Since the wiring layer is reliably electrically insulated from the wiring layer by the side wall, it is not necessary to make a margin at the time of forming the contact hole, so that the degree of freedom of the layout pattern can be improved without impairing the reliability. A method for manufacturing the same is provided.

According to a fifth aspect of the present invention, in the second or third aspect, the sidewall is formed on the side wall of the contact hole, and then the impurity is injected into the substrate or the semiconductor substrate to form the impurity layer. Since the impurity layer is surely formed on the substrate or the semiconductor substrate below the contact hole, the method for manufacturing the semiconductor device in which the wiring layer formed through the contact hole is surely connected to the impurity layer is provided. To do.

According to the sixth aspect of the present invention, the element isolation region is formed on the semiconductor substrate, the element isolation region is formed across the active region of the semiconductor substrate to reach the element isolation region, and at the same time, on the active region. A gate electrode layer to be a gate electrode is formed, the interlayer insulating film and the element isolation region are etched to reach the semiconductor substrate to form a contact hole, a sidewall is formed on the side wall of the contact hole, and the sidewall of the contact hole is masked. As the impurity layer is formed by injecting an impurity into the semiconductor substrate exposed in the contact hole, and the bit line is formed through the contact hole, the bit line is formed on the element isolation region. Provided is a semiconductor device manufacturing method capable of improving the degree of freedom of a layout pattern without impairing reliability.

According to a seventh aspect of the present invention, in the sixth aspect, the sidewall is formed after etching a part or all of the exposed portion of the gate electrode layer exposed in the contact hole at the time of forming the contact hole. Since the gate electrode layer and the bit line are reliably electrically insulated from each other by the sidewalls in the contact hole, it is not necessary to take a margin when forming the contact hole, and the reliability is impaired. There is provided a method of manufacturing a semiconductor device which can improve the degree of freedom of a layout pattern without being affected by a gate electrode length because a bit line is formed on an element isolation region.

According to the eighth aspect of the present invention, the first wiring layer formed through the contact hole having the sidewall on the side wall and the second wiring layer to be electrically insulated from the first wiring layer. A semiconductor device having a wiring layer of
Since the wiring layer has a concave end surface and the concave end surface is provided on the extended surface of the side wall of the contact hole, the first wiring layer and the second wiring layer have sidewalls inside the contact hole. As a result, the semiconductor device is surely electrically insulated, so that it is not necessary to take a margin when forming the contact hole, and therefore, the semiconductor device capable of improving the flexibility of the layout pattern without impairing the reliability is provided.

According to claim 9 of the present invention, the first wiring layer and the second wiring layer, which are formed on the same substrate with a predetermined space, and the first and second wiring layers. An interlayer insulating film formed so as to cover the contact hole, a contact hole formed by opening the interlayer insulating film between the first and second wiring layers until reaching the substrate, and a side formed on the sidewall of the contact hole. In a semiconductor device including a wall and a third wiring layer that is formed through a contact hole and is to be insulated from the first and second wiring layers, the first and second wiring layers have concave end faces, respectively. However, since the concave end surface is provided on the extended surface of the side wall of the contact hole, the first and second wiring layers and the third wiring layer are surely electrically connected to each other by the sidewall in the contact hole. Is insulated to The predetermined spacing of the margin forming the contact holes are first and second wiring layers, or the first
Since the predetermined distance between the second wiring layer and the second wiring layer can be formed without being influenced by the size of the contact hole, a semiconductor device in which the degree of freedom of the layout pattern can be improved without impairing reliability. provide.

According to a tenth aspect of the present invention, a semiconductor substrate, an element isolation region formed on the semiconductor substrate,
A gate electrode layer which is formed over the active region of the semiconductor substrate to reach the element isolation region and which serves as a gate electrode on the active region, and an interlayer insulating film formed so as to cover the gate electrode layer and the interlayer insulating film. A contact hole formed through the interlayer insulating film and the element isolation region to reach the semiconductor substrate, a sidewall formed on the sidewall of the contact hole, and an impurity in the semiconductor substrate exposed in the contact hole. Since the impurity layer formed by injecting and the bit line formed through the contact hole are provided, the bit line is formed on the element isolation region, so that the layout pattern of the layout pattern can be formed without impairing reliability. Provided is a semiconductor device capable of improving the degree of freedom.

According to the eleventh aspect of the present invention, in the eleventh aspect, the gate electrode layer has the concave end face, and the concave end face is provided on the extended surface of the side wall of the contact hole. In the contact hole, the gate electrode layer and the bit line are reliably electrically insulated by the side wall, so that it is not necessary to take a margin when forming the contact hole, and therefore the degree of freedom of layout pattern can be reduced without impairing reliability. It is possible to provide a semiconductor device in which the bit line is formed on the element isolation region and which is not affected by the gate electrode length.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a top view showing the configuration of the semiconductor device shown in FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG.

FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG.

5 is a top view showing a manufacturing process of the semiconductor device shown in FIG. 2. FIG.

FIG. 6 is a sectional view showing a configuration of a semiconductor device according to the present invention.

FIG. 7 is a top view showing the configuration of the semiconductor device shown in FIG.

8 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG.

9 is a top view showing a manufacturing process of the semiconductor device shown in FIG. 7. FIG.

FIG. 10 is a sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention.

11 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG.

FIG. 12 is a sectional view showing the structure of a semiconductor device according to a fourth embodiment of the present invention.

13 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG.

FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment of the invention.

FIG. 15 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 16 is a sectional view showing a structure of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 17 is a top view showing the configuration of the semiconductor device shown in FIG.

18 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG.

19 is a top view showing the manufacturing process of the semiconductor device shown in FIG.

20 is a top view showing a manufacturing process of the semiconductor device shown in FIG.

FIG. 21 is an explanatory diagram for explaining the effect of the semiconductor device of the sixth embodiment of the present invention.

FIG. 22 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the eighth embodiment of the present invention.

FIG. 23 is a sectional view showing a configuration of a conventional semiconductor device.

FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 23.

FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 23.

FIG. 26 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 23.

FIG. 27 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 23.

28 is a top view showing the configuration of the semiconductor device shown in FIG. 23. FIG.

29 is a top view showing a manufacturing process for the semiconductor device shown in FIG. 28. FIG.

30 is a top view showing a manufacturing process for the semiconductor device shown in FIG. 28. FIG.

FIG. 31 is an explanatory diagram illustrating a problem of a conventional semiconductor device.

[Explanation of symbols]

30a, 34a, 43a, 44a, 53a, 66a, 7
4a, 89a, 89b Exposed part, 34, 43 First gate electrode layer, 35, 44 First gate electrode layer, 38, 4
7,57,68,77,88 Contact hole, 3
9,48,58,69,78,90 Sidewall,
40, 49, 55, 80 bit lines, 41, 50, 5
1, 61, 71, 73, 81, 92 Concave end face portion, 5
3,74 gate electrode layer, 59,79 second impurity layer, 60 lower electrode, 64 first wiring layer, 66 second
Wiring layer, 70 third wiring layer, 84, 86 active region, 85, 87 bit line contact hole, 89 wiring, 91 portion.

Claims (11)

[Claims] 1. A method of manufacturing a semiconductor device, comprising forming a side wall on a side wall of a contact hole and then forming a first wiring layer through the contact hole, wherein the first wiring layer is electrically insulated from the first wiring layer. A method for manufacturing a semiconductor device, comprising: forming a sidewall on a sidewall of the contact hole after etching a part or all of an exposed portion of the second wiring layer to be exposed in the contact hole. 2. A step of forming first and second wiring layers on the same substrate, a step of forming an interlayer insulating film so as to cover both of the wiring layers, and a step of forming the interlayer insulating film between the wiring layers. A semiconductor device comprising: a step of forming a contact hole by etching until reaching the substrate; a step of forming a sidewall on a side wall of the contact hole; and a step of forming a third wiring layer in the contact hole. The manufacturing method further includes a step of forming a sidewall after etching a part or all of an exposed portion of the first or second wiring layer exposed in the contact hole when the contact hole is formed. A method for manufacturing a characteristic semiconductor device. 3. A step of forming a first interlayer insulating film on a semiconductor substrate, a step of forming a first wiring layer on the first interlayer insulating film, and a step of covering the first wiring layer. Forming a second interlayer insulating film, forming a contact hole by etching the first and second interlayer insulating films until reaching the semiconductor substrate, and forming a sidewall on the side wall of the contact hole. And a step of forming a second wiring layer in the contact hole, the exposed portion in which the first wiring layer is exposed in the contact hole when the contact hole is formed. After etching some or all of
A method of manufacturing a semiconductor device, comprising the step of forming the sidewall. 4. A step of forming a first interlayer insulating film so as to cover the first wiring layer, and a second step on the first interlayer insulating film.
Forming a second wiring layer, a step of forming a second interlayer insulating film so as to cover the second wiring layer, and the first and second interlayer insulating films reaching the first wiring layer. A method of manufacturing a semiconductor device, comprising: a step of etching the contact hole to form a contact hole; a step of forming a sidewall on the side wall of the contact hole; and a step of forming a third wiring layer in the contact hole. A method of manufacturing a semiconductor device, comprising the step of forming a sidewall after etching a part or all of an exposed portion of the second wiring layer exposed in the contact hole when the contact hole is formed. Method. 5. The method of manufacturing a semiconductor device according to claim 2, wherein after forming a sidewall on the side wall of the contact hole, impurities are implanted into the substrate or the semiconductor substrate to form an impurity layer. Of manufacturing a semiconductor device. 6. A step of forming an element isolation region on a semiconductor substrate, and a gate forming a gate electrode on the active region while traversing the active region of the semiconductor substrate to reach the element isolation region. A step of forming an electrode layer, a step of forming a contact hole by etching the interlayer insulating film and the element isolation region until reaching the semiconductor substrate, a step of forming a sidewall on a side wall of the contact hole, and the contact A step of implanting an impurity into the semiconductor substrate exposed in the contact hole using the sidewall of the hole as a mask to form an impurity layer; and a step of forming a bit line through the contact hole A method for manufacturing a semiconductor device, comprising: 7. The method according to claim 6, further comprising a step of forming a sidewall after etching a part or all of an exposed portion of the gate electrode layer exposed in the contact hole when forming the contact hole. Of manufacturing a semiconductor device of. 8. A first wiring layer formed through a contact hole having a sidewall on a side wall, and the first wiring layer.
And a second wiring layer to be electrically insulated, the second wiring layer has a concave end surface, and the concave end surface is an extension surface of a side wall of the contact hole. A semiconductor device having the above. 9. A first wiring layer and a second wiring layer formed on the same substrate with a predetermined space, and an interlayer insulation formed so as to cover the first and second wiring layers. A membrane,
Via the contact hole formed by opening the interlayer insulating film between the first and second wiring layers until reaching the substrate, the sidewall formed on the side wall of the contact hole, and the contact hole. In a semiconductor device having the above-mentioned first and second wiring layers and a third wiring layer to be insulated, each of the first and second wiring layers has a concave end face, and A semiconductor device comprising an end surface on an extension surface of a side wall of the contact hole. 10. A semiconductor substrate, a device isolation region formed on the semiconductor substrate, and a device which is formed across the active region of the semiconductor substrate and extends to the device isolation region, and a gate electrode on the active region. A gate electrode layer, an interlayer insulating film formed so as to cover the gate electrode layer and the interlayer insulating film, and an opening that penetrates the interlayer insulating film and the element isolation region and reaches the semiconductor substrate. Contact holes, sidewalls formed on the sidewalls of the contact holes, an impurity layer formed by implanting impurities into the semiconductor substrate exposed in the contact holes, and the contact holes. And a bit line. 11. The semiconductor device according to claim 10, wherein the gate electrode layer has a concave end surface, and the concave end surface is provided on an extended surface of a side wall of the contact hole.