JP2009147161A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of effectively suppressing a leakage current near a contact part for electrically connecting a plurality of conductive layers. <P>SOLUTION: The semiconductor device includes: an impurity region formed on the main surface of a semiconductor substrate 1 and provided with a lightly-doped impurity region 5b and a heavily-doped impurity region 5a; a gate electrode 4 formed on the main surface at a position adjacent to the lightly-doped impurity region 5b; sidewall insulating films 12a and 12b formed on one sidewall of the gate electrode 4; low-height sidewall insulating films 12a and 12b extended on the other sidewall of the gate electrode 4 from the top of the lightly-doped impurity region 5b; a silicon nitride film 9a covering the low-height sidewall insulating films 12a and 12b and the lightly-doped impurity region 5b and reaching the other sidewall of the gate electrode 4; and a plug 11 formed so as to cover the silicon nitride film 9a and electrically connected with both of the impurity region and the gate electrode 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more specifically to a semiconductor device having a contact portion extending over a plurality of conductive layers and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, in a semiconductor device such as SRAM (Static Random Access Memory), a shared contact portion, which is an example of a contact portion that is provided so as to straddle a plurality of conductive layers and electrically connects the plurality of conductive layers, is formed. May be.

Semiconductor devices having this shared contact portion are described in, for example, Japanese Patent Application Laid-Open Nos. 2006-100388 and 2001-44294.
JP 2006-1000037 A JP 2001-44294 A

  In the shared contact portion, a wiring layer such as a gate electrode formed on a semiconductor substrate through an insulating film is electrically connected to an impurity region formed at a position adjacent to the wiring layer. There is. In this case, the shared contact portion includes a contact hole extending from the wiring layer to the impurity region, and a conductive layer that is formed in the contact hole and electrically connects the wiring layer and the impurity region.

  When the impurity region has a low concentration region, for example, a sidewall insulating film is formed on the sidewall of the wiring layer so as to cover the low concentration region, and the conductive layer and the low concentration region in the contact portion are formed by the sidewall insulating film. It is conceivable to prevent contact.

  However, for example, if the interlayer insulating film is made thicker to reduce the interlayer capacitance while further miniaturization is being performed, the etching selectivity between the sidewall insulating film and the interlayer insulating film is ensured during the etching for forming the contact hole. It can be difficult. In this case, the sidewall insulating film is also etched when the contact hole is formed, and the height of the sidewall insulating film is lowered. In addition, when a barrier metal is formed in the contact hole, sputter etching may be performed before the barrier metal is formed. This sputter etching also etches the sidewall insulating film, and increases the height of the sidewall insulating film. Will be even lower.

  Thus, when the height of the sidewall insulating film is lowered, it is difficult to reliably cover the low concentration region with the sidewall insulating film, and there is a risk that the conductive layer of the shared contact portion and the low concentration region of the impurity region are in contact with each other. Increases nature. When the conductive layer of the shared contact portion and the low concentration region of the impurity region come into contact with each other, there arises a problem that junction leakage current from the conductive layer of the shared contact portion to the semiconductor substrate is likely to occur.

  The present invention has been made to solve the above-described problems, and a semiconductor device capable of effectively suppressing a leakage current in or near a contact portion that electrically connects a plurality of conductive layers, and its manufacture It aims to provide a method.

  A semiconductor device according to the present invention includes an impurity region formed on a main surface of a semiconductor substrate, having a low concentration impurity region, a high concentration impurity region containing a higher concentration impurity than the low concentration impurity region, and a low concentration impurity. A first conductive layer formed on the main surface adjacent to the region; a first sidewall insulating film formed on one side wall of the first conductive layer; and a first conductive layer from above the low-concentration impurity region The second sidewall insulating film extending on the other sidewall and having a lower height than the first sidewall insulating film, the second sidewall insulating film, and the low-concentration impurity region are covered, and the other sidewall of the first conductive layer is reached. A third sidewall insulating film; and a second conductive layer formed to cover the third sidewall insulating film and electrically connected to both the impurity region and the first conductive layer.

  The semiconductor device further includes an interlayer insulating film formed on the main surface of the semiconductor substrate and having a contact hole reaching the main surface and the first conductive layer, and a fourth side wall insulating film formed on the side wall of the contact hole. It may be provided. In this case, the second conductive layer is formed in the contact hole and on the fourth sidewall insulating film. Moreover, the first and second sidewall insulating films may each be composed of a plurality of insulating films.

  In one aspect, a method for manufacturing a semiconductor device according to the present invention includes the following steps. A first conductive layer is selectively formed on the main surface of the semiconductor substrate via a first insulating film. A low concentration impurity region is formed on the main surface adjacent to the first conductive layer. A first sidewall insulating film is formed on one sidewall of the first conductive layer, and a second sidewall insulating film is formed on the other sidewall of the first conductive layer from the low concentration impurity region. A high concentration impurity region containing an impurity having a higher concentration than the low concentration impurity region is formed on the main surface adjacent to the second sidewall insulating film. An interlayer insulating film is formed on the main surface of the semiconductor substrate so as to cover the first conductive layer, the low concentration impurity region, and the high concentration impurity region. A contact hole reaching the first conductive layer and the high-concentration impurity region is formed in the interlayer insulating film and the height of the second sidewall insulating film is reduced. A second insulating film is formed on the interlayer insulating film so as to cover the second sidewall insulating film. By etching the second insulating film, a third side wall insulating film that covers the second side wall insulating film and the low concentration impurity region and reaches the other side wall of the first conductive layer is formed. A second conductive layer is formed in the contact hole so as to cover the third sidewall insulating film.

  The contact hole forming step may include a step of exposing a partial surface of the other side wall of the first conductive layer by reducing the height of the second side wall insulating film. Further, the step of forming the third sidewall insulating film may include a step of forming the third sidewall insulating film so as to reach a part of the surface of the other side wall of the exposed first conductive layer. .

  The step of forming the third sidewall insulating film may include a step of forming a fourth sidewall insulating film on the sidewall of the contact hole simultaneously with the formation of the third sidewall insulating film. The forming step may include a step of forming the second conductive layer in the contact hole from the third sidewall insulating film to the fourth sidewall insulating film.

  In another aspect, the method for manufacturing a semiconductor device according to the present invention includes the following steps. A first conductive layer is selectively formed on the main surface of the semiconductor substrate via a first insulating film. A low concentration impurity region is formed on the main surface adjacent to the first conductive layer. A first sidewall insulating film is formed on one sidewall of the first conductive layer, and a second sidewall insulating film is formed on the other sidewall of the first conductive layer. A high concentration impurity region containing an impurity having a higher concentration than the low concentration impurity region is formed on the main surface adjacent to the second sidewall insulating film. The first and second sidewall insulating films are removed. A second insulating film is formed on the main surface of the semiconductor substrate so as to cover the first conductive layer, the low concentration impurity region, and the high concentration impurity region. An interlayer insulating film is formed on the second insulating film. A contact hole reaching the first conductive layer and the high concentration impurity region is formed in the interlayer insulating film, and the height of the second insulating film located on the other side wall of the first conductive layer is reduced. A third insulating film is formed on the interlayer insulating film so as to cover the second insulating film on the other side wall of the first conductive layer. By etching the third insulating film, a third sidewall insulating film that covers the second insulating film and the low-concentration impurity region and reaches the other sidewall of the first conductive layer is formed. A second conductive layer is formed in the contact hole so as to cover the third sidewall insulating film.

  According to the present invention, since the further side wall insulating film is formed so as to cover the side wall insulating film on the lower side, the low concentration impurity region can be covered with this further side wall insulating film. Thereby, it is possible to avoid contact between the low-concentration impurity region and the conductive layer in the contact hole, and leakage current resulting from the contact can be effectively suppressed.

Hereinafter, embodiments of the present invention will be described with reference to FIGS.
(Embodiment 1)
FIG. 1 is a partial cross-sectional view of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device according to the first embodiment includes a semiconductor substrate 1 having a main surface, element isolation regions 2 selectively formed on the main surface of the semiconductor substrate 1, and element isolation regions 2 And various elements formed on the main surface of the semiconductor substrate 1.

  As the semiconductor substrate 1, for example, a silicon substrate can be used. Both p-type and n-type silicon substrates can be used. In the first embodiment, an example in which a p-type MOS (Metal Oxide Semiconductor) transistor is formed on the main surface of the semiconductor substrate 1 will be described as an example of an element. However, any other element such as an n-type MOS transistor is formed. May be. When forming a p-type MOS transistor, it is conceivable to use an n-type silicon substrate. However, an n-type region such as an n-well is formed on the p-type silicon substrate, and the p-type MOS transistor is formed on the n-type region. Can also be considered.

  As the element isolation region 2, a trench isolation structure is employed in the example of FIG. More specifically, a trench isolation structure is formed by forming a trench in the main surface of the semiconductor substrate 1 and embedding an insulating film such as a silicon oxide film in the trench. However, any other element isolation structure can be used.

  As shown in FIG. 1, a MOS transistor is formed on the active region surrounded by the element isolation region 2. The MOS transistor includes an impurity region that functions as a source or a drain and a gate electrode. The impurity region is a p-type impurity region in the first embodiment, and a high-concentration impurity region 5a containing a relatively high-concentration p-type impurity and a low-concentration impurity containing a relatively low-concentration p-type impurity. And a region 5b.

The concentration of the p-type impurity contained in the high-concentration impurity region 5a is, for example, about 2 × 10 ¹⁵ cm ⁻³ , and the concentration of the p-type impurity contained in the low-concentration impurity region 5b is, for example, 2 × 10 ¹⁴ cm ^−3. Degree. When the impurity region is an n-type impurity region, the concentration of the n-type impurity contained in high-concentration impurity region 5a is, for example, about 4 × 10 ¹⁵ cm ⁻³ and is contained in low-concentration impurity region 5b. The concentration of the n-type impurity is, for example, about 4 × 10 ¹⁴ cm ⁻³ .

  The gate electrode (first conductive layer) 4 is formed on the channel region sandwiched between the low-concentration impurity regions 5b via the gate insulating film 3. That is, gate electrode 4 is formed on the main surface of semiconductor substrate 1 at a position adjacent to low concentration impurity region 5b. The gate electrode 4 can be formed of a conductive layer such as polysilicon doped with impurities. The gate electrode 4 may be formed of a single conductive layer, but may be formed of a plurality of conductive layers.

  In the first embodiment, a salicide (Self-aligned silicide) structure is adopted, and silicide layers 5 a 1 and 4 a are formed on the surface of the high-concentration impurity region 5 a and the surface of the gate electrode 4. Thus, by forming the silicide layers 5a1 and 4a, the resistance of the high concentration impurity region 5a and the gate electrode 4 can be reduced.

  Side wall insulating films 12a and 12b (first side wall insulating films) are formed on one side wall of the gate electrode 4, and side wall insulating films 12a and 12b (second side walls) are formed on the other side wall of the gate electrode 4. Sidewall insulating film) is formed. The sidewall insulating film 12a can be formed of, for example, TEOS (Tetra Ethyl OrthoSilicate), and the sidewall insulating film 12b can be formed of a silicon nitride film or the like. The sidewall insulating films 12a and 12b are typically made of insulating films made of different materials, but may be made of the same kind of insulating film. Further, in the example of FIG. 1, a sidewall insulating film is formed by combining two insulating films. However, a sidewall insulating film is formed by combining a single layer or three or more insulating films. May be. By configuring the sidewall insulating film with a plurality of insulating films, it is possible to easily form a sidewall insulating film having a certain plane width (width viewed from above). Further, by forming the sidewall insulating film 12a on the gate electrode 4 side with a silicon oxide film, this oxide film can function as a stress buffer film.

  As shown in FIG. 1, the height of the sidewall insulating films 12a and 12b on the other side wall (left side wall in FIG. 1) of the gate electrode 4 is equal to one side wall (right side wall in FIG. 1). ) It is lower than the height of the upper sidewall insulating films 12a and 12b. The side wall insulating films 12a and 12b on the other side wall of the gate electrode 4 extend from the low concentration impurity region 5b to the other side wall of the gate electrode 4, but the surface of the low concentration impurity region 5b. It does not cover the entire surface.

  A sidewall insulating film 9a (third sidewall insulating film) is formed so as to cover the sidewall insulating films 12a and 12b on the other sidewall of the gate electrode 4. The sidewall insulating film 9a can be formed of an insulating film such as a silicon oxide film or a silicon nitride film. As shown in FIG. 1, the sidewall insulating film 9 a is formed to cover the sidewall insulating films 12 a and 12 b and the low concentration impurity region 5 b and reach the other side wall of the gate electrode 4. In the example of FIG. 1, the sidewall insulating film 9a is formed so as to cover almost the entire upper portion of the other side wall of the gate electrode 4 located above the sidewall insulating films 12a and 12b.

  By covering the low concentration impurity region 5b with the sidewall insulating film 9a as described above, it is possible to avoid contact of the conductive layer of the contact portion such as a barrier metal film described later with the low concentration impurity region 5b. Leakage current at or near the contact portion between the conductive layer and the impurity region including the low-concentration impurity region 5b can be effectively suppressed.

  As shown in FIG. 1, a silicon nitride film 6 is formed on the main surface of the semiconductor substrate 1. The silicon nitride film 6 extends from the side wall insulating films 12 a and 12 b on one side wall (the right side wall in FIG. 1) of the gate electrode 4 to the upper surface of the gate electrode 4. On this silicon nitride film 6, an interlayer insulating film 7 made of an insulating film such as a silicon oxide film is formed. The interlayer insulating film 7 may be composed of a single layer insulating film or may be composed of a plurality of insulating films.

  As shown in FIG. 1, the interlayer insulating film 7 has contact holes 8a and 8b. Contact hole 8 a is formed to reach both the main surface (high concentration impurity region 5 a) of semiconductor substrate 1 and gate electrode 4. On the other hand, contact hole 8b is formed to reach the main surface (high concentration impurity region 5a) of semiconductor substrate 1 at a position spaced from gate electrode 4.

  A silicon nitride film 9b (fourth sidewall insulating film) is formed on the sidewall of the contact hole 8a. A plug 11 (second conductive layer) is formed through the barrier metal film 10 in the contact hole 8a and on the silicon nitride films 9a and 9b. Here, by forming the silicon nitride films 9a and 9b, the inner peripheral surface can be slightly inclined from the opening of the contact hole 8a toward the inside, and the formation of the barrier metal film 10 can be performed. It becomes easy. The barrier metal film 10 and the plug 11 are electrically connected to both the impurity region and the gate electrode 4. That is, a shared contact portion is formed by the contact hole 8a and the conductive layer in the contact hole 8a and a plurality of conductive layers to which the conductive layer is electrically connected.

  As the barrier metal film 10, for example, a laminated structure of titanium (Ti) and titanium nitride (TiN) can be adopted, and as the plug 11, a refractory metal layer such as tungsten (W) is adopted. Can do.

  A silicon nitride film 9b is also formed on the side wall of the contact hole 8b. A plug 11 is formed in the contact hole 8b and on the silicon nitride film 9b with a barrier metal film 10 interposed therebetween.

  Next, a method for manufacturing a semiconductor device having the above-described structure will be described with reference to FIGS.

  As shown in FIG. 2, an element isolation region 2 is formed on the main surface of the semiconductor substrate 1. Specifically, the main surface of the semiconductor substrate 1 is etched to form a trench. Thereafter, an insulating film such as a silicon oxide film is deposited on the main surface of the semiconductor substrate 1 by using a CVD (Chemical Vapor Deposition) method or the like, and the thickness is reduced from the upper surface of the insulating film. For example, the thickness is reduced from the upper surface of the insulating film by using a CMP (Chemical Mechanical Polishing) method or the like. Thereby, an insulating film can be embedded in the trench, and a trench isolation structure can be formed. At this time, a trench isolation structure called STI (Shallow Trench Isolation) can be formed by forming the trench relatively shallowly.

  Next, an insulating film such as a silicon oxide film is formed on the main surface of the semiconductor substrate 1 using a technique such as a thermal oxidation method. A polysilicon film having a thickness of about 200 nm is deposited on the insulating film by CVD or the like. The polysilicon film and the insulating film are patterned into a predetermined shape as shown in FIG. Thereby, the gate electrode 4 (first conductive layer) and the gate insulating film 3 (first insulating film) can be formed.

Next, as shown in FIG. 3, p-type impurities such as BF ₂ are implanted into the main surface of the semiconductor substrate 1 using the gate electrode 4 as a mask. When BF ₂ is implanted as a p-type impurity, for example, BF ₂ may be implanted under conditions of about 3.2 KeV and 2 × 10 ¹⁴ cm ⁻³ . Thereby, the low concentration impurity region 5 b can be formed on both sides of the gate electrode 4.

  Next, a lower insulating film such as TEOS is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrode 4 by using a CVD method or the like. On this lower insulating film, an upper insulating film such as a silicon nitride film is formed by CVD or the like. Then, an anisotropic etching process is performed on the upper insulating film and the lower insulating film. Thereby, as shown in FIG. 4, sidewall insulating films 12a and 12b (first and second sidewall insulating films) can be formed on both side walls of the gate electrode 4, respectively.

  In the present embodiment, the width of the sidewall insulating films 12a and 12b as viewed from above is, for example, about 60 nm. Further, in this embodiment, the thickness of the sidewall insulating film 12a is thinner than the thickness of the sidewall insulating film 12b, but it is also possible to make both the thicknesses equal.

Next, p-type impurities such as BF ₂ are implanted into the main surface of the semiconductor substrate 1 using the gate electrode 4 and the sidewall insulating films 12a and 12b as a mask. When BF ₂ is implanted as a p-type impurity, for example, BF ₂ may be implanted under conditions of about 20 KeV and 2 × 10 ¹⁵ cm ⁻³ . Thereby, as shown in FIG. 5, the high concentration impurity region 5a can be formed on both sides of the gate electrode 4 and the low concentration impurity region 5b.

  Next, using a sputtering method or the like, a metal film such as titanium is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrode 4. Then, heat treatment is performed on the metal film under known conditions. Thereby, as shown in FIG. 6, silicide layers 4a and 5a1 are formed in a self-aligned manner on the upper surface of the gate electrode 4 and the surface of the high concentration impurity region 5a. The silicide layers 4a and 5a1 can be omitted.

  Next, as shown in FIG. 7, an insulating film such as a silicon nitride film 6 having a thickness of about 30 nm is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrode 4 by using a CVD method or the like. The silicon nitride film 6 functions as an etching stopper film when the contact holes 8a and 8b are formed later.

  Next, as shown in FIG. 8, an interlayer insulating film 7 is formed using a CVD method or the like. In the first embodiment, a single-layer silicon oxide film having a thickness of about 600 nm is formed as the interlayer insulating film 7, but the interlayer insulating film 7 may be formed of a plurality of silicon oxide films. The interlayer insulating film 7 may be formed of a composite film that is a combination of an insulating film and another insulating film.

  Next, a resist film 13 is applied on the interlayer insulating film 7, and as shown in FIG. 9, the resist film 13 is patterned to a predetermined formation by a known method. The interlayer insulating film 7 is etched using the patterned resist film 13 as a mask. Thereby, contact holes 8a and 8b are formed as shown in FIG. At this time, since the silicon nitride film 6 is formed under the interlayer insulating film 7, the etching can be stopped by the silicon nitride film 6. However, when the interlayer insulating film 7 is formed of a thick silicon oxide film having a thickness of about 600 nm as described above, the etching selectivity between the silicon nitride film 6 and the interlayer insulating film 7 becomes small, and therefore the contact holes 8a and 8b. During the formation, the silicon nitride film 6 is etched to some extent.

  The contact hole 8a is formed so as to overlap a part of the sidewall insulating films 12a and 12b and the gate electrode 4, and the contact hole 8b is located at a position separated from the gate electrode 4 and the sidewall insulating films 12a and 12b. It is formed.

  Next, the silicon nitride film 6 located at the bottom of the contact holes 8a and 8b is etched. As a result, as shown in FIG. 11, the silicide layer 5a1 on the surface of the high concentration impurity region 5a is exposed. At this time, since the silicon nitride film 6 is etched to some extent at the bottom of the contact hole 8a when the contact hole 8a is formed, the side wall insulating films 12a and 12b (second second) formed on the other side wall of the gate electrode 4 are used. The side wall insulating film) is also etched, and a partial surface of the other side wall of the gate electrode 4 is exposed. As a result, the height of the sidewall insulating films 12a and 12b on the other side wall side (left side in FIG. 11) of the gate electrode 4 is equal to the side wall insulating film 12a on one side wall side (right side in FIG. 11) of the gate electrode 4. , 12b (first sidewall insulating film). In some cases, the sidewall insulating films 12a and 12b at the bottom of the contact hole 8a may be completely eliminated. Since the sidewall insulating films 12a and 12b at the bottom of the contact hole 8a are thus etched, in the example of FIG. 11, a partial surface of the low concentration impurity region 5b is exposed. After the etching, the resist film 13 is removed as shown in FIG.

  Next, as shown in FIG. 13, a silicon nitride film 9 (second insulating film) is formed on the interlayer insulating film 7 from the contact holes 8a and 8b by using the CVD method or the like. Although the silicon nitride film 9 having a thickness of about 30 nm is formed in the first embodiment, an insulating film such as a silicon oxide film having an equivalent thickness may be formed instead of the silicon nitride film 9. The thickness of the silicon nitride film 9 is considered to be about 1/4 or less of the minimum diameter (width) of the contact holes 8a and 8b, for example.

  Thereafter, the silicon nitride film 9 is subjected to an anisotropic etching process (etch back process). Thereby, as shown in FIG. 14, the silicon nitride films 9a and 9b can be left in the contact holes 8a and 8b as sidewall insulating films.

  At this time, the silicon nitride film 9a (third sidewall insulating film) covers both the sidewall insulating films 12a and 12b formed on the other sidewall of the gate electrode 4 and the low-concentration impurity region 5b. More specifically, the silicon nitride film 9a reaches from the high concentration impurity region 5a to the other side wall of the gate electrode 4 via the side wall insulating films 12a and 12b on the other side wall side of the gate electrode 4. As a result, both the side wall insulating films 12a and 12b on the other side wall side of the gate electrode 4 and the low concentration impurity region 5b are covered. Silicon nitride film 9b (fourth sidewall insulating film) is formed on the sidewalls of contact holes 8a and 8b.

  Next, as shown in FIG. 15, a barrier metal film 10 is formed on the interlayer insulating film 7 from the contact holes 8a and 8b by using a sputtering method or the like. For example, a stacked structure of titanium (Ti) and titanium nitride (TiN) may be formed. A metal film (second conductive layer) made of tungsten or the like is formed using CVD or the like so as to cover the barrier metal film 10. At this time, a metal film such as tungsten is formed so as to fill the contact holes 8a and 8b. As a result, the metal film is formed from the silicon nitride film 9a to the silicon nitride film 9b.

Thereafter, the metal film and the barrier metal film 10 on the interlayer insulating film 7 are removed using CMP or the like, while the metal film and the barrier metal film 10 are left in the contact holes 8a and 8b. . Thereby, as shown in FIG. 1, the barrier metal film 10 and the plug 11 can be formed in the contact holes 8a and 8b, respectively. Through the above steps, the semiconductor device shown in FIG. 1 is obtained.
(Embodiment 2)
Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 16 is a partial cross-sectional view showing the semiconductor device according to the second embodiment.

  As shown in FIG. 16, in the second embodiment, the element isolation region 2 reaches below the gate electrode 4, and the impurity region is formed only on the other side wall side (left side in FIG. 16) of the gate electrode 4. ing. Further, the contact hole 8b shown in FIG. 1 is not formed. The other configuration is basically the same as that of the first embodiment shown in FIG.

  Also in the case of the second embodiment, as in the case of the first embodiment, it is possible to avoid contact of the conductive layer of the contact portion such as the barrier metal film 10 with the low-concentration impurity region 5b. Alternatively, the leakage current in the vicinity thereof can be effectively suppressed.

  In order to obtain the structure shown in FIG. 16, basically the same manufacturing process as in the first embodiment described above may be performed. However, when the gate electrode 4 is formed, the gate electrode 4 is formed on the element isolation region 2.

  As shown in FIG. 17, after forming the interlayer insulating film 7 through the same process as in the first embodiment, a resist film is applied on the interlayer insulating film 7. After this resist film is patterned into a predetermined shape, a contact hole 8a is formed only on the other side wall side of the gate electrode 4 as shown in FIG. 17 using the patterned resist film as a mask.

Thereafter, silicon nitride films 9a and 9b, barrier metal film 10 and plug 11 are formed by the same method as in the first embodiment. Thereby, the semiconductor device shown in FIG. 16 is obtained.
(Embodiment 3)
Next, Embodiment 3 of the present invention will be described with reference to FIGS. FIG. 18 is a partial cross-sectional view showing the semiconductor device according to the third embodiment.

  As shown in FIG. 18, in the third embodiment, the diameters (widths) of the contact holes 8a and 8b are made larger than those in the above-described embodiments. For example, it is conceivable that the diameters (widths) of the contact holes 8a and 8b are larger than the thicknesses of the silicon nitride films 9 (9a and 9b) by more than twice the thicknesses of the above-described embodiments. Thereby, the contact area between the barrier metal film 10 and the silicide layer 5a1, that is, the contact area between the conductive layer and the impurity region of the contact part can be increased, and the contact resistance in the contact part can be reduced.

  However, for the contact hole 8b which is a contact hole other than the shared contact portion, it is necessary to set the diameter (width) of the contact hole 8b so that the gate electrode 4 and the contact hole 8b do not overlap.

  In the example shown in each drawing of the present embodiment, the contact hole 8b is formed so as to overlap the sidewall insulating film 12b, but it is not always necessary to overlap the both. The other configuration is basically the same as that of the first embodiment shown in FIG.

  Also in the case of the third embodiment, as in the case of each of the above-described embodiments, it can be avoided that the conductive layer of the contact portion such as the barrier metal film 10 is in contact with the low-concentration impurity region 5b. Leakage current at or near the contact portion can be effectively suppressed. In addition to this effect, according to the third embodiment, the contact resistance can also be reduced.

  Next, a manufacturing method of the semiconductor device in the present third embodiment will be described with reference to FIGS.

  As shown in FIG. 19, contact holes 8a and 8b are formed through the same steps as in the first embodiment. At this time, the diameters (widths) of the contact holes 8a and 8b are increased by twice the thickness of the silicon nitride film 9 to be formed later than in the first embodiment.

After the formation of the contact holes 8a and 8b, as shown in FIG. 20, a silicon nitride film 9 is formed using a CVD method or the like. By etching back the silicon nitride film 9, silicon nitride films 9a and 9b, which are sidewall insulating films, are formed in the contact holes 8a and 8b as shown in FIG. Thereafter, the semiconductor device shown in FIG. 18 can be formed through the same steps as those in the above embodiments.
(Embodiment 4)
Next, Embodiment 4 of the present invention will be described with reference to FIGS. FIG. 22 is a partial cross-sectional view showing the semiconductor device according to the fourth embodiment.

  As shown in FIG. 22, in the fourth embodiment, the sidewall insulating films 12a and 12b are removed, and the silicon nitride film 6a is formed directly on the side wall of the gate electrode 4 (first conductive layer). A side wall insulating film is formed by the silicon nitride film 6a. More specifically, on one side wall side (right side in FIG. 22) of the gate electrode 4, the side wall insulating film is formed by forming the silicon nitride film 6 a so as to cover the entire one side wall and reach the upper surface of the gate electrode 4. On the other side wall side (left side in FIG. 22), a side wall insulating film is formed by forming a silicon nitride film 6a so as to cover a part of the surface of the other side wall.

  The side wall insulating film on the other side wall of the gate electrode 4 covers a part of the surface of the low concentration impurity region 5b, but does not cover the entire surface of the low concentration impurity region 5b. Therefore, an insulating film such as a silicon nitride film 9a is formed, and the silicon nitride film 9a covers both the low concentration impurity region 5b and the silicon nitride film 6a. The other configuration is basically the same as that in the first embodiment.

  By covering both the low-concentration impurity region 5b and the silicon nitride film 6a with the silicon nitride film 9a as described above, the conductivity of the contact portion such as the barrier metal film 10 is the same as in the above-described embodiments. It is possible to avoid contact of the layer with the low-concentration impurity region 5b, and it is possible to effectively suppress the leakage current at or near the contact portion.

  Next, a method for manufacturing a semiconductor device according to the fourth embodiment will be described with reference to FIGS.

  As shown in FIG. 23, silicide layers 4a and 5a1 are formed through the same process as in the first embodiment. Thereafter, by performing an etching process or the like, as shown in FIG. 24, the sidewall insulating films 12a and 12b (first and second sidewall insulating films) are removed.

  Next, using a CVD method or the like, as shown in FIG. 25, a silicon nitride film 6a (second insulating film) having a thickness of about 30 nm is formed. On this silicon nitride film 6a, a silicon oxide film having a thickness of about 600 nm is deposited by CVD or the like. Thereby, an interlayer insulating film 7 is formed as shown in FIG.

  Next, a resist film 13 is applied on the interlayer insulating film 7, and as shown in FIG. 27, the resist film 13 is patterned into a predetermined formation by a known method. The interlayer insulating film 7 is etched using the patterned resist film 13 as a mask. Thereby, as shown in FIG. 28, contact holes 8a and 8b are formed. At this time, since the silicon nitride film 6a is formed under the interlayer insulating film 7, the etching can be stopped by the silicon nitride film 6a. However, in the present embodiment as well, as in the case of the first embodiment, since the interlayer insulating film 7 is composed of a thick silicon oxide film, the silicon nitride film 6a is etched relatively much. .

  Next, the silicon nitride film 6a located at the bottom of the contact holes 8a and 8b is etched. As a result, as shown in FIG. 29, the silicide layer 5a1 on the surface of the high concentration impurity region 5a is exposed. At this time, since the silicon nitride film 6a is etched to some extent at the bottom of the contact hole 8a when the contact hole 8a is formed, the silicon nitride film 6a is further etched on the other side wall of the gate electrode 4. The amount of silicon nitride film 6a (sidewall insulating film: second side wall insulating film) remaining on the other side wall is reduced.

  As a result, the height of the silicon nitride film 6a remaining on the other side wall of the gate electrode 4 is lowered, a part of the surface of the other side wall of the gate electrode 4 is exposed, and one side wall side of the gate electrode 4 (FIG. 29). The right side) of the silicon nitride film 6a (side wall insulating film: first side wall insulating film). In some cases, the sidewall insulating film at the bottom of the contact hole 8a may be completely eliminated. Since the side wall insulating film at the bottom of the contact hole 8a is thus etched, a part of the surface of the low concentration impurity region 5b is exposed also in the example of FIG. After the etching, the resist film 13 is removed as shown in FIG.

  Next, as shown in FIG. 31, a silicon nitride film 9 (third insulating film) is formed on the interlayer insulating film 7 from the contact holes 8a and 8b by using the CVD method or the like. Although the silicon nitride film 9 having a thickness of about 30 nm is formed in the fourth embodiment, an insulating film such as a silicon oxide film having an equivalent thickness may be formed instead of the silicon nitride film 9. As in the case of the first embodiment, the thickness of the silicon nitride film 9 is considered to be about 1/4 or less of the minimum diameter of the contact holes 8a and 8b.

  Thereafter, the silicon nitride film 9 is subjected to an anisotropic etching process (etch back process). Thereby, as shown in FIG. 32, silicon nitride films 9a and 9b can be left in contact holes 8a and 8b as sidewall insulating films.

  At this time, the silicon nitride film 9a (third sidewall insulating film) covers both the sidewall insulating film formed on the other sidewall of the gate electrode 4 and the low-concentration impurity region 5b. More specifically, the silicon nitride film 9a is formed so as to reach the other side wall of the gate electrode 4 from above the high concentration impurity region 5a via the side wall insulating film on the other side wall side of the gate electrode 4. As a result, both the side wall insulating film on the other side wall side of the gate electrode 4 and the low concentration impurity region 5b are covered. Silicon nitride film 9b (fourth sidewall insulating film) is formed on the sidewalls of contact holes 8a and 8b.

Thereafter, barrier metal film 10 and plug 11 (second conductive layer) are respectively formed in contact holes 8a and 8b by the same method as in the first embodiment. The semiconductor device shown in FIG. 22 is obtained through the above steps.
(Embodiment 5)
Next, a fifth embodiment of the present invention will be described. In the fifth embodiment, a specific device example to which the above-described structure can be applied and a modification thereof will be described.

  In each of the above-described embodiments, the case where the structure of the present invention is applied to the shared contact portion reaching the impurity region and the gate electrode of the pMOS transistor is exemplified. However, such a contact structure can be adopted in, for example, an SRAM.

  However, the structure of the present invention can be applied to any structure that electrically connects the low-concentration impurity region and another conductive layer through a common contact portion. Specifically, the structure of the present invention can also be applied to a shared contact portion reaching the impurity region and gate electrode of an nMOS transistor. The structure of the present invention can also be applied to a common contact portion that electrically connects an impurity region including a low-concentration impurity region and a wiring layer provided adjacent to the impurity region.

  Although the embodiments of the present invention have been described above, it is also planned from the beginning to combine the configurations of the embodiments as appropriate. The scope of the present invention is not limited to the above-described embodiment. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a fragmentary sectional view of the semiconductor device in Embodiment 1 of this invention. It is a figure which shows the 1st process in the manufacturing process of the semiconductor device shown in FIG. It is a figure which shows the 2nd process in the manufacturing process of the semiconductor device shown in FIG. It is a figure which shows the 3rd process in the manufacturing process of the semiconductor device shown in FIG. It is a figure which shows the 4th process in the manufacturing process of the semiconductor device shown in FIG. FIG. 10 is a diagram showing a fifth step in the manufacturing process of the semiconductor device shown in FIG. 1. It is a figure which shows the 6th process in the manufacturing process of the semiconductor device shown in FIG. It is a figure which shows the 7th process in the manufacturing process of the semiconductor device shown in FIG. It is a figure which shows the 8th process in the manufacturing process of the semiconductor device shown in FIG. It is a figure which shows the 9th process in the manufacturing process of the semiconductor device shown in FIG. It is a figure which shows the 10th process in the manufacturing process of the semiconductor device shown in FIG. It is a figure which shows the 11th process in the manufacturing process of the semiconductor device shown in FIG. It is a figure which shows the 12th process in the manufacturing process of the semiconductor device shown in FIG. It is a figure which shows the 13th process in the manufacturing process of the semiconductor device shown in FIG. It is a figure which shows the 14th process in the manufacturing process of the semiconductor device shown in FIG. It is a fragmentary sectional view of the semiconductor device in Embodiment 2 of this invention. FIG. 17 is a diagram showing a characteristic process in the manufacturing process of the semiconductor device shown in FIG. 16. It is a fragmentary sectional view of the semiconductor device in Embodiment 3 of this invention. FIG. 19 is a diagram showing a characteristic first step in the manufacturing process of the semiconductor device shown in FIG. 18. FIG. 19 is a diagram showing a characteristic second step in the manufacturing process of the semiconductor device shown in FIG. 18. FIG. 19 is a diagram showing a characteristic third step in the manufacturing process of the semiconductor device shown in FIG. 18. It is a fragmentary sectional view of the semiconductor device in Embodiment 4 of this invention. FIG. 23 is a diagram showing a characteristic first step in the manufacturing process of the semiconductor device shown in FIG. 22. FIG. 23 is a diagram showing a characteristic second step in the manufacturing process of the semiconductor device shown in FIG. 22. FIG. 23 is a diagram showing a characteristic third step in the manufacturing process of the semiconductor device shown in FIG. 22. FIG. 23 is a diagram showing a characteristic fourth step in the manufacturing process of the semiconductor device shown in FIG. 22. FIG. 23 is a diagram showing a characteristic fifth step in the manufacturing process of the semiconductor device shown in FIG. 22; FIG. 23 is a diagram showing a characteristic sixth step in the manufacturing process of the semiconductor device shown in FIG. 22. FIG. 23 is a diagram showing a characteristic seventh step in the manufacturing process of the semiconductor device shown in FIG. 22. FIG. 23 is a diagram showing a characteristic eighth step in the manufacturing process of the semiconductor device shown in FIG. 22. FIG. 23 is a diagram showing a characteristic ninth step in the manufacturing process of the semiconductor device shown in FIG. 22; FIG. 23 is a diagram showing a characteristic tenth step in the manufacturing process of the semiconductor device shown in FIG. 22.

Explanation of symbols

  1 semiconductor substrate, 2 element isolation region, 3 gate insulating film, 4 gate electrode, 4a, 5a1 silicide layer, 5a high concentration impurity region, 5b low concentration impurity region, 6, 6a, 9, 9a, 9b silicon nitride film, 7 Interlayer insulating film, 8a, 8b contact hole, 10 barrier metal film, 11 plug, 12a, 12b side wall insulating film, 13 resist film.

Claims (7)

An impurity region formed on a main surface of the semiconductor substrate and having a low-concentration impurity region and a high-concentration impurity region containing a higher-concentration impurity than the low-concentration impurity region;
A first conductive layer formed on the main surface at a position adjacent to the low-concentration impurity region;
A first sidewall insulating film formed on one sidewall of the first conductive layer;
A second sidewall insulating film extending from above the low-concentration impurity region onto the other sidewall of the first conductive layer and having a height lower than that of the first sidewall insulating film;
A third sidewall insulating film that covers the second sidewall insulating film and the low-concentration impurity region and reaches the other sidewall of the first conductive layer;
A second conductive layer formed to cover the third sidewall insulating film and electrically connected to both the impurity region and the first conductive layer;
A semiconductor device comprising: An interlayer insulating film formed on a main surface of the semiconductor substrate and having a contact hole reaching the main surface and the first conductive layer;
A fourth sidewall insulating film formed on the sidewall of the contact hole,
The semiconductor device according to claim 1, wherein the second conductive layer is formed in the contact hole and on the fourth sidewall insulating film.   3. The semiconductor device according to claim 1, wherein each of the first and second sidewall insulating films includes a plurality of insulating films. Selectively forming a first conductive layer on a main surface of a semiconductor substrate via a first insulating film;
Forming a low-concentration impurity region on the main surface at a position adjacent to the first conductive layer;
Forming a first sidewall insulating film on one sidewall of the first conductive layer, and forming a second sidewall insulating film on the other sidewall of the first conductive layer from the low-concentration impurity region;
Forming a high concentration impurity region containing a higher concentration impurity than the low concentration impurity region on the main surface adjacent to the second sidewall insulating film;
Forming an interlayer insulating film on a main surface of the semiconductor substrate so as to cover the first conductive layer, the low-concentration impurity region, and the high-concentration impurity region;
Forming a contact hole reaching the first conductive layer and the high concentration impurity region in the interlayer insulating film and reducing a height of the second sidewall insulating film;
Forming a second insulating film on the interlayer insulating film so as to cover the second sidewall insulating film;
Etching the second insulating film to form a third sidewall insulating film that covers the second sidewall insulating film and the low-concentration impurity region and reaches the other sidewall of the first conductive layer;
Forming a second conductive layer in the contact hole so as to cover the third sidewall insulating film;
A method for manufacturing a semiconductor device comprising: The step of forming the contact hole includes a step of exposing a partial surface of the other side wall of the first conductive layer by reducing the height of the second side wall insulating film,
5. The step of forming the third sidewall insulating film includes a step of forming the third sidewall insulating film so as to reach a part of a surface of the other sidewall of the exposed first conductive layer. Semiconductor device manufacturing method. Forming the third sidewall insulating film includes forming a fourth sidewall insulating film on the sidewall of the contact hole simultaneously with the formation of the third sidewall insulating film;
6. The step of forming the second conductive layer includes a step of forming the second conductive layer in the contact hole from the third sidewall insulating film to the fourth sidewall insulating film. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. Selectively forming a first conductive layer on a main surface of a semiconductor substrate via a first insulating film;
Forming a low-concentration impurity region on the main surface at a position adjacent to the first conductive layer;
Forming a first sidewall insulating film on one sidewall of the first conductive layer, and forming a second sidewall insulating film on the other sidewall of the first conductive layer;
Forming a high concentration impurity region containing a higher concentration impurity than the low concentration impurity region on the main surface adjacent to the second sidewall insulating film;
Removing the first and second sidewall insulating films;
Forming a second insulating film on the main surface of the semiconductor substrate so as to cover the first conductive layer, the low-concentration impurity region, and the high-concentration impurity region;
Forming an interlayer insulating film on the second insulating film;
Forming a contact hole reaching the first conductive layer and the high-concentration impurity region in the interlayer insulating film, and reducing a height of the second insulating film located on the other side wall of the first conductive layer; When,
Forming a third insulating film on the interlayer insulating film so as to cover the second insulating film on the other side wall of the first conductive layer;
Etching the third insulating film to form a third sidewall insulating film that covers the second insulating film and the low-concentration impurity region and reaches the other sidewall of the first conductive layer;
Forming a second conductive layer in the contact hole so as to cover the third sidewall insulating film;
A method for manufacturing a semiconductor device comprising:

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