JP2007123850A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with large on-current of a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). <P>SOLUTION: The semiconductor device includes a semiconductor substrate 1. A trench 2 defining an element region is formed in a surface of the semiconductor substrate. The MOSFET includes a gate insulating film 11 formed on the semiconductor substrate, a gate electrode 12 formed on the gate insulating film, and a source/drain diffusion layer 21 sandwiching a channel region below the gate electrode. A stress film 31 is continuously formed over the gate electrode and source/drain diffusion layer and in the trench and applies a tensile stress or compressive stress to the semiconductor substrate. An insulating film 41 buries the trench via the stress film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, for example, a structure of an element isolation insulating film of a semiconductor device.

  As an element isolation insulating film that partitions an element region (active region) of a semiconductor device, an STI (Shallow Trench Isolation) structure is known. The element isolation insulating film having the STI structure is formed by embedding an insulating film in a trench formed on the surface of the semiconductor substrate. A semiconductor element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed in the active region.

  In addition, a technique for increasing the on-state current of a MOSFET (hereinafter simply referred to as a transistor) is known using stress applied to a semiconductor substrate by an insulating film constituting an element isolation insulating film. An insulating film suitable for obtaining an on-current increasing effect (hereinafter referred to as an on-current increasing effect) of the transistor due to this stress is formed on the side surface in the trench, and the remaining portion of the trench has insulation characteristics such as good embedding property. Embedded with membrane.

  A method for manufacturing a semiconductor device having an element isolation insulating film capable of realizing an on-current increasing effect will be described with reference to FIGS. First, as shown in FIG. 14, a silicon nitride film 102 is formed on a semiconductor substrate 101, and a trench 103 is formed on the surface of the silicon nitride film 102 and the semiconductor substrate 101.

  Next, after a silicon nitride film 104 is formed on the inner surface of the trench 103, the trench 103 is filled with an insulating film 105 to an appropriate depth. Next, the silicon nitride film 104 exposed in the trench 103 is removed. Next, an insulating film 106 is formed in the trench 103. Next, the silicon nitride film 102 is removed to form an element isolation insulating film.

  Thereafter, as shown in FIG. 15, a transistor having a gate insulating film 111, a gate electrode 112, and a source / drain diffusion layer 113 is formed. Next, as shown in FIG. 16, an etching stopper film 114 is formed on the entire surface of the structure obtained through the steps so far. Thereafter, formation of an interlayer insulating film, wiring layers, contact plugs, and the like are formed. The etching stopper film 114 has a function as a stopper when the contact hole is formed in the interlayer insulating film.

  When the stress of the silicon nitride film 104 acts on the channel region of the transistor, the on-state current of the transistor is increased. The closer the distance between the silicon nitride film 104 and the channel region, the greater the effect of increasing the on-current.

Japanese Patent Laid-Open No. 2003-158241 discloses that a silicon nitride film is provided on the side surface of a trench in contact with the NMOS active region, and a silicon nitride film is provided only on the side surface of the trench in contact with the PMOS active region in a direction perpendicular to the channel direction. Discloses a technique for increasing the on-current of both NMOS and PMOS.
JP 2003-158241 A

  The present invention intends to provide a semiconductor device having a large on-current of a MOSFET and a method for manufacturing the same.

  A semiconductor device according to a first aspect of the present invention includes a semiconductor substrate, a trench formed on a surface of the semiconductor substrate and defining an element region, a gate insulating film provided on the semiconductor substrate, and the gate insulating film A MOSFET including a gate electrode provided thereon, and a source / drain diffusion layer sandwiching a channel region below the gate electrode; and the gate electrode, the source / drain diffusion layer, and the trench. And a stress film that applies tensile stress or compressive stress to the semiconductor substrate, and an insulating film that embeds the trench through the stress film.

  A method of manufacturing a semiconductor device according to a second aspect of the present invention includes a step of forming a trench for partitioning an element region on a surface of a semiconductor substrate, a gate insulating film on the surface of the semiconductor substrate, and a gate insulating film formed on the surface of the semiconductor substrate. Forming a MOSFET including a gate electrode formed on the gate electrode and a source / drain diffusion layer sandwiching a channel region below the gate electrode; and continuous on the gate electrode, the source / drain diffusion layer, and in the trench And a step of forming a stress film that applies a tensile stress or a compressive stress to the semiconductor substrate, and a step of filling the trench with a first insulating film through the stress film.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device with large ON current of MOSFET and its manufacturing method can be provided.

  In the course of developing the present invention, the present inventors have studied a method for effectively executing the on-current increasing effect by the element isolation insulating film. As a result, the present inventors have obtained knowledge as described below.

  As described in the background section, the silicon nitride film 104 is not formed on the side surface of the trench 103 near the surface of the semiconductor substrate 101. The upper surface of the silicon nitride film 104 is covered with an insulating film 106. This is because when the silicon nitride film 104 is exposed in the trench 103 in the step of removing the silicon nitride film 102, the silicon nitride film 104 is significantly larger than the surface of the semiconductor substrate when the silicon nitride film 102 is removed. This is because it is etched back to a deep position.

  Thus, the silicon nitride film 104 has to be removed in the vicinity of the surface of the semiconductor substrate 101 in the trench 103 for reasons of the manufacturing process. As a result, the silicon nitride film 104 is not formed in the portion closest to the channel region that exhibits the largest on-current increasing effect. Only the silicon nitride film 104 near the bottom of the trench 103 is less effective in increasing the on-current than when the silicon nitride film 104 is also formed near the surface of the semiconductor substrate 101 in the trench 103.

  In addition, recently, by controlling the stress of the etching stopper film 114, the etching stopper film 114 has the same effect of increasing the on-current as the silicon nitride film 104. However, in the steps shown in FIGS. 14 to 16, a very large number of steps are required to form the silicon nitride film 104 and the etching stopper film 114. For this reason, a process for realizing a higher on-current increasing effect and efficiently forming a stress film for increasing the on-current is desired.

  Hereinafter, an embodiment of the present invention configured based on such knowledge will be described with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

  FIG. 1 is a plan view showing a main part of a semiconductor device according to an embodiment of the present invention. FIGS. 2 and 3 are cross-sectional views taken along lines II-II and III-III in FIG. is there. As shown in FIGS. 1, 2, and 3, a trench 2 constituting an element isolation region is formed on the surface of a semiconductor substrate 1 made of, for example, silicon. The element isolation region defines an element region (active region) 4. The trench 2 is formed in a region other than the active region 4 in the surface of the semiconductor substrate 1. On the side and bottom surfaces of the trench 2, an insulating film 3 made of, for example, a silicon oxide film is formed.

  A MOSFET is formed in the element region 4. The MOSFET includes at least a gate insulating film 11, a gate electrode 12, and a source / drain diffusion layer 21.

  The gate insulating film 11 is provided on the surface of the semiconductor substrate 1 and is made of, for example, a silicon oxide film. The gate electrode 12 is provided on the gate insulating film 11 and is made of, for example, polysilicon made conductive by introducing impurities.

  The gate electrode 12 reaches a position beyond the element region 4 at the end along the vertical direction in FIG. Under the gate electrode in the element isolation region, the trench 2 is not formed, but the insulating film 3 is buried. The gate electrode 12 is located on the gate insulating film 11 in the element region 4 and on the insulating film 3 in the element isolation region.

  A silicide 13 is formed on the upper surface of the gate electrode 12.

  On the side surfaces of the gate insulating film 11 and the gate electrode 12, an insulating film 14 made of, for example, a silicon nitride film is provided. A spacer 15 made of, for example, a silicon nitride film is provided on the side wall of the insulating film 14.

  The source / drain diffusion layer 21 is formed on the surface of the semiconductor substrate 1 in the element region 4 so as to sandwich the channel region below the gate electrode 12. The source / drain diffusion layer 21 includes a low concentration portion (Lightly Doped Drain) 21a and a high concentration portion 21b. The low concentration portion 21 a is located below the insulating film 14 and the spacer 15 and is formed in a shallow region near the surface of the semiconductor substrate 1. The high concentration portion 21b extends to a position deeper than the low concentration portion 21a with the low concentration portion 21a interposed therebetween. Silicide 22 is formed on the surface of the source / drain diffusion layer 21.

  A stress film 31 is provided on the side surface of the spacer 15, the upper surface of the gate electrode 12, the surface of the semiconductor substrate 1 in the element region 4, the angle formed by the trench 2 and the semiconductor substrate 1, and the insulating film 3 in the trench 2. Yes. The stress film 31 extends over the entire surface of the insulating film 3 formed in the trench 2. For this reason, the stress film 31 can apply a large stress to the semiconductor substrate 1. Further, a stress film 31 is also formed on a portion of the surface of the trench 2 closest to the channel region of the MOSFET, that is, in the vicinity of the surface of the semiconductor substrate 1. Therefore, the effect of increasing the on-current of the MOSFET due to the stress film 31 can be utilized to the maximum.

  The stress film 31 has a material and a composition that increase the on-current of the MOSFET due to the stress applied to the semiconductor substrate 1 by the stress film 31. As the stress film 31, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an aluminum oxide film, an aluminum nitride film, a tantalum oxide film, a titanium oxide film, or the like can be used.

  Further, the stress film 31 has a characteristic according to the conductivity type of the channel of the MOSFET that increases the on-current. More specifically, a stress film 31 having a tensile stress is used for an n-channel MOSFET. A stress film 31 having a compressive stress is used for a MOSFET whose channel is p-type. In order to increase both the n-type and p-type on-currents with one material, the composition of this material is appropriately set. Of course, different materials can be used for each conductivity type.

  Furthermore, as shown in FIG. 4, the stress film 31 may have a laminated structure including a first layer 31a and a second layer 31b. FIG. 4 illustrates the case of two layers, but it is of course possible to have three or more layers. When the stress film 31 has a laminated structure, the above-described materials can be used for each layer. It is also possible to obtain an effect of simultaneously increasing the on-currents of both n-type and p-type MOSFETs by stacking a layer having tensile stress and a layer having compressive stress.

  The stress film 31 also has a function as an etching stopper at least on the surfaces of the semiconductor substrate 1 and the gate electrode 12.

  Over the entire surface of the stress film 31, an interlayer insulating film 41 made of, for example, a silicon oxide film is provided. The interlayer insulating film 41 has a function as an element isolation insulating film in the trench 2 by being embedded in the trench 2. On the entire surface of the interlayer insulating film 41, interlayer insulating films 42 and 43 made of, for example, a silicon oxide film are sequentially provided.

  Contact plugs 51 reaching the silicides 13 and 22 are provided in the interlayer insulating films 42 and 41. The contact plug 51 is made of a conductive material embedded in the contact hole via a barrier metal 52 provided on the inner surface of the contact hole.

  A wiring layer 61 whose bottom surface is in contact with the contact plug 51 is provided in the interlayer insulating film 43. The wiring layer 61 is made of a conductive material embedded in the wiring groove via a barrier metal 62 provided on the inner surface of the wiring groove.

  Next, a method for manufacturing the semiconductor device of FIGS. 1 to 3 will be described with reference to FIGS. 5 to 12 are cross-sectional views sequentially showing a part of the manufacturing process of the semiconductor device of FIGS. 1 to 3, and show the same cross section as FIG. As shown in FIG. 5, an insulating film 71 having a thickness of about 150 nm is formed on the semiconductor substrate 1 by, for example, an LPCVD (Low Pressure Chemical Vapor Deposition) method. The insulating film 71 has a function such as a mask for forming a trench for partitioning the element region, and for example, a silicon nitride film can be used. Next, a resist film (not shown) is applied on the entire surface of the insulating film 71. Next, a pattern having an opening above the region where the trench 2 is to be formed is formed in the resist film by a lithography process. The element region 4 is partitioned by the trench 2.

  Next, using the resist film as a mask, the insulating film 71 is etched by anisotropic etching such as RIE (Reactive Ion Etching). Subsequently, the trench 2 is formed by etching the semiconductor substrate 1 to about 300 nm by RIE or the like.

  Next, an insulating film 3 made of, for example, a silicon oxide film is deposited on the entire surface of the structure obtained through the steps up to here by, eg, CVD. Next, the insulating film is planarized by a CMP (Chemical Mechanical Polishing) method using the insulating film 71 as a stopper.

  Next, as shown in FIG. 6, the upper surface of the insulating film 3 is etched to a position slightly higher than the surface of the semiconductor substrate 1, more specifically, about 100 nm from the state of FIG. 5. Next, the insulating film 71 is removed by wet etching or the like. As a result, an element isolation region is formed. Next, p-type and n-type wells (not shown) are formed by ion implantation and a thermal process.

  Next, as shown in FIG. 7, a gate insulating film 11 and a gate electrode 12 are formed. That is, the gate insulating film 11 is formed by oxidizing the surface of the semiconductor substrate 1 by, for example, a thermal oxidation method. Next, a conductive polysilicon film having a thickness of about 150 nm is formed on at least the gate insulating film and the insulating film 3 by, for example, LPCVD.

  Next, the polysilicon film is patterned into the shape of the gate electrode 12 by a lithography process and anisotropic etching such as RIE. As shown in FIG. 1, the polysilicon film slightly reaches the element isolation region from the element region, and is located on the insulating film 3 in this portion.

  Next, the portion of the gate insulating film 11 that is not covered with the gate electrode 12 is removed by, for example, wet etching. Next, the low concentration portion 21a of the source / drain diffusion layer 21 is formed by ion implantation using the gate electrode 12 as a mask and a thermal process at about 800 ° C.

  Next, as shown in FIG. 8, the insulating film 14 and the insulating film to be the spacer 15 are sequentially deposited on the entire surface of the structure obtained through the steps so far, for example, by LPCVD. Next, the insulating film 14 and the spacer 15 are formed by etching back these insulating films. Next, the high concentration portion 21b of the source / drain diffusion layer 21 is formed by ion implantation using the gate electrode 12, the insulating film 14, and the spacer 15 as a mask, and a thermal process.

  Next, as shown in FIG. 9, a metal film (not shown) serving as a silicide material is formed on the entire surface of the structure obtained through the steps so far. Next, by performing a thermal process, silicides 13 and 22 are formed on the gate electrode 12 and on the surface of the semiconductor substrate 1 (the surface of the source / drain diffusion layer 21), respectively. Next, the metal film that did not contribute to silicidation is removed.

  Next, a resist film 72 is formed on the entire surface of the structure obtained through the steps so far by coating. Next, a pattern having an opening 73 above the trench 2 (above the insulating film 3) is formed in the resist film 72 by a lithography process.

  Next, as shown in FIG. 10, the insulating film 3 is etched back by, for example, the RIE method using the resist film as a mask. The opening 73 of the resist film 72 has a shape slightly smaller than the planar shape of the trench 2 in consideration of the occurrence of a positional shift of the resist film pattern. Therefore, the insulating film 3 remains on the side surface of the trench 2 as a result of etching.

  As the distance between the stress film 31 and the semiconductor substrate 1 on the side surface of the trench 2 is smaller, the stress applied to the semiconductor substrate 1 by the stress film 31 becomes larger. From the viewpoint of obtaining a larger stress, the insulation on the side surface of the trench 2 The film 3 is preferably thin. However, when the insulating film 3 is completely removed, the stress film 31 comes into contact with the surface of the trench 2, that is, silicon. As a result, an interface state is generated, and the performance of the semiconductor device is deteriorated, which is not preferable. Therefore, it is preferable that the trench 2 is covered with the thin insulating film 3.

  The insulating film 3 is etched back so that the insulating film 3 remains slightly on the bottom surface of the trench 2. This is because the surface of the semiconductor substrate 1 on the bottom surface of the trench 2 may be roughened if the insulating film 3 is to be completely removed. That is, depending on the portion, not only the removal of the insulating film 3 but also the silicon on the bottom surface of the trench 2 may be etched. As a result, if a well is formed in this portion, the characteristics of the well are disturbed, the characteristics of the semiconductor device change, and in the worst case, the semiconductor device does not function.

  On the other hand, if the insulating film 3 on the bottom surface of the trench 2 is too thick, the area of the stress film 31 on the side surface of the trench 2 becomes small. Then, the effect of increasing the on-current of the MOSFET due to the stress film 31 is reduced. Therefore, it is desirable that the insulating film 3 on the bottom surface of the trench 2 is thin from the viewpoint of obtaining a larger stress. The insulating film 3 on the bottom surface of the trench 2 is desirably located at a position deeper than at least the position of the bottom surface (junction depth) of the source / drain diffusion layer 21.

  Next, as shown in FIG. 11, a stress film 31 is deposited on the entire surface of the structure obtained by the steps so far, for example, by LPCVD. The thickness of the stress film 31 is, for example, 30 nm. As a result, the stress film 31 is formed on the gate electrode 12, the spacer 15, the surface of the semiconductor substrate 1, and the insulating film 3. The stress film 31 is originally provided on the gate electrode 12 and the surface of the semiconductor substrate 1 as a stopper film against etching when forming a contact hole in a later process. By forming the film used for such an application even on the inner surface of the trench 2, the stress film 31 is efficiently formed in the trench 2 while utilizing the manufacturing process of the conventional semiconductor device. be able to.

  More specifically, in the method shown in FIGS. 14 to 16, the stress film 104 on the side surface of the trench 103 and the etching stopper film 114 having a function of applying stress are formed in separate steps. On the other hand, according to this embodiment, it is created in one process. For this reason, a manufacturing process can be made efficient.

  As a result of the process of FIG. 11, the stress film 31 is formed on the entire surface on the side surface of the trench 2 including the vicinity of the surface of the semiconductor substrate 1 (the corner of the trench 2) that contributes most to the on-current increasing effect of the MOSFET.

  Next, as shown in FIG. 12, an interlayer insulating film 41 having a thickness of about 400 nm is deposited on the entire surface of the structure obtained through the steps so far, for example, by LPCVD. At this time, the trench 2 is filled with the interlayer insulating film 41. Next, the interlayer insulating film 41 is planarized by, for example, a CMP method.

  Next, an interlayer insulating film 42 having a thickness of about 200 nm is deposited on the entire surface of the interlayer insulating film 41 by, eg, plasma CVD.

  Next, as shown in FIG. 2, contact holes reaching the silicides 13 and 22 are formed in the interlayer insulating films 41 and 42 by a lithography process and anisotropic etching such as RIE. Next, a barrier metal 52 having a thickness of about 5 nm is formed on the inner surface of the contact hole by sputtering, for example. Next, the contact plug 51 is formed by filling the contact hole with a conductive material such as tungsten by, for example, thermal CVD.

  Next, an interlayer insulating film 43 is formed on the entire surface of the structure obtained through the above steps. Next, a barrier metal 62 and a wiring layer 61 are formed in the interlayer insulating film 43 by a lithography process, etching, a CVD method, or the like. Thereafter, if desired, further interlayer insulating films, via plugs, wiring layers, pads, and the like are formed by a known method.

  In the above description, the step of positively removing the insulating film 3 in the trench 2 is illustrated. However, it is not limited to this. Specifically, it can be configured as shown in FIG. FIG. 13 will be described below.

  After the trench 2 is filled with the insulating film 3 in the process of FIG. 5, the ratio of the etching rate between the film removed in a certain etching process and the insulating film 3 may not be sufficiently large. In such an etching process, the upper end of the insulating film 3 is slightly etched back. By overlapping the etching processes under such conditions, the upper end of the insulating film 3 is positioned lower than the surface of the semiconductor substrate 1 as shown in FIG. In this state, the stress film 31 is formed on the upper surface of the thick insulating film 3 in the trench 2 as shown in FIG.

  Also in the case of FIG. 13, the stress film 31 is formed on the entire surface on the side surface of the trench 2 including the vicinity of the surface of the semiconductor substrate 1 that contributes most to the on-current increasing effect of the MOSFET. In FIG. 13, the insulating film 2 remains on the side surface of the trench 2 near the surface of the semiconductor substrate 1. This is an oxide film that is naturally formed when the semiconductor device being processed is taken out of the processing device.

  According to the semiconductor device of one embodiment of the present invention, the film formed on the gate electrode 12 and the surface of the semiconductor substrate 1 as the etching stopper film extends to the inner surface of the trench 2 as the element isolation region. For this reason, the stress film 31 is formed on the entire surface on the side surface of the trench 2 including the vicinity of the surface of the semiconductor substrate 1 that contributes most to the on-current increasing effect of the MOSFET. Therefore, the on-current increasing effect can be utilized to the maximum by the stress film 31 in the trench 2.

  14 to 16, the stress film 31 is not formed when the insulating film (for example, silicon nitride film) 71 used for forming the trench for the element region is removed. Therefore, even if the insulating film 71 and the stress film 31 are made of similar materials and are removed together under certain etching conditions, the silicon nitride film 102 is unavoidable in the steps of FIGS. It is not necessary to cover the silicon nitride film 104 at that time. Therefore, the stress film 31 can be formed on the entire side surface of the trench 2 as the element isolation region.

  Further, the stress film 31 extending into the trench 2 is realized by diverting the etching stopper film. That is, a film disposed on the surface of the semiconductor substrate as an etching stopper film is also formed on the inner surface of the trench 2 as an element isolation region in the film forming process. For this reason, the stress film also having a function as an etching stopper on the surface of the semiconductor substrate 1 and the stress film on the inner surface of the trench 2 which have been formed in separate steps can be formed in one step. As described above, the stress film 31 can be efficiently formed on the portion that contributes to the effect of increasing the on-current by using the originally required film forming process.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

The top view which shows the principal part of the semiconductor device which concerns on one Embodiment of this invention. Sectional drawing of FIG. Sectional drawing of FIG. Sectional drawing which shows the principal part of the semiconductor device which concerns on other embodiment of this invention. FIG. 3 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device of FIG. 2. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. FIG. 11 is a cross-sectional view showing a step following FIG. 10. Sectional drawing which shows the process following FIG. Sectional drawing which shows the principal part of the semiconductor device which concerns on other embodiment of this invention. Sectional drawing which shows a part of manufacturing process of the conventional semiconductor device. The figure which shows the process of following FIG. The figure which shows the process of following FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Trench, 3 ... Insulating film, 11 ... Gate insulating film, 12 ... Gate electrode, 13 ... Silicide, 14 ... Insulating film, 15 ... Spacer, 21 ... Source / drain diffused layer, 21a ... Low concentration Part, 21b ... High concentration part, 22 ... Silicide, 31 ... Stress film, 41, 42, 43 ... Interlayer insulating film, 51 ... Contact plug, 52 ... Barrier metal, 61 ... Wiring layer, 62 ... Barrier metal.

Claims (5)

A semiconductor substrate;
A trench formed on a surface of the semiconductor substrate and defining an element region;
A MOSFET comprising: a gate insulating film provided on the semiconductor substrate; a gate electrode provided on the gate insulating film; and a source / drain diffusion layer sandwiching a channel region below the gate electrode;
A stress film formed continuously on the gate electrode, the source / drain diffusion layer and in the trench, and applying a tensile stress or a compressive stress to the semiconductor substrate;
An insulating film that embeds the trench through the stress film;
A semiconductor device comprising:   When the conductivity type of the channel of the MOSFET is n-type, the stress film is substantially composed of a material that applies tensile stress to the semiconductor substrate. When the conductivity type of the channel of the MOSFET is p-type, the semiconductor substrate The semiconductor device according to claim 1, wherein the semiconductor device is substantially made of a material that applies compressive stress to the substrate.   The stress film is made of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an aluminum oxide film, an aluminum nitride film, a tantalum oxide film, a titanium oxide film, or a laminated film of these materials. The semiconductor device according to claim 1. Further comprising an insulating film formed on a side surface of the trench;
The stress film is formed in the trench through the insulating film;
2. The semiconductor device according to claim 1, wherein Forming a trench for partitioning an element region on a surface of a semiconductor substrate;
Forming a MOSFET including a gate insulating film, a gate electrode formed on the gate insulating film, and a source / drain diffusion layer sandwiching a channel region below the gate electrode on the surface of the semiconductor substrate;
Forming a stress film that applies a tensile stress or a compressive stress to the semiconductor substrate, which is continuous on the gate electrode, the source / drain diffusion layer, and in the trench;
Filling the trench with a first insulating film through the stress film;
A method for manufacturing a semiconductor device, comprising:

Images