JP2021524149A - Selective etching and controlled atomic layer etching of transition metal oxide films for device manufacturing - Google Patents

Abstract

Selective etching and controlled atomic layer etching of transition metal oxide films for device manufacturing, as well as the resulting devices are described. In an example, the method of dry etching a film involves forming a transition metal oxide film having a latent pore forming material inside. The method also comprises removing the surface portion of the potential pore forming material of the transition metal oxide film to form a porous region of the transition metal oxide film. The method also comprises removing the porous region of the transition metal oxide film.

Description

The embodiments of the present disclosure relate to the field of semiconductor structure and processing, in particular to selective etching and controlled atomic layer etching of transition metal oxide films for device manufacturing, and the resulting devices.

Over the last few decades, scaling features in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling to increasingly fine features allows for increased density of functional units over the limited area of semiconductor chips.

In a first aspect, the integrated circuit comprises a conductive microelectronic structure commonly known in the art as a via, thereby allowing the metal wire or other interconnect above the via to the metal wire or other below the via. Electrically connect to the interconnect of. Vias are typically formed by a lithography process. Typically, the photoresist layer can be spin coated over the dielectric layer, the photoresist layer can be exposed to patterned chemical lines through a patterned mask, and then into the photoresist layer. The exposed layer can be developed to form an opening. Next, by using the openings of the photoresist layer as an etching mask, the openings for vias can be etched into the dielectric layer. This opening is called a via opening. Finally, the via openings can be filled with one or more metals or other conductive materials to form vias.

One challenge is that the superposition between the vias and the upper interconnects and the superposition between the vias and the lower landing interconnects are generally controlled with a high margin of error of about a quarter of the via pitch. Need to be done. As the via pitch scales smaller and smaller, the overlay tolerance also tends to scale accordingly, even faster than the lithography equipment can keep up. Therefore, improvements are needed in the area of vias and related interconnect manufacturing technologies.

In the second aspect, multi-gate transistors such as tri-gate transistors have become more widely used as device dimensions continue to shrink. In conventional processes, trigate transistors or other non-planar transistors are typically manufactured on either a bulk silicon substrate or a silicon on insulator substrate. In some cases, bulk silicon substrates are suitable due to their lower cost and compatibility with the infrastructure of existing high yield bulk silicon substrates. However, it has not been possible to scale a multi-gate transistor without causing an effect. Used to manufacture these building blocks as the dimensions of these basic building blocks of a microelectronic circuit decrease and as the number of building blocks manufactured in a given region increases. The restrictions on semiconductor processes are increasing. Therefore, improvements are needed in the area of non-planar transistor manufacturing technology.

A cross-sectional view and a corresponding plan view of the operation in the controlled etching scheme of the transition metal oxide film according to the embodiment of the present disclosure are shown. FIG. 3 shows a cross-sectional view of the operation in a controlled etching scheme of a transition metal oxide film according to another embodiment of the present disclosure. FIG. 3 shows a cross-sectional view of the operation in a controlled etching scheme of a transition metal oxide film according to another embodiment of the present disclosure. FIG. 5 shows a cross-sectional view of a portion of an integrated circuit layer representing various operations in a method involving self-aligned conductive via formation for back end of line (BEOL) interconnect manufacturing according to an embodiment of the present disclosure. FIG. 5 shows a cross-sectional view of a portion of an integrated circuit layer representing various operations in a method involving self-aligned conductive via formation for back end of line (BEOL) interconnect manufacturing according to an embodiment of the present disclosure. FIG. 5 shows a cross-sectional view of a portion of an integrated circuit layer representing various operations in a method involving self-aligned conductive via formation for back end of line (BEOL) interconnect manufacturing according to an embodiment of the present disclosure. FIG. 5 shows a cross-sectional view of a portion of an integrated circuit layer representing various operations in a method involving self-aligned conductive via formation for back end of line (BEOL) interconnect manufacturing according to an embodiment of the present disclosure. FIG. 5 shows a cross-sectional view of a portion of an integrated circuit layer representing various operations in a method involving self-aligned conductive via formation for back end of line (BEOL) interconnect manufacturing according to an embodiment of the present disclosure. FIG. 5 shows a cross-sectional view of a portion of an integrated circuit layer representing various operations in a method involving self-aligned conductive via formation for back end of line (BEOL) interconnect manufacturing according to an embodiment of the present disclosure. The selective etching of the gate electrode cap layer with respect to the contact cap layer for manufacturing a self-aligned gate contact according to the embodiment of the present disclosure is shown. The selective etching of the gate electrode cap layer with respect to the contact cap layer for manufacturing a self-aligned gate contact according to the embodiment of the present disclosure is shown. The selective etching of the gate electrode cap layer with respect to the contact cap layer for manufacturing a self-aligned gate contact according to the embodiment of the present disclosure is shown. Various operations in the treatment scheme using the transition metal oxide dry etching approach for the gate electrode treatment according to the embodiment of the present disclosure are shown. The cross-sectional view of the non-planar type semiconductor device which concerns on embodiment of this disclosure is shown. A plan view of the semiconductor device of FIG. 7A along the aa'axis according to the embodiment of the present disclosure is shown. A computing device according to an implementation of the present disclosure is shown. An interposer that implements one or more embodiments of the present disclosure.

Selective etching and controlled atomic layer etching of transition metal oxide films for device manufacturing, as well as the resulting devices are described. In the following description, a number of specific details are described, including specific integrations and material regimes, to provide a full understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other examples, well-known features such as integrated circuit design layouts are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are exemplary representations and are not necessarily depicted to scale.

Certain terms may also be used in the following description for reference purposes only and are therefore not intended to be limiting. For example, terms such as "top," "bottom," "top," and "bottom," "bottom," and "top" refer to directions within the referenced drawing. Terms such as "front", "rear", "back", and "side" are consistent but arbitrary, as revealed by reference to the text and related drawings that describe the components under discussion. Describe the orientation and / or position of the component parts within a flexible reference frame. Such terms may include the words specifically mentioned above, their derivatives, and words with similar meanings.

The embodiments described herein may relate to the semiconductor processing and structure of the Front End of Line (FEOL). FEOL is the first part of integrated circuit (IC) manufacturing in which individual devices (eg, transistors, capacitors, resistors, etc.) are patterned on a semiconductor substrate or layer. FEOL generally includes everything up to (but not including) the deposition of metal interconnect layers. After the final FEOL step, a wafer typically results with separated transistors (eg, without any wires).

The embodiments described herein may relate to the semiconductor processing and structure of the back end of line (BEOL). BEOL is a second part of IC manufacturing in which individual devices (eg, transistors, capacitors, resistors, etc.) are interconnected with wiring on a wafer, such as one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers can be added in BEOL.

The embodiments described below may be applied to FEOL treatment and structure, BEOL treatment and structure, or both FEOL treatment and structure and BEOL treatment and structure. In particular, exemplary processing schemes can be demonstrated using the context of FEOL processing, but such an approach can also be applied to BEOL processing. Similarly, exemplary processing schemes can be demonstrated using the context of BEOL processing, but such an approach can also be applied to FEOL processing.

One or more embodiments described herein relate to selective etching of metal oxide films and controlled atomic layer etching. Embodiments may relate to one or more of selective etching and controlled atomic layer etching of metal oxide films, including atomic layer deposition, atomic layer etching, etching selectivity, metal oxides, and potential porosity. , Provides depth control for etching. The embodiments described herein can be implemented to enable new integration schemes that require multicolored dielectrics. An example is described herein.

To provide context, a new integration scheme for integrated circuit manufacturing uses a variety of dielectric materials with the selective etching required to remove / recess another material in the presence of one material. It may need to be present (eg in a particular layer). However, HfO _2, for ZrO ₂ or a combination of other similar, selective etching of a similar material may be not be easily achieved. This is because such pairs of materials can be very similar in etching properties.

According to one or more embodiments of the present disclosure, selective etching of similar metal oxide films in flat regions and features is performed with one of the metal oxide films and metal oxides that are oxides or non-transitional metal oxides. It is achieved through mutual mixing with components with higher or lower etchability, such as possible second oxide species. Such intermixed metal oxides, or co-oxides, are present during one vapor deposition of metal oxides, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Can be generated. Cooxide components can be dispersed in transition metal oxide films in a variety of ways. An example thereof will be described later in relation to FIGS. 1 to 3.

According to the embodiments of the present disclosure, the etching properties of the transition metal oxide film are modified by introducing a cooxide into the transition metal oxide film. An etching process that first targets the removal of cooxide may be selected. As the cooxide is removed, the etchability of the surrounding metal oxide material increases. In addition, the inclusion of cooxide may provide an opportunity to adjust the dielectric properties of the transition metal oxide film.

In some embodiments, in addition to selective etching, the approaches described herein can be used to control the "atomic" layer etching of metal oxides. For example, with reference to FIG. 2, which is described in more detail below, the cooxide can be used as an etching stop layer, allowing the metal oxide material to be removed from above, but further unless desired. Inhibits etching. In other embodiments, the deposition process can be modified to provide a thin layer of metal nitride to provide a difference in etching selectivity. In such cases, a nitride of the same metal as the transition metal oxide can be used in a deposition process that switches between co-reactants, requiring only one metal precursor (eg, TiO ₂ / TiN). Form a pair or a Ta ₂ O ₅ / TaN pair).

In a first example, FIG. 1 shows a cross-sectional view and a corresponding plan view of the operation in a controlled etching scheme of a transition metal oxide film according to an embodiment of the present disclosure.

Referring to the portion (a) of FIG. 1, the method of dry etching the film 102 on or above the substrate 100 includes forming a transition metal oxide film 104 having a latent pore forming material 106 in it. In the embodiment, as shown in FIG. 1, the latent pore-forming material 106 is randomly dispersed in the transition metal oxide film 104. The film 102 has a thickness (T).

In an embodiment, the transition metal oxide film 104 having the latent pore-forming material 106 in it is formed by co-reacting an oxide precursor during the gas phase deposition process. In embodiments, the transition metal oxide film 104 comprises a transition metal oxide material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, niobium oxide and tantalum oxide. In embodiments, the latent pore-forming material 106 comprises a material selected from the group consisting of aluminum oxide, gallium oxide, tin oxide, cobalt oxide, nickel oxide, and silicon oxide. In embodiments, the latent pore-forming material 106 occupies between 10 percent and 25 percent of the total volume of the transition metal oxide film 104 (ie, between 10 percent and 25 percent of the total volume of the film 102).

With reference to the portion (b) of FIG. 1, the surface portion of the latent pore-forming material 106 of the transition metal oxide film 104 is removed to form the porous region 108 of the transition metal oxide film 104, for example, modified. The transition metal oxide film 104'is formed.

With reference to portion (c) of FIG. 1, the porous region 108 of the modified transition metal oxide film 104'has been removed, for example having a thickness reduced by the amount of etching (X), i.e. T-. A partially etched transition metal oxide film 104 "with a thickness of X is formed. Steps (b) and (c) are repeated until the film 102 of the desired thickness is removed. You should understand what you get.

In the embodiment, for an etching solution that easily etches the latent hole forming material 106 (also referred to as a cooxide in the present specification), when the surface portion of the latent hole forming material 106 comes into contact with the etching solution. It represents a weak point in the film 102 that is selectively dissolved. As the cooxide is removed, the remaining porous metal oxide (eg, having region 108) is also removed at a faster rate than the underlying high density metal oxide. This is because the contact with the etching solution is larger and the access point to the metal center of the transition metal oxide film is increased.

In the embodiment, the removal of the surface portion of the latent pore forming material 106 is carried out in the first etching process and the removal of the porous region 108 of the transition metal oxide film 104 is carried out in the second different etching process. In another embodiment, the removal of the surface portion of the latent pore forming material 106 is performed in the first etching process and the removal of the porous region 108 of the transition metal oxide film 104 is performed in the same etching process. In the embodiment, the removal of the surface portion of the latent pore forming material 106 and the removal of the porous region 108 of the transition metal oxide film 104 are performed using one or more plasma etching processes.

In a second example, FIG. 2 shows a cross-sectional view of the operation in a controlled etching scheme of the transition metal oxide film according to another embodiment of the present disclosure.

Referring to the portion (a) of FIG. 2, the method of dry etching the film 202 on or above the substrate 200 alternately forms the transition metal oxide film 204 and the layer of the latent pore forming material 206 between them. Including stages. In the embodiment, as shown in FIG. 2, the latent pore-forming material 206 is dispersed in the transition metal oxide film 204 as one or more laminated plane layers.

With reference to the portion (b) of FIG. 2, the surface layer of the latent pore forming material 206 is removed in order to expose the lower layer of the transition metal oxide film 204. With reference to portion (c) of FIG. 2, the exposed lower layer of the transition metal oxide film 204 is removed to expose the next layer of latent pore forming material 206. In an embodiment, the next layer of latent pore forming material 206 is an effective etching stop layer, which provides highly controlled removal of only the top layer of the transition metal oxide film 204. It should be understood that the processes of steps (b) and (c) can be repeated until the film 202 of the desired thickness is removed.

In a third example, FIG. 3 shows a cross-sectional view of the operation in a controlled etching scheme of the transition metal oxide film according to another embodiment of the present disclosure.

With reference to the portion (a) of FIG. 3, the method of dry-etching the film 302 in the dielectric layer 301 or on the substrate 300 is to dry-etch a layer of the transition metal oxide film 304 and the latent pore-forming material 306 between them. Includes alternating steps (for simplicity of explanation, one layer 306 is shown in FIG. 3). In the embodiment, as shown in FIG. 3, the latent pore-forming material 306 is dispersed as a conformal layer in the transition metal oxide film 304.

With reference to the portion (b) of FIG. 3, latent pore formation is performed in order to effectively form the porous upper region of the transition metal oxide film 304 and to form the recessed latent pore forming material 306. The surface portion of material 306 is removed. Referring to the portion (c) of FIG. 3, the porous upper region of the transition metal oxide film 304 is removed in order to provide the recessed transition metal oxide film 304. It should be understood that the processes of steps (b) and (c) can be repeated until the film 302 of the desired thickness is removed.

With respect to the implementation of the etching schemes described herein, the need to control the production of features at nanometer and lower levels becomes mandatory as conventional scaling, eg, reduction of minimum line widths smaller than 14 nanometers, continues. It should be understood that Membrane stacks are now constantly approaching 2-3 nanometer thicknesses in many applications, requiring the adoption of accurate atomic level techniques such as atomic layer etching. In particular, the efficient etching and removal of transition metal oxides in semiconductor processing is becoming increasingly important as more of these elements are incorporated into all transient technology nodes.

Three exemplary implementations of transition metal oxide film etching are described below as first, second, and third aspects of the embodiments of the present disclosure. It should be understood that the three exemplary implementations by no means limit the possible applications of the etching approach described herein. Implementations can include, but are by no means limited to, advanced transistor architectures.

In the first exemplary implementation, one or more embodiments relate to an approach for producing metal wire and associated conductive vias. One or more conductive vias, by definition, are used to land on the metal pattern of the previous layer. Similarly, the embodiments described herein allow for a stronger interconnect manufacturing scheme, as restrictions on lithography equipment are relaxed. Such interconnect manufacturing schemes can be used to eliminate the need for multiple alignments / exposures, otherwise the overall process operations and processing required to pattern such features using traditional approaches. It can be used to reduce time. Other benefits may include improved yields or prevention of incorrect wire short circuits. Embodiments may be implemented to provide improved via short-circuit margins, for example, for 10 nm and smaller technology nodes, by "coloring" self-alignment through selective deposition, and subsequent self-organization. ..

In an exemplary approach using colored hardmask selection of conductive wires and caps, FIGS. 4A-4F show the self-aligned conductive via formation for the back end of line (BEOL) interconnect manufacturing according to the embodiments of the present disclosure. A cross-sectional view of a portion of the integrated circuit layer representing various operations in the accompanying method is shown.

With reference to FIG. 4A, the initial structure 400 is provided as a starting point for manufacturing a new metallization layer (eg, BOOL layer). The initial structure 400 includes an interstitial dielectric (ILD) layer 404 located above the substrate 402. As described below, the ILD layer may be placed above the underlying metallization layer formed above the substrate 402. The trench is formed in the ILD layer 404 and is filled with one or more conductive layers, thereby providing a conductive wire 406 (and, in some cases, a corresponding conductive via 408). In an embodiment, a pitch split patterning process flow is used to form a trench in the conductive wire 406 in the ILD layer 404. It should be understood that the following process operations described below may or may not include pitch splitting first. In either case, however, especially when pitch division is also used, embodiments may allow the pitch scaling of the metal layer to be continuously varied beyond the resolution of conventional lithography equipment.

Referring to FIG. 4B, optionally, the conductive wire 406 is recessed below the upper surface of the ILD layer 404 and has a recessed region 412 above the recessed conductive wire 410. Line 410 is provided. In embodiments, the conductive wire 406 is recessed to form the recessed conductive wire 410 using a selective wet etching process, such as a wet etching process based on sulfuric acid and hydrogen peroxide. In another embodiment, the conductive wire 406 is recessed to form a recessed conductive wire 410 using a selective dry or plasma etching process.

With reference to FIG. 4C, a conductive cap 414 is optionally formed in the recessed region 412 above the recessed conductive wire 410. In the embodiment, the conductive cap 414 is made of a material having surface characteristics that are significantly different from the surface of the ILD layer 404 than the material of the conductive wire 406. In embodiments, the conductive wire 406 comprises a copper-filled material in a barrier liner of titanium nitride or tantalum nitride, and the conductive cap 414 is, but is not limited to, Al, Pt, Ni, Ru, Pd, W, Ti, It is composed of a metal such as Ta, Ir, or Er, or an alloy thereof. In another embodiment, Co or an alloy of Co such as CoWB is used. In embodiments, at least a portion of the conductive wire 406 (eg, a copper-filled material) is formed using electroplating, and the conductive cap 414 is a chemical vapor deposition (CVD) process, atomic layer deposition (ALD). ) Process, physical vapor deposition (PVD) process, electron beam deposition process, electroplating, electroless deposition process, or spin-on process. In each case, in both embodiments, after deposition, the material of the conductive cap 414 is flattened, for example using chemical mechanical polishing (CMP), and the top surface of the ILD layer 404, as illustrated in FIG. 4C. Produces a conductive cap 414 that is substantially coplanar with. As described herein, in embodiments, metal cap formation is based on a recessing, filling, CMP process. In another embodiment, cap deposition is achieved through selective deposition (eg, in either concave or non-concave profiles). In another embodiment, cap formation is achieved through selective deposition.

In addition to the metal protection of the recessed conductive wire 410 in the subsequent processing steps, it should be understood that the conductive cap material can also assist in the selective deposition of hardmask materials, especially "color" hardmask materials. be. For example, Ru and W provide improved DSA brush graft densities compared to cobalt. Moreover, selective metal oxide deposition on Co using a self-assembled monolayer (SAM) can be difficult due to the oxidizing tendency of cobalt. In an embodiment, the conductive cap 414 provides the advantages of airtightness during processing and reliability in place of the conventional etching stop layer, in addition to promoting pattern replication, as described below.

With reference to FIG. 4D, the hard mask layer 416 is formed on the structure of FIG. 4C. The hardmask layer 416 includes a first hardmask component 418 and a second hardmask component 420. The first hardmask component is formed on and aligned with the conductive cap 414. The second hard mask component 420 is formed on and aligned with the exposed surface of the ILD layer 404. In an embodiment, the hard mask layer 416 with the first hard mask component 418 and the second hard mask component 420 is formed using a self-organizing or selective deposition approach and finally the first hard mask component 418. And the second hardmask component 420 alternate to form two different regions. In one such embodiment, the self-assembling or selective deposition approach is enhanced by the use of a conductive cap 414, as opposed to using the surface of the conductive wire 406. In embodiments, the materials of the first hard mask component 418 and the second hard mask component 420 exhibit different etching selectivity from each other. As described in more detail below, self-organization or selective growth is used to selectively align the first hardmask component 418 and the second hardmask component 420 with the dielectric and metal surfaces, respectively. can.

In an embodiment, the first hard mask component 418 comprises a transition metal oxide film having a latent pore-forming material (shown as a point) therein. In one embodiment, the transition metal oxide film comprises a transition metal oxide material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, niobium oxide and tantalum oxide. In one embodiment, the latent pore-forming material comprises a material selected from the group consisting of aluminum oxide and silicon oxide. In embodiments, as described above, co-reactive vapor phase deposition is used to form a transition metal oxide film with latent pore-forming material therein.

In an embodiment, as illustrated in FIG. 4D, the first hardmask component 418 is limited to the top surfaces of the plurality of conductive wires 410 (eg, conductive caps 414). In another embodiment (not shown), the first hardmask component 418 extends to the top surface portion of the ILD layer 404.

In a first general embodiment, a self-assembling (DSA) block copolymer deposition and polymer assembling process is performed to finally form the first hard mask component 418 and the second hard mask component 420. In embodiments, the DSA block copolymer is coated and annealed on the surface and the polymer is separated into first and second blocks. In one embodiment, the first polymer block preferably binds to the exposed surface of the ILD layer 404. The second polymer block adheres to the conductive cap 414. In embodiments, each of the second and first block polymers is sequentially replaced with the materials of the first hard mask component 418 and the second hard mask component 420, respectively. In one such embodiment, selective etching and deposition processes are used to replace the second and first block polymers with the materials of the first hard mask component 418 and the second hard mask component 420, respectively.

In a second general embodiment, a selective growth process is used instead of the DSA approach to finally form the first hardmask component 418 and the second hardmask component 420. In one such embodiment, the material of the second hard mask component 420 grows above the exposed portion of the ILD layer 404. A second different material of the first hardmask component 418 grows above the conductive cap 414. In embodiments, selective growth is achieved by a deposition / etching / deposition / etching approach for both the materials of the first hardmask component 418 and the second hardmask component 420, resulting in multiple layers of each material. Such an approach may be preferred over conventional selective growth techniques that can form a film in the form of "upper mushrooms". The tendency of film growth to become mushroom-shaped at the top can be reduced through an alternating deposition / etching / deposition (dep-etch-dep-etch) approach. In another embodiment, the membranes are selectively deposited on the metal, then different membranes are selectively deposited on the ILD (and vice versa) and repeated multiple times to form a sandwich-like stack. Form. In another embodiment, both materials grow simultaneously (eg, by a CVD process) in a reaction chamber that selectively grows on each exposed area of the underlying substrate.

As described in more detail below, in embodiments, the resulting structure of FIG. 4D allows for improved via short circuit margins when later producing a via layer on top of the structure of FIG. 4D. In one embodiment, manufacturing a structure with alternating "color" hardmask components reduces the risk of vias shorting to the wrong metal wire, thus achieving an improved short circuit margin. In one embodiment, the alternating color hardmask components self-align with the alternating ILD layer 104 and the surface of the underlying conductive cap 414, thus achieving self-alignment. In embodiments, as shown, the first hardmask component 418 is limited to the conductive caps 414 of the plurality of conductive wires 410. However, in another embodiment (not shown), the first hardmask component 418 extends to the top surface portion of the ILD layer 404.

Referring to FIG. 4E, a second interstitial dielectric (ILD) layer 422 is formed above the structure of FIG. 4D. An opening 424 is formed in the second ILD layer 422. In an embodiment, the opening 424 is formed at a position selected for the production of conductive vias for the next level of metallization layer. In contrast to conventional via position selection, the opening 424 has a relatively relaxed width in one embodiment as compared to the width of the corresponding conductive wire 406 in which the conductive via is finally formed. For example, in certain embodiments, the width (W) of the opening 424 has a pitch dimension of about 3/4 of the conductive wire 406. Corresponding to such a relatively wide via opening 424 can relax restrictions on the lithography process used to form the opening 424. In addition, the misalignment tolerance can be increased.

FIG. 4F shows the structure of FIG. 4E following the production of vias in the next layer. For example, one of the first hardmask components 418 is selected for removal by a selective transition metal oxide etching process, such as the process described above in connection with FIGS. 1 to 3. In this case, the exposed first hard mask component 418 is selectively removed by the exposed portion of the second hard mask component 420.

Conductive vias 428 are then formed in the openings 424 and in areas where selected of the first hardmask components 418 have been removed. The conductive via 428 makes electrical contact with the corresponding conductive cap 414 of the recessed conductive wire 410. In an embodiment, the conductive vias 428 are conductive of the recessed conductive wires 410 without short-circuiting with one of the adjacent or adjacent conductive caps 414 / recessed conductive wire 410 pairs. Electrical contact with the corresponding one on the cap 414. In certain embodiments, as illustrated in FIG. 4F, the portion of the conductive via 428 is located in one or more exposed portions of the second hardmask component 420. In embodiments, improved short circuit margins are achieved.

With reference to FIG. 4F again, in an exemplary embodiment, the integrated circuit structure includes a plurality of conductive wires 410 in the interlayer dielectric (ILD) layer 404 above the substrate 402. Each of the plurality of conductive wires 410 is recessed with respect to the uppermost surface of the ILD layer 404. The plurality of conductive caps 414 are on the corresponding ones of the plurality of conductive wires 410 in the recessed region above each of the plurality of conductive wires 410. The hard mask layer 426 is on the plurality of conductive caps 414 and on the top surface of the ILD layer 404. The hard mask layer 426 includes a first hard mask component 418 matched with them on a plurality of conductive caps 414. The second hardmask component 420 of the hardmask layer 426 is on and aligned with the top surface region of the ILD layer 404. The first hard mask component 418 and the second hard mask component 420 have different compositions from each other, and the first hard mask component 418 includes a transition metal oxide film having a latent pore-forming material therein. The conductive via 428 is in the hard mask layer 426 and in the opening on the conductive cap 414 of one of the plurality of conductive wires 410. The portion of the conductive via 428 is on the portion of the second hard mask component 420 of the hard mask layer 426.

In an embodiment, as illustrated in FIG. 4F, the plurality of conductive caps 414 have an top surface that is substantially coplanar with the top surface of the ILD layer 404. In an embodiment, as illustrated in FIG. 4F, the first hardmask component 418 has an uppermost surface that is substantially coplanar with the uppermost surface of the second hardmask component 420. In an embodiment, the integrated circuit structure further comprises a second ILD layer 422 above the hardmask layer 426. The conductive via 428 is further located within the opening of the second ILD layer 422. In one such embodiment, the opening of the second ILD layer has a width equal to about 3/4 of the pitch of the plurality of conductive wires 410. In an embodiment, as illustrated in FIG. 4F, one of the plurality of conductive wires 410 is coupled to the underlying conductive via structure 4108. In one such embodiment, the lower conductive via structure 408 is connected to a lower metallization layer (not shown) of the integrated circuit structure.

It should be understood that the layers and materials described in relation to FIGS. 4A-4F are typically formed on or above the underlayer semiconductor substrate or structure, such as the underlayer device layer of an integrated circuit. .. In embodiments, the underlayer semiconductor substrate represents a common machined object used to manufacture integrated circuits. Semiconductor substrates often include wafers or other components of silicon or other semiconductor materials. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulators (SOIs), as well as similar substrates made of other semiconductor materials. Semiconductor substrates often include transistors, integrated circuits, and the like, depending on the manufacturing stage. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly used for semiconductor substrates. In addition, the structures illustrated in FIG. 4F can be manufactured on lower levels of lower interconnect layers.

In embodiments, as used throughout this description, the interstitial dielectric (ILD) material is composed of or comprises a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO _2)), silicon nitride (eg, silicon nitride (Si 3 N _4)), doped silicon oxide, silicon fluoride oxide Includes materials, carbon-doped silicon oxides, various low dielectric constant dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by prior art such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

In embodiments, the metal wire or interconnect wire material (and via material) is composed of one or more metals or other conductive structures, as used throughout this description. A common example is the use of copper wire and structures that may or may not include a barrier layer between copper and the ILD material that surrounds it. The term metal as used herein includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect wire may include a barrier layer, a stack of different metals or alloys, and the like. Thus, the interconnect wire can be a single material layer or can be formed from multiple layers, including a conductive liner layer and a packed layer. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, can be used to form the interconnect lines. In embodiments, the interconnect wire is composed of a barrier layer and a conductive filling material. In one embodiment, the barrier layer is a tantalum or tantalum nitride layer, or a combination thereof. In one embodiment, the conductive filling material is not limited to these, but Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. It is a conductive material such as. In addition, the interconnect wire may be referred to in the art as a wiring, a wire, a line, a metal, a metal wire, or simply an interconnect.

The patterned features can be patterned in a grid pattern with lines, holes, or trenches of constant width at constant pitch intervals. For example, the pattern can be manufactured by a pitch 2-split or pitch 4-split approach. In an example, a blanket film (such as a polycrystalline silicon film) is patterned using, for example, spacer-based quadruple patterning (SBQP) or lithography and etching processes that may involve pitch quadrants. NS. Understand that line grid patterns can be manufactured by a number of methods, including 193 nm immersion lithography (i193), extreme ultraviolet lithography (EUV) and / or electron beam direct writing (EBDW) lithography, self-assembly, and the like. Should be. In other embodiments, the pitch and width do not have to be constant.

In a second aspect of the present disclosure, one or more embodiments relate to an approach for landing a gate contact via just above an active transistor gate, and the structure formed from it. Such an approach can eliminate the need to extend a separate gate line for contact purposes. Such an approach can also eliminate the need for separate gate contact layers to conduct signals from gate lines or structures. In embodiments, removal of the above features is achieved by recessing the contact metal into the trench contacts and introducing additional dielectric material in the process flow. Additional dielectric materials are included as trench contact dielectric cap layers that have different etching properties than the gate dielectric material cap layers already used for trench contact matching in gate matching contact process processing schemes.

As an example, FIGS. 5A-5C show selective etching of a gate electrode cap layer against a contact cap layer for the manufacture of self-aligned gate contacts according to an embodiment of the present disclosure.

With reference to FIG. 5A, the gate stack 502 is formed on or above the substrate 500. The first and second conductive trench contacts 514 are the first and second surfaces of the gate stack 502, respectively, with any dielectric spacer 512 formed between them. The first hardmask component 510 is formed and aligned with the top surface of the gate stack 502. The second hard mask component 516 is formed on and aligned with the first and second conductive trench contacts 514. The first hard mask component 510 and the second hard mask component 516 have different compositions from each other. In an embodiment, the first hard mask component 510 comprises a transition metal oxide film having a latent pore-forming material therein. In an embodiment, as illustrated, the gate stack 502 includes a high-k gate dielectric layer 504, a work function gate electrode layer 506, and a conductive packing layer 508.

In embodiments, the transition metal oxide film comprises a transition metal oxide material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, niobium oxide and tantalum oxide. In embodiments, the latent pore-forming material comprises a material selected from the group consisting of aluminum oxide and silicon oxide.

Referring to FIG. 5B, the first hard mask component 510 is removed from above the gate electrode 502 to form an opening 520 above the gate electrode 502. Aperture 520 may expose only a portion of the gate electrode 502, but the portion of the gate electrode 502 below and above the perspective page shown remains covered by the remaining unetched portion of the first hardmask component 510. You should understand that there is. In embodiments, the first hardmask component 510 is selectively removed from the second hardmask component 516 and, where applicable, the dielectric spacer 512.

With reference to FIG. 5C, the conductive via 522 is formed in the first hardmask component and at the opening 520 over a portion of the gate stack 502. In an embodiment, as shown, the portion of the conductive via 522 is on the portion of the second hardmask component 516.

In a third aspect of the present disclosure, embodiments relate, for example, to the recessing of a gate dielectric layer for forming a dielectric cap. FIG. 6 shows various operations in a treatment scheme that uses a transition metal oxide dry etching approach for gate electrode treatment according to an embodiment of the present disclosure.

With reference to the portion (a) of FIG. 6, a plurality of gate trenches 600 are formed in the insulating or dielectric layer 602 formed above the substrate 604. With reference to the portion (b) of FIG. 6, the transition metal oxide gate dielectric layer 606 is formed in the plurality of gate trenches 600. In the embodiment, the transition metal oxide gate dielectric layer 606 includes a transition metal oxide film having a latent pore-forming material therein. Next, as shown in the portion (b) of FIG. 6, the gate electrode 608 is formed on the transition metal oxide gate dielectric layer 606. The gate electrode 608 can be controlled to the level of the field, or growth can be over-performed and then re-flattened (eg by a CMP process), during which time transition metal oxides are formed on the field. It should be understood that the gate dielectric layer 606 can also be removed.

With reference to the portion (c) of FIG. 6, the gate electrode 608 and the transition metal oxide gate dielectric layer 606 are partially recessed, and the recessed gate electrode 610 and the recessed transition metal oxide gate dielectric layer 612 are formed. Each is provided. In one such embodiment, the gate electrode 608 is first selectively partially recessed in the transition metal oxide gate dielectric layer 606. The transition metal oxide gate dielectric layer 608 is then partially recessed using a transition metal oxide dry etching approach as described above in connection with FIGS. 1-3. With reference to portion (d) of FIG. 6, the dielectric cap layer 620 is then formed on the recessed gate electrode 610 and on the recessed transition metal oxide gate dielectric layer 612. Such a dielectric cap layer 620 can be used to facilitate further processing and / or to prevent short circuits between different conductive features, such as for self-aligned contact formation. As described in connection with FIGS. 5A-5C, the dielectric cap layer 620 itself can be formed as a transition metal oxide film having a latent pore-forming material therein.

One or more embodiments described herein relate to the manufacture of semiconductor devices, such as for the manufacture of MIMO and NMOS devices. For example, one or more features of a semiconductor device are formed using a transition metal oxide dry etching approach as described in connection with FIGS. 1 to 3. As an example of the completed device, FIGS. 7A and 7B show a cross-sectional view and a plan view (along the aa'axis of the cross-sectional view) of the non-planar semiconductor device according to the embodiment of the present disclosure, respectively. .. As described below, the transition metal oxide gate dielectric film can be recessed by using a transition metal oxide dry etching approach, as described herein.

With reference to FIG. 7A, the semiconductor structure or device 700 includes a non-planar active region within the separation region 706 formed from the substrate 702 (eg, a fin structure including a protruding fin portion 704 and a sub fin region 705). The gate line 708 is placed on the overhanging portion 704 of the non-planar active region and on the portion of the separation region 706. As shown, the gate wire 708 includes a gate electrode 750 and a gate dielectric layer 752. In one embodiment, the gate wire 708 may also include a dielectric cap layer 754. The gate contact 714 and the upper gate contact via 716 can also be seen from this perspective view. Together with the gate contacts 714 and the upper gate contact vias 716, they are all located on the interlayer dielectric stack or layer 770. As can be further seen from the perspective view of FIG. 7A, in one embodiment the gate contact 714 is located above the separation region 706, but not above the non-planar active region. In an embodiment, the fin pattern is a grid pattern.

In an embodiment, as described in connection with FIGS. 1-3, the transition metal oxide dry etching approach is used to recess at least a portion of the dielectric layer 752 and then the dielectric cap layer 754. Is formed. Here, the dielectric layer 752 is or includes a transition metal oxide film having a latent pore-forming material therein. In the same or different embodiments, the dielectric cap layer 754 is formed from a transition metal oxide film having a latent pore-forming material therein.

With reference to FIG. 7B, the gate line 708 is shown as being located on the protruding fin portion 704. The source and drain regions 704A and 704B of the protruding fin portion 704 can be seen from this perspective view. In one embodiment, the source and drain regions 704A and 704B are the doped portions of the original material of the protruding fin portion 704. In another embodiment, the material of the protruding fin portion 704 is removed and replaced with another semiconductor material, for example by epitaxial growth. In either case, the source and drain regions 704A and 704B can extend below the height of the dielectric layer 706, i.e. within the subfin region 705.

In embodiments, the semiconductor structure or device 700 is a non-planar device, such as, but not limited to, a FinFET or trigate device. In such an embodiment, the channel region of the corresponding semiconductor is composed of or formed into a three-dimensional object. In one such embodiment, the gate electrode stack of gate wires 708 surrounds at least a pair of top and side walls of a three-dimensional object. This concept can extend to the gates of the entire device, such as nanowire-based transistors.

The substrate 702 can be made of a semiconductor material that can withstand the manufacturing process and can transfer charges. In embodiments, the substrates 702 described herein are crystalline silicon, silicon / silicon, doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, or a combination thereof to form the active region 704. It is a bulk substrate composed of germanium or a germanium layer. In one embodiment, the concentration of silicon atoms in the bulk substrate 702 is higher than 97%. In another embodiment, the bulk substrate 702 is composed of an epitaxial layer grown on a separate crystalline substrate, eg, a silicon epitaxial layer grown on a boron-doped bulk silicon single crystal substrate. The bulk substrate 702 may optionally be composed of a group III-V material. In embodiments, the bulk substrate 702 is gallium nitride, gallium phosphide, gallium phosphide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium phosphide, indium phosphide, and the like. Or composed of III-V materials such as combinations thereof. In one embodiment, the bulk substrate 702 is composed of a III-V material and the charge carrier dopant impurity atoms are, but are not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, tellurium and the like.

The separation region 706 is an activity formed in the lower bulk substrate such that the permanent gate structure is finally partially electrically separated from the lower bulk substrate or contributes to the separation, or the fin active region is separated. It may be composed of a material suitable for separating the regions. For example, in one embodiment, the separation region 706 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon nitride, silicon nitride, or carbon-doped silicon nitride.

The gate wire 708 may consist of a gate electrode stack that includes a gate dielectric layer 752 and a gate electrode layer 750. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide. , But not limited to, composed of materials such as aluminum oxide, lead tantalum pentoxide, lead zinc niobate or a combination thereof. In addition, some of the gate dielectric layers may include a layer of natural oxide formed from some top layer of substrate 702. In embodiments, the gate dielectric layer is composed of a high-k portion of the top and a bottom composed of oxides of the semiconductor material. In one embodiment, the gate dielectric layer is composed of an upper part of hafnium oxide and a bottom part of silicon dioxide or silicon nitride.

The spacer associated with the gate wire or gate electrode stack is a suitable material that ultimately electrically separates the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts, or contributes to this separation. Can consist of. For example, in one embodiment, the spacer is composed of, but is not limited to, a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride or carbon-doped silicon nitride.

The gate contact 714 and the upper gate contact via 716 may be made of a conductive material. In embodiments, one or more of the contacts or vias are composed of metal species. The metal species may be a pure metal such as tungsten, nickel, or cobalt, or an alloy such as an intermetal alloy or a metal-semiconductor alloy (eg, silicic material).

In an embodiment (not shown), the provision of structure 700 involves forming a contact pattern that is essentially perfectly matched to an existing gate pattern without using the very stringent lithography steps of the positioning budget. In one such embodiment, this approach allows the use of inherently highly selective wet etching (eg, as opposed to conventional dry etching or plasma etching) to generate contact openings. .. In embodiments, the contact pattern is formed by utilizing an existing gate pattern in combination with the contact plug lithography process. In one such embodiment, the approach makes it possible to eliminate the otherwise critical lithography steps used in conventional approaches to generate contact patterns. In embodiments, trench contact grids are not patterned separately, but rather formed between poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed after gate grid patterning but before gate grid cut.

In addition, the gate stack structure 708 can be manufactured by the replacement gate process. In such schemes, dummy gate materials such as polysilicon or silicon nitride pillar materials can be removed and replaced with permanent gate electrode materials. In one such embodiment, the permanent gate dielectric layer is not carried over from the previous process, but is also formed in this process. In the embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polycrystalline silicon or amorphous silicon and is removed using a dry etching process involving the use of _{SF 6.} In another embodiment, the dummy gate is composed of polycrystalline silicon or amorphous silicon, is removed by wet etching process involving the use of aqueous NH 4 _OH solution or tetramethylammonium hydroxide aqueous solution. In one embodiment, the dummy gate is composed of silicon nitride and is removed by wet etching containing an aqueous solution of phosphoric acid.

In embodiments, the one or more approaches described herein are essentially intended to be a dummy and replacement gate process in combination with a dummy and replacement contact process to reach structure 700. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature annealing of at least a portion of the permanent gate stack. For example, in such particular embodiments, annealing of at least some of the permanent gate structures is performed, for example, at temperatures above about 600 ° C. after the gate dielectric layer has been formed. Annealing is performed prior to the formation of permanent contacts.

With reference to FIG. 7A again, the semiconductor structure or the configuration of the device 700 places the gate contact over the separation region. Such an arrangement may be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that serves as a contact for a portion of the gate electrode formed over the active region. Generally, one or more of the present disclosures prior to forming a gate contact structure (eg, vias) above the active portion of the gate and in the same layer as the trench contact vias (eg, in addition to forming it). Embodiments initially include the use of a gate-matched trench contact process. Such a process can be implemented to form a trench contact structure for the manufacture of semiconductor structures, eg, the manufacture of integrated circuits. In embodiments, the trench contact pattern is formed to match the existing gate pattern. In contrast, traditional approaches usually involve an additional lithography process that tightly positions the lithography contact pattern with respect to the existing gate pattern, in combination with selective contact etching. For example, a conventional process may include patterning a poly (gate) grid while patterning contact features separately.

It should be understood that all aspects of the process described above need not be practiced to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, the dummy gate need not be formed at all prior to making the gate contact above the active portion of the gate stack. The gate stack described above can actually be a permanent gate stack as originally formed. Also, the processes described herein can be used to manufacture one or more semiconductor devices. The semiconductor device can be a transistor or similar device. For example, in embodiments, the semiconductor device is a metal oxide film semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Also, in embodiments, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independently accessed double-gate device or a FinFET. One or more embodiments may be particularly useful for manufacturing semiconductor devices at 10 nanometers (10 nm) or smaller technology nodes.

It should be understood that both of the above aspects of the embodiments of the present disclosure can be applied to processing techniques in the front end of line or back end of line. In addition, the embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories may be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art. For example, computer systems (eg desktops, laptops, servers), mobile phones, personal electronic devices and the like. Integrated circuits can be coupled with buses and other components of the system. For example, the processor may be coupled to memory, chipsets, etc. by one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the approaches disclosed herein.

FIG. 8 shows a computing device 800 according to an implementation of the present disclosure. The computing device 800 houses the board 802. Board 802 may include a number of components, including, but not limited to, a processor 804 and at least one communication chip 806. The processor 804 is physically and electrically connected to the board 802. In some implementations, at least one communication chip 806 is also physically and electrically coupled to the board 802. In a further implementation, the communication chip 806 is part of the processor 804.

Depending on the application, the computing device 800 may include other components that may or may not be physically and electrically coupled to the board 802. These other components are, but are not limited to, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), flash memory, graphics processor, digital signal processor, crypto processor, chipset, antenna. , Display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and (hard disk drive, compact disk) Includes mass storage devices (such as (CD), digital multipurpose discs (DVD), etc.).

The communication chip 806 enables wireless communication for data transmission to and from the computing device 800. The term "radio" and its derivatives are used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that are capable of data communication using modulated electromagnetic radiation via non-solid media. May be used for. In some embodiments, the associated device may not include wired, but the term does not imply that these devices do not include wired at all. The communication chip 806 is not limited to Wi-Fi (IEEE802.11 family), WiMAX® (registered trademark) (IEEE802.16 family), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, LTE, GSM®, GPRS, CDMA, TDMA, DECT, Bluetooth®, derivatives thereof, and any other radio protocol designated as 3G, 4G, 5G and later generations. Any of a number of radio standards or protocols may be implemented, including. The computing device 800 may include a plurality of communication chips 806. For example, the first communication chip 806 may be dedicated to short-range wireless communication such as Wi-Fi® and Bluetooth®, and the second communication chip 806 may be GPS, LTE, GPRS, etc. It may be dedicated to long-range wireless communication such as CDMA, WiMAX®, LTE, Ev-DO and the like.

The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. In some implementations of the present disclosure, the integrated circuit die of the processor comprises one or more features manufactured using selective metal oxide etching constructed according to the implementation of the disclosure. The term "processor" is any device or part of any device that processes electronic data from multiple registers and / or memory and converts the electronic data into other electronic data that can be stored in the registers and / or memory. May point to.

The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. According to embodiments of the present disclosure, the integrated circuit die of the communication chip comprises one or more features manufactured using selective metal oxide etching constructed according to the implementation of the disclosure.

In a further implementation, another component housed within the compute device 800 is an integrated circuit containing one or more features manufactured using selective metal oxide etching built according to the disclosed implementation. May include dies.

In various implementation examples, the computing device 800 is a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultramobile PC, mobile phone, desktop computer, server, printer, scanner. , Monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In a further implementation, the computing device 800 can be any other electronic device that processes data.

FIG. 9 shows an interposer 900 that includes one or more embodiments of the present disclosure. The interposer 900 is an interposer substrate used as a bridge between the first substrate 902 and the second substrate 904. The first substrate 902 can be, for example, an integrated circuit die. The second substrate 904 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of the interposer 900 is to extend the connection to a wider pitch or to reroute the connection to a different connection. For example, the interposer 900 may connect an integrated circuit die to a ball grid array (BGA) 906 that can later be connected to a second substrate 904. In some embodiments, the first and second substrates 902/904 are mounted on the side facing the interposer 900. In other embodiments, the first and second substrates 902/904 are mounted on the same side as the interposer 900. In a further embodiment, the three or more substrates are interconnected by an interposer 900.

The interposer 900 may be made of a polymeric material such as epoxy resin, fiberglass reinforced epoxy resin, ceramic material or polyimide. In a further implementation, the interposer may contain the same materials as those described above used for semiconductor substrates, such as silicon, germanium, and other group III-V and IV materials, with alternating stiffening or overlapping. It can be made of flexible material.

The interposer may include a plurality of metal interconnects 908 and a plurality of vias 910, including, but not limited to, a plurality of through silicon vias (TSVs) 912. The interposer 900 may further include a plurality of embedded devices 914, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may be further formed on the interposer 900. According to embodiments of the present disclosure, the equipment or processes disclosed herein can be used in the manufacture of the interposer 900 or in the manufacture of the components contained in the interposer 900.

Accordingly, embodiments of the present disclosure include selective etching of transition metal oxide films for device fabrication, and controlled atomic layer etching, as well as the resulting device.

The above description of the indicated implementation of the embodiments of this disclosure, including those described in the abstract, is not intended to be exhaustive or to limit the disclosure to the exact form disclosed. .. Specific implementations and examples of the present disclosure are set forth herein for illustrative purposes and, as will be appreciated by those skilled in the art, various equivalent modifications are possible within the scope of the present disclosure. ..

These modifications may be made to this disclosure in light of the detailed description above. The terms used in the following claims should not be construed as limiting this disclosure to the specific implementations disclosed herein and in the claims. Rather, the scope of the present disclosure is entirely determined by the following claims, which are construed in accordance with the established policies of the claims.

Illustrative Embodiment 1: The method of dry etching a film includes a step of forming a transition metal oxide film having a latent pore-forming material inside. The method also comprises removing the surface portion of the potential pore forming material of the transition metal oxide film to form a porous region of the transition metal oxide film. The method also comprises removing the porous region of the transition metal oxide film.

Illustrative Embodiment 2: The step of removing the surface portion of the latent pore-forming material is carried out in the first etching process, and the removal of the porous region of the transition metal oxide film is carried out in the second different etching process. , The method according to the exemplary embodiment 1.

Exemplary Embodiment 3: The step of removing the surface portion of the latent pore-forming material and the step of removing the porous region of the transition metal oxide film are carried out in the same etching process, according to the exemplary embodiment 1. The method described.

Exemplary Embodiment 4: The step of removing the surface portion of the latent pore-forming material and the step of removing the porous region of the transition metal oxide film are performed using one or more plasma etching processes. The method according to the exemplary embodiment 1, 2 or 3.

Illustrative Embodiment 5: The step of forming a transition metal oxide film having a latent pore-forming material in it comprises a co-reactive oxide precursor during the vapor deposition process, exemplary Embodiments 1, 2, 3 or The method according to 4.

Illustrative Embodiment 6: The transition metal oxide film comprises a transition metal oxide material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, niobium oxide, and tantalum oxide. 3, 4 or 5 according to the method.

Illustrative Embodiment 7: The method according to exemplary embodiment 1, 2, 3, 4, 5 or 6, wherein the latent pore-forming material comprises a material selected from the group consisting of aluminum oxide and silicon oxide.

Example 8: The method according to exemplary embodiment 1, 2, 3, 4, 5, 6 or 7, wherein the latent pore-forming material comprises 10 percent to 25 percent of the total volume of the transition metal oxide film. ..

Example 9: The method according to exemplary embodiment 1, 2, 3, 4, 5, 6, 7 or 8, wherein the latent pore-forming material is randomly dispersed in the transition metal oxide film.

Illustrative Embodiment 10: The latent pore-forming material is dispersed as one or more laminated planar layers in the transition metal oxide film, exemplary Embodiment 1, 2, 3, 4, 5, 6, 7 or 8. The method described in.

Illustrative Embodiment 11: In exemplary embodiments 1, 2, 3, 4, 5, 6, 7 or 8, the latent pore-forming material is dispersed as one or more conformal layers in the transition metal oxide film. The method described.

Illustrative Embodiment 12: An integrated circuit structure comprises a plurality of conductive wires in an interstitial dielectric (ILD) layer on a substrate. The hard mask layer is on a plurality of conductive wires, on the top surface of the ILD layer. The hardmask layer includes a first hardmask component that is on the top surface of the plurality of conductive wires and is matched to it, and a second hardmask component that is on the top surface area of the ILD layer and is matched to it. .. The first hard mask component and the second hard mask component have different compositions from each other. The first hard mask component includes a transition metal oxide film having a latent pore-forming material inside. The conductive via is in the hard mask layer and in the opening on one portion of the plurality of conductive wires.

Illustrative Embodiment 13: The transition metal oxide film comprises the transition metal oxide material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, niobium oxide, and tantalum oxide. Integrated circuit structure.

Illustrative Embodiment 14: The latent pore-forming material comprises a material selected from the group consisting of aluminum oxide, gallium oxide, tin oxide, cobalt oxide, nickel oxide, and silicon oxide, according to exemplary embodiment 12 or 13. Integrated circuit structure.

Illustrative Embodiment 15: The integrated circuit structure according to exemplary embodiment 12, 13 or 14, wherein the first hardmask component is restricted to the top surfaces of a plurality of conductive wires.

Illustrative Embodiment 16: The integrated circuit structure according to exemplary embodiment 12, 13 or 14, wherein the first hardmask component extends over a portion of the top surface of the ILD layer.

Illustrative Embodiment 17: The integrated circuit structure according to exemplary embodiment 12, 13, 14, 15 or 16, wherein the portion of the conductive via is on a portion of the second hardmask component of the hardmask layer.

Illustrative Embodiment 18: In exemplary embodiments 12, 13, 14, 15, 16 or 17, the first hardmask component has an uppermost surface that is substantially coplanar with the uppermost surface of the second hardmask component. The integrated circuit structure described.

Illustrative Embodiment 19: An exemplary embodiment 12, 13, 14, 15, 16, 17 or 18 further comprises a second ILD layer above the hardmask layer and the conductive vias are further within the opening of the second ILD layer. The integrated circuit structure described in.

Illustrative Embodiment 20: One of the plurality of conductive wires is coupled to the lower conductive via structure, and the lower conductive via structure is connected to the lower metallization layer of the integrated circuit structure. The integrated circuit structure according to 14, 15, 16, 17, 18 or 19.

Exemplary Embodiment 21: The integrated circuit structure includes a gate stack above the substrate. The first and second conductive trench contacts are on the first and second surfaces of the gate stack, respectively. The first hardmask component is on the top surface of the gate stack and is aligned with it. The second hardmask component is on and aligned with the first and second conductive trench contacts. The first and second hardmask components differ from each other in composition. The first hard mask component includes a transition metal oxide film contained in the latent pore-forming material. The conductive vias are in the first hardmask component and in an opening on a portion of the gate stack.

Illustrative Embodiment 22: The transition metal oxide film comprises the transition metal oxide material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, niobium oxide, and tantalum oxide. Integrated circuit structure.

Illustrative Embodiment 23: The integrated circuit structure of exemplary embodiment 21 or 22, wherein the latent pore-forming material comprises a material selected from the group consisting of aluminum oxide and silicon oxide.

Illustrative Embodiment 24: The integrated circuit structure according to exemplary embodiment 21, 22 or 23, wherein the portion of the conductive via is on a portion of the second hardmask component.

Claims (24)

It is a method of dry etching the film.
At the stage of forming a transition metal oxide film having a latent pore-forming material inside,
A step of removing the surface portion of the latent pore-forming material of the transition metal oxide film to form a porous region of the transition metal oxide film.
A method comprising a step of removing the porous region of the transition metal oxide film. The step of removing the surface portion of the latent pore-forming material is performed in the first etching process, and the removal of the porous region of the transition metal oxide film is performed in a second different etching process. The method according to claim 1. The step of removing the surface portion of the latent pore-forming material and the removal of the porous region of the transition metal oxide film are carried out in the same etching process, according to claim 1. Method. The step of removing the surface portion of the latent pore-forming material and the step of removing the porous region of the transition metal oxide film are performed using one or more plasma etching processes. The method according to any one of claims 1 to 3. The method according to any one of claims 1 to 4, wherein the step of forming the transition metal oxide film having the latent pore-forming material therein includes a co-reactive oxide precursor in the gas phase deposition process. .. The transition metal oxide film according to any one of claims 1 to 5, wherein the transition metal oxide film contains a transition metal oxide material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, niobium oxide, and tantalum oxide. Method. The method of claim 6, wherein the latent pore-forming material comprises a material selected from the group consisting of aluminum oxide, gallium oxide, tin oxide, cobalt oxide, nickel oxide, and silicon oxide. The method according to any one of claims 1 to 7, wherein the latent pore-forming material has 10% to 25% of the total volume of the transition metal oxide film. The method according to any one of claims 1 to 8, wherein the latent pore-forming material is randomly dispersed in the transition metal oxide film. The method according to any one of claims 1 to 9, wherein the latent pore-forming material is dispersed as one or a plurality of laminated plane layers in the transition metal oxide film. The method according to any one of claims 1 to 10, wherein the latent pore-forming material is dispersed as one or a plurality of conformal layers in the transition metal oxide film. It is an integrated circuit structure
Multiple conductive wires in the interlayer dielectric layer (ILD layer) above the substrate,
A hard mask layer on the plurality of conductive wires and on the uppermost surface of the ILD layer, wherein the hard mask layer is on the uppermost surfaces of the plurality of conductive wires. A first hardmask component aligned with the top surface of the line and a second hardmask component above the top surface region of the ILD layer and aligned with the top surface region of the ILD layer. The first hard mask component and the second hard mask component have different compositions from each other, and the first hard mask component includes a hard mask layer including a transition metal oxide film having a latent pore-forming material inside.
An integrated circuit structure including a conductive via in an opening on one portion of the plurality of conductive wires in the hard mask layer. The integrated circuit structure according to claim 12, wherein the transition metal oxide film comprises a transition metal oxide material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, niobium oxide, and tantalum oxide. 13. The integrated circuit structure of claim 13, wherein the latent pore-forming material comprises a material selected from the group consisting of aluminum oxide and silicon oxide. The integrated circuit structure according to any one of claims 12 to 14, wherein the first hard mask component is limited to the uppermost surface of the plurality of conductive wires. The integrated circuit structure according to any one of claims 12 to 15, wherein the first hard mask component extends to the uppermost portion of the ILD layer. The integrated circuit structure according to any one of claims 12 to 16, wherein the conductive via portion is located on the portion of the second hard mask component of the hard mask layer. The integrated circuit structure according to any one of claims 12 to 17, wherein the first hard mask component has an uppermost surface that is substantially the same plane as the uppermost surface of the second hard mask component. The integrated circuit structure according to any one of claims 12 to 18, further comprising a second ILD layer above the hard mask layer, wherein the conductive via is further in an opening of the second ILD layer. 13. The integrated circuit structure described. It is an integrated circuit structure
With the gate stack on the board,
A first conductive trench contact on the first surface of the gate stack and a second conductive trench contact on the second surface.
A first hardmask component that is above the top surface of the gate stack and is aligned with the top surface of the gate stack.
A second hardmask component that is above the first conductive trench contact and the second conductive trench contact and is matched with the first conductive trench contact and the second conductive trench contact, the first hard. The mask component and the second hard mask component have different compositions from each other, and the first hard mask component includes a second hard mask component containing a transition metal oxide film having a latent pore-forming material inside.
An integrated circuit structure comprising a conductive via in an opening on a portion of the gate stack in the first hardmask component. 21. The integrated circuit structure of claim 21, wherein the transition metal oxide film comprises a transition metal oxide material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, niobium oxide, and tantalum oxide. 22. The integrated circuit structure of claim 22, wherein the latent pore-forming material comprises a material selected from the group consisting of aluminum oxide and silicon oxide. The integrated circuit structure according to any one of claims 21 to 23, wherein the conductive via portion is located on the portion of the second hard mask component.

Images