JP3039078B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device.
In respect, in particular, a semiconductor device of high reliability noble metal wire
The present invention relates to a method for manufacturing a semiconductor device having a structure .

[0002]

2. Description of the Related Art In recent VLSIs, multilayer wiring and miniaturization of wiring have been rapidly advanced in order to respond to demands for higher performance, higher density, and higher speed. In addition to three-layer wiring products, four-layer wiring products have begun to be commercialized, and submicron wirings of less than 1.0 μm have begun to be used in various places.

[0003] For such multilayering and miniaturization,
In the former, the flattening of the interlayer insulating film is the key, and in the latter, ensuring the reliability is the key. This multi-layering and miniaturization 2
The technology currently used for the two problems is an interlayer planarization technology that combines an insulating film formed by a plasma-enhanced chemical vapor deposition (hereinafter, referred to as a PCVD method) and a coated and baked film (hereinafter, referred to as an SOG film). And a multilayer wiring technology of a refractory metal and an aluminum alloy.

FIG. 4 (a cross-sectional view of a conventional product) realizes a three-layer wiring using these techniques.
3a to 3f and a stack of Al—Si—Cu 4a to 4c, and the interlayer insulating film is a SiO ₂ film (hereinafter referred to as PS
that iO _2. 5) The structure is such that the SOG films 6a and 6b are sandwiched between 5a to 5d. Here, the through holes for connecting the upper and lower wirings are omitted because they are not related to the gist of the present invention. In the above conventional products, W, Mo, etc. may be used instead of TiN3a to 3f, and further, Al-S
Al-Cu may be used other than i-Cu4a-4c. In FIG. 4, 1 is a silicon substrate, and 2 is a BPSG film.

[0005]

The above prior art is based on the two basic concepts of flattening by the SOG method and extending the life of the wiring by lamination, but these elements themselves have a multilayer structure. The biggest problem is that it has drawbacks that hinder high performance.

First, the SOG method has a problem that it has pattern dependency. That is, the flatness changes due to the density of the wiring pattern. As shown in FIG. 3 to be described later, in a pattern continuous at a certain wiring interval, there is no flatness problem.
As shown in (a diagram for explaining the problems and disadvantages of the conventional product), when there is an isolated pattern 7, the coverage of the wiring is reduced at both ends thereof and at the ends of the equally-spaced continuous pattern 8 (FIG. 5 (see 5a, 9b, 9c).

Naturally, the degree of the reduction in the coverage is related to the thickness of the wiring and the thickness of the coating film, and the smaller the thickness of the wiring and the thicker the coating film, the higher the coverage. Gets better. However, since the film thickness of the wiring is defined by the wiring resistance, it must be set to be equal to or less than the allowable maximum value of the parasitic resistance. Also, if the coating film is formed too thick, it will cause cracks, so that it cannot be made too thick. Sufficient coverage can be obtained with the current three-layer wiring structure.
It is about μm. Furthermore, in order to realize a four-layer structure,
It is necessary to keep the thickness of the wiring up to the third layer at 0.5 μm or less.

Turning now to the conventional wiring itself shown in FIG. 4, TiN3a-3f and Al--Si--Cu4a-4c
The specific resistance of TiN is Al-
Parasitic resistance is significantly higher than that of Si-Cu.
-Si-Cu is determined by the film thickness. And in order to sufficiently secure the effect of extending the wiring life,
The total thickness of the upper and lower TiN layers is required to be about 0.1 to 0.15 μm. Therefore, when a four-layer wiring is realized, Al-Si
The Cu thickness had to be set to 0.35 to 0.4 μm or less.

On the other hand, in a device such as a bipolar VLSI that requires an ultra-high-speed operation, this point is fatal. In short, it is not possible to increase the wiring film thickness in order to reduce the parasitic resistance. For example, for a 0.8 μm wide wiring
Although the thickness is required to be about 1.0 μm in terms of thickness, as described above, it cannot be realized at all by the prior art. Further, when the thickness of the high melting point metal covering the wiring is large, the wiring interval is reduced accordingly, and there is a disadvantage that the yield is reduced by particles (for example, the wiring is short-circuited by metal particles).

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device which solves the above problems and disadvantages. It is an object of the present invention to provide a method of manufacturing a semiconductor device which solves the problem of coverage and reliability. In addition, the thickness of the refractory metal film
Thinner, and then increase the wire spacing to
To provide a method of manufacturing a semiconductor device which is less affected by
With the goal.

[0011]

SUMMARY OF THE INVENTION The present invention provides a semiconductor device comprising:
A method for manufacturing a body device, which is manufactured by the manufacturing method of the present invention.
In a semiconductor device to be formed, a noble metal wiring (for example, Au or Ag) whose periphery is covered with a high melting point metal film (for example, a film of Ti, W, Mo, or the like) is formed on a semiconductor substrate on which element formation is completed.
And a silicon oxide film (Si) formed between the noble metal wires by a liquid phase growth method.
The gist is a method for manufacturing a semiconductor device provided with an O ₂ film. The method of manufacturing a semiconductor device of the present invention, (1) element formed of the terminated SiO ₂ based insulating film on a semiconductor board was
When the step of the first refractory metal film and the noble metal film is deposited sequentially laminated product <br/> layer film, (2) forming a resist film on the laminated film, the resist film as a mask Forming a noble metal plating film on the laminated film by a plating method; (3) removing the first refractory metal film and the noble metal film from the exposed laminated film after removing the resist film; to process, (4) a step of grown on the precious metal plating film surface of the second refractory metal film is selected択的, covering the upper and side surfaces of the precious metal plating film, a silicon oxide (5) liquid phase growth method The film is made of the SiO2
Formed on the base insulating film, and at the same time, the thickness of the silicon oxide film
Liquid phase on the top surface of the second refractory metal film.
Forming a silicon oxide film by a long method , (6) a table of the semiconductor substrate on which the silicon oxide film is formed.
Forming a coating film covering the silicon oxide film on the surface;
(7) the step of smoothing the surface of the semiconductor substrate, (7) the etching rate of the coating film and the silicon oxide
Under the condition that the etching rate of the film is the same,
Etch back the film and the silicon oxide film
No second refractory metal film covering the upper surface of the metal plating film
A step of performing until the upper surface of the noble metal plating film exposed (8), third KoToru
It is intended to growing a point metal film selectively, the production method of the semi-conductor device you <br/> comprising a a a gist.

The present invention will be described in more detail. The present invention is characterized in that it has been changed from an Al-based material, which has been conventionally used as a wiring material, to a wiring made of a noble metal material and that selective growth of SiO ₂ is used. As a result, the above-mentioned object is achieved, that is, a wiring structure having extremely excellent flatness and low electric resistance and excellent reliability can be realized. That is, the present invention provides, as a wiring material,
By using Au or Ag whose specific resistance is smaller by 20 to 40% than that of Al-based alloys and whose wiring life is longer than several tens of times,
This solves the problem of flattening.

[0013]

Next, an embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a cross-sectional view of a manufacturing method according to the present invention.
FIG. 4 is a diagram for explaining a semiconductor device to be manufactured . Also,
FIG. 2 is a diagram for explaining a method of manufacturing the semiconductor device shown in FIG. 1 , and FIG. 3 is a method of manufacturing a semiconductor device according to the present invention .
It is a figure for explaining the Example of .

A semiconductor manufactured by the manufacturing method of the present invention.
The device will be specifically described with reference to FIG. 1 (a cross-sectional view of a semiconductor chip). The device is formed by forming an Au film (Au wiring) 13a on a BPSG film 2 on a silicon substrate 1 on which elements have been formed.
Between the periphery of ~13d coated with W film 14a~14d wiring is made of the structure which is filled with liquid phase growth oxide film LPD-SiO ₂ film 15a to 15c. In FIG. 1, 10a to 10d are Ti, and 16a to 16c are P-SiO ₂ films.

Example 1 Next, a method for manufacturing the semiconductor device will be specifically described with reference to FIG. First,
As shown in step A of FIG.
After a Ti film 10a and an Au film 11 are respectively deposited on the G film 2 by about 500 angstroms by a sputtering method, a resist film 12 is formed by a usual photolithography technique, and electrolytic plating is performed using the resist film 12 as a mask. Form 13a.

Next, after the resist film 12 is removed by O ₂ plasma, the Au film 11 is removed by an ion-scilling method, and subsequently, a T ion is removed by a reactive ion etching method.
The i-film 10a is removed by etching, and the wiring is separated as shown in step B in FIG.
Growing 14a by about 1000 angstroms. Here, in order to obtain good selectivity, after the above-described dry etching is completed, a pretreatment is performed for several seconds using an aqueous solution of potassium iodide having a concentration of several percent, and 25% using a SiH ₄ reduction method of WF _6.
W may be grown under the condition of 0 ° C. to 300 ° C.

Next, as shown in the step C of the figure, LPD-SiO ₂ 15a is selectively grown by a liquid phase growth method, a region other than the wiring is filled, and P-SiO ₂ 16a is grown on the entire surface. Here, the liquid phase oxide film growth method is described, for example, by H. Nagayama and the like in the Journal of Electrochemical Society: Liquid State Science and Technology (Jornal of Electorochemic).
al Society: SOLID-STATESCIENCE AND TECHNOLOGY) 135
Volume No. 8, pages 2013-2016.

The principle is that in the following formula (1), SiO
₂ is formed, and when boric acid is added thereto,
As shown in equation (2), HF is consumed, a supersaturated state of SiO ₂ is realized, and SiO ₂ is deposited. Equation _{(1) H 2 SiF 6 +} 2H 2 O → 6HF + SiO 2 H 2 SiF 6 + 2H 2 O ← 6HF + SiO 2 Equation _{(2) H 3 BO 3 +} 4HF → BF 4 - + H 3 O + + 2H 2 O H 3 BO 3 + 4HF ← BF ₄ ⁻ + H ₃ O ⁺ + 2H ₂ O LPD-SiO ₂ deposited here has selectivity depending on the material, and grows very well on an SiO ₂ -based isolated film such as BPSG, whereas W Etc. have the property of being extremely difficult to grow. For example, this selectivity is
There is a relationship such as W = Mo>Au> Ti. This manufacturing method
Oite law, there the Au film surface This is why coated with W film, and, in order to ensure the selectivity of LPD-SiO _2, for example, in the case of _LPD-SiO 2 1 [mu] m, Some 1000 Å Is enough.

The first layer is completed as described above, but LPD-SiO ₂ is not formed on the wiring.
Since the film formation proceeds at a rate controlled by the surface reaction and there is no pattern dependence, complete planarization is realized, and there is no adverse effect on the formation of the second and subsequent layers. By repeating this, multilayer wiring can be easily achieved, and the wiring film thickness can be freely set.
Can be sufficiently satisfied.

( Embodiment ) Next, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG.
A description will be given based on (a cross-sectional view in the order of steps of a semiconductor chip).
Describing the manufacturing method of this embodiment with the same comparison of the production method of FIG. 2, in the manufacturing method of FIG. 2, W film 14a
Has a thickness of about 1000 angstroms, and such a thickness is required. With this film thickness, it means that the wiring width is expanded by 0.1 μm on one side, and the wiring interval is 0.2 μm.
m narrower. Products having extremely strict design rules have a drawback that the wiring interval is less than 0.5 μm, and the yield is significantly reduced by particles.

As a countermeasure, it is effective to make the W film thin, but on the other hand, the selectivity of LPD-SiO ₂ is reduced. The manufacturing method of FIG. 2 covers this point as described below. Manufacturing
When the W film 14a is set to about 250 angstroms in the step B in FIG. 2 of the method and the LPD-SiO ₂ film is grown to 1 μm, the L film is formed on the W film as shown in the step A in FIG.
PD-SiO ₂ 17 resulting in growth. If left as is, it will lead to poor flatness and poor through-hole opening,
This needs to be removed.

Therefore, in the manufacturing method of FIG. 2 , first,
As shown in step A of FIG. 3, after the SOD film 18 is applied and the surface is smoothed, the reactive ion is applied under the condition that the etching rates of the SOG film 18 and the LPD-SiO ₂ film 17 become the same. The entire surface is etched back by an etching method. For example, it is preferable to use a mixed gas plasma of C ₂ F ₆ , CHF ₃ , O ₂ and He. In this gas system,
Since the W film is also etched, the non-selective LPD-SiO ₂
Is completely etched, as shown in FIG.
The W film on the wiring 13a also disappears.

[0023] Therefore, subsequently, after W film was about 100 to 200 Angstroms grown on Au13a by selective growth conditions described above, the entire surface is grown P-SiO _2, thereby, the manufacturing method of FIG. 2 A structure having the same structure as in step C of FIG. 2 is obtained. For the manufacturing method of FIG 2, the reason for growing again W film on the Au film 13a is completely free from the viewpoint of the selectivity of LPD -SiO _2, Au film itself P-
Since the adhesion to SiO ₂ is extremely poor, it is necessary to grow thinly in order to prevent peeling.

In the above-described manufacturing method of the present invention shown in FIG. 3 , the Au film and the W film have been described, but they can be replaced with an Ag film and a Mo film, respectively. In particular, in the case of the Ag film, the specific resistance is lower by about 30% than that of the Au film, so that the electric characteristics are more advantageous.

As described in detail above, the present invention relates to paragraph 0
02, the thickness of the refractory metal covering the wiring is large
And the wiring spacing becomes smaller by that amount,
(For example, wiring by metal particles)
Short) becomes noticeable.
Wear. For this reason, the present invention relates to the thickness of the refractory metal covering the wiring.
Deterioration of selectivity of silicon oxide film by liquid phase growth method
Until it ends up, and then increase the wire spacing
To reduce the effects of particles.
I do. However, precious metal plating
Silicon oxide is also applied to the upper surface of the refractory metal film that covers the upper surface of the film.
The film grows thinly. To remove this,
A step of performing etch back using a coating film is required.

[0026]

According to the present invention, as described in detail above, the use of a noble metal material instead of the conventionally used Al-based material and the use of selective growth of SiO ₂ have extremely excellent flatness. Moreover, there is an effect that a semiconductor device having a wiring structure with low electric resistance and excellent reliability can be manufactured . According to the present invention, there is a merit that has a great effect on commercialization of fine multilayer wiring. Further, the invention of the present application provides the thickness of the refractory metal covering the wiring.
If the wire is thicker, the wiring spacing will be reduced accordingly,
Decrease in yield due to particles (for example, due to metal particles)
Short-circuit of the wiring)
Solvable. For this reason, the present invention has a high melting point covering the wiring.
Selection of silicon oxide film by liquid phase growth method with metal thickness
Thinner until the performance is reduced, and the wiring spacing
It is said that it is increased to reduce the effect of particles
It works. However, due to reduced selectivity,
The upper surface of the refractory metal film that covers the upper surface of the
Con oxide film grows thinly.
Requires a process of performing etch-back using a coating film.
You.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip showing a semiconductor device manufactured according to the present invention.

FIG. 2 is a cross-sectional view in a process order in main manufacturing steps showing a method of manufacturing the semiconductor device in FIG . 1 ;

FIG. 3 is a cross-sectional view in a process order in main manufacturing steps showing an embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view of a conventional semiconductor chip.

FIG. 5 is a diagram for explaining problems and disadvantages of a conventional product.

[Explanation of symbols]

1 silicon substrate 2 BPSG film 3a~3f TiN 4a~4c Al-Si-Cu 5a~5d P-SiO 2 6a, 6b SOG film 7 isolated pattern portion 8 equally spaced continuous pattern 9a~9c coverage reduction unit 10 a to 10 d Ti film 11 Au film 12 resist film 13 a to 13 d Au film 14a to 14d W film 15a to 15c LPD-SiO ₂ film 16 a to 16 c P-SiO ₂ film 17 LPD-SiO ₂ film 18 SOG film

Claims (5)

(57) [Claims] 1. A (1) S in finished semiconductor base plate element forming
The iO ₂ -based insulating film, the first refractory metal film, and the noble metal film are arranged in this order.
The step of depositing the next stacked laminated film, (2) the after forming a resist film on the laminated film, the step of forming a noble metal plating layer by plating on the laminated film using the resist film as a mask, (3 ) After the resist film is removed, out of the exposed the laminated film, the step of removing said noble metal layer and said first refractory metal film, (4) a second refractory metal film is selected択的the noble metal plating layer surface grown, the step of covering the upper and side surfaces of the precious metal plating film, a silicon oxide film (5) liquid phase growth method, the SiO ₂
Formed on the base insulating film, and at the same time, the thickness of the silicon oxide film
Liquid phase on the top surface of the second refractory metal film.
Forming a silicon oxide film by a long method , (6) a table of the semiconductor substrate on which the silicon oxide film is formed.
Forming a coating film covering the silicon oxide film on the surface;
(7) the step of smoothing the surface of the semiconductor substrate, (7) the etching rate of the coating film and the silicon oxide
Under the condition that the etching rate of the film is the same,
Etch back the film and the silicon oxide film
No second refractory metal film covering the upper surface of the metal plating film
A step of performing until the upper surface of the noble metal plating film exposed (8), third KoToru
Method of manufacturing a semi-conductor device you comprising the steps of growing a point metal film selectively. 2. The method according to claim 1, wherein the first refractory metal film is titanium or titanium tungsten. 3. The method according to claim 1, wherein the noble metal film is made of gold or silver. 4. The method according to claim 1, wherein the noble metal plating film is made of gold or silver. 5. The method according to claim 1, wherein the second refractory metal film is made of tungsten or molybdenum.