JPH11340227A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the device, and also to provide a technique which can improve adhesion between a copper-based wiring and a barrier layer, suppress voids generated in the copper-based wiring, suppress diffusion of copper from the copper-based wiring, and suppress increase in the effective resistance of the copper-based wiring. SOLUTION: A barrier layer covering at least one of upper, lower and side surfaces of a Cu-embedded wiring 16A consists of two laminated barrier films of different materials, e.g. a first barrier film 14 of Si and a second barrier film 15 of Ta. An amorphous layer 18 of Si and Ta as constituent elements is interposed between the first and second films 14 and 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which copper or a copper alloy is used as a material for circuit wiring, and the wiring is insulated by an insulating layer made of a material containing silicon oxide, and a method of manufacturing the same.

[0002] At present, further miniaturization of semiconductor devices is progressing, and accordingly, the width of wiring is also reduced. As a means for avoiding this, a semiconductor device using copper or a copper alloy as a material for circuit wiring has been realized.

[0003] However, since various problems are derived from the use of the copper-based material, the present invention discloses one means for solving this problem and contributes to practical use.

[0004]

2. Description of the Related Art Aluminum or an aluminum alloy has been widely used as a material for circuit wiring in a semiconductor device. However, as the semiconductor device becomes more highly integrated, the wiring pitch becomes finer and the wiring becomes more difficult. The width is also required to be 0.3 [μm] or less.

In such a case, a problem of naturally increasing the sheet resistance occurs. To solve the problem, the height of the wiring is increased. Due to the increase, the wiring delay time increases, and there is a concern that the circuit response speed may decrease.In addition, when the circuit wiring is miniaturized, the wiring current density increases, and the wiring life decreases due to electromigration. Is also a concern.

In order to solve the above problems, it has been attempted to use copper or a copper alloy having a lower electric resistivity and a higher electromigration resistance as a wiring material as compared with an aluminum-based wiring material. Although it has been gained, new problems have arisen with it.

In a semiconductor device using an aluminum-based wiring material, silicon oxide has been frequently used as a material for holding the wiring and insulating between the wirings. Various problems occur when wiring materials are used, for example, copper is inferior to aluminum in terms of oxidation resistance and corrosion resistance, and diffuses at a high speed in oxides.

Accordingly, a material having high oxidation resistance and capable of acting as a barrier for suppressing intrusion of copper into the oxide, for example, a nitride such as titanium nitride, tungsten nitride or tantalum nitride, or a material such as tantalum or tungsten It is necessary to cover the surface of the copper-based wiring with this layer.

However, the barrier layer as described above can exhibit a barrier function if it has a sufficient thickness, but has an effect of promoting the diffusion of copper through crystal grain boundaries when it is thin.

Therefore, attempts have been made to suppress the diffusion of copper in a thin layer by using a barrier material having an amorphous structure having no crystal grain boundaries.
No. 33927 ").

By the way, since it is very difficult to form a fine wiring using a copper-based material by applying an etching method due to an etchant, first, a groove or a groove is formed in an interlayer insulating layer. A hole is formed, a barrier layer is deposited on the bottom and side walls of the groove or hole, copper is deposited therein to fill the groove or hole, and then the copper deposited outside the groove or outside the hole is chemically mechanically polished. (Chemical mechanical
A wiring or a conductive plug is formed by removing by a polishing (CMP) method (if necessary, “Proceedings of 8th”).
Int'l IEEE VLSI Multilevel
l Interconnect Conferenc
e, p. 144, 1991 ").

FIG. 6 is a cutaway side view of a main part showing a semiconductor device in the middle of a process for explaining a conventional technique.

6 (A) 6- (1) An insulating layer 3 is formed on a base insulating layer 1 covering a semiconductor substrate (not shown) via an etching stop layer 2. The insulating layer 3 plays a role of insulating and supporting the wiring.

6- (2) A groove (or hole) 3A is formed in a portion of the insulating layer 3 where a wiring is to be formed.

6- (3) The barrier layer 8 is formed on the entire surface including the inside of the groove 3A.

6 (B) 6- (4) A copper-based material layer such as copper or a copper alloy is formed on the barrier layer 8 to fill the groove 3A.

6- (6) Grinding from the surface is stopped when the insulating layer 3 is exposed, and the wiring 7 made of a copper-based material is completed.

As is apparent from the above description, the barrier layer is required to be formed in a groove (or a hole) having a high aspect by applying a film forming / deposition technique having good step coverage.

When a nitride such as tungsten or tantalum is used for the barrier film covering the copper-based wiring, these compounds are extremely stable and form a reaction layer with the copper-based wiring and the surrounding oxide insulating layer. Therefore, when various stresses are applied in a later step, there is a problem that the interface is easily separated at the interface between the insulating layer and the barrier layer or at the interface between the copper-based wiring and the barrier layer.

In addition, since the adhesion between the copper-based wiring and the barrier layer is weak, if a heat treatment for stabilizing the grain boundaries is performed after the copper-based wiring material layer is formed, the copper-based wiring material layer may be interposed through the interface. There is also a problem that atoms easily move, and voids easily accumulate at the corners of the groove or at the triple point of the grain boundary.

Further, when titanium or titanium nitride is used so as to have strong adhesion to both the oxide insulating layer and the copper-based wiring material, titanium forms an extremely stable oxide, Although strong adhesion with the layer can be maintained, a large amount of oxygen is also present at the columnar polycrystalline grain boundaries, and copper reacts with the oxygen to diffuse through the barrier layer and cause the oxide in the oxide insulating layer. There is a problem that it is easy to slip out.

Further, when a ternary alloy of titanium, silicon, and nitrogen, a ternary alloy of tantalum, silicon, and nitrogen, and a ternary alloy of tungsten, silicon, and nitrogen are used, an amorphous structure can be formed in a specific composition range. When this is used as a barrier layer material, it works effectively as a diffusion barrier, but has a high specific resistivity,
It is necessary to control the composition in order to increase the effective resistance of the wiring, to maintain the amorphous structure stably, and to form an extremely thin film uniformly in a groove or hole with a large aspect with high step coverage. There are technical problems such as the need to film.

[0023]

SUMMARY OF THE INVENTION The adhesion between the copper-based wiring and the barrier layer is improved, the voids generated in the copper-based wiring are suppressed, and the diffusion of copper from the copper-based wiring is suppressed. To provide a technique for suppressing an increase in effective resistance in the semiconductor device.

[0024]

According to the present invention, a barrier layer for covering at least one of the upper and lower surfaces and side surfaces of a wiring is constituted by a laminate of two types of material layers, and between the two types of material layers. Is based on interposing an amorphous layer made of the same two kinds of materials.

FIG. 1 is a sectional side view showing a semiconductor device in the middle of a process for explaining the principle of the present invention.

1 (A) 1- (1) An insulating layer 3 is formed on a base insulating layer 1 covering a semiconductor substrate (not shown) with an etching stop layer 2 interposed therebetween. The insulating layer 3 plays a role of insulating and supporting the wiring.

1- (2) A groove (or hole) 3A is formed in a portion of the insulating layer 3 where a wiring is to be formed.

1- (3) A laminate comprising the first barrier layer 4 and the second barrier layer 5 including the inside of the groove 3A is formed.

Referring to FIG. 1B, 1- (4) For example, a material forming the second barrier layer 5 between the second barrier layer 5 and the first barrier layer 4 by performing a heat treatment, An amorphous layer 6 made of a material constituting one barrier layer 4 is formed.

1- (5) A copper-based material layer such as copper or a copper alloy is formed on the second barrier layer 5 to fill the groove 3A.

1- (6) Grinding from the surface is stopped when the insulating layer 3 is exposed, and the wiring 7 made of a copper-based material is completed.

In the wiring structure formed as described above, the barrier function against the diffusion of copper is sufficiently large, the adhesion between the wiring 7 and the insulating layer 3 is very good, and the electromigration resistance is also high. high.

In this wiring structure, the diffusion of copper into the insulating layer 3 is suppressed by the amorphous layer 6 at the interface between the second barrier layer 5 and the first barrier layer 4.

In general, when a polycrystalline layer is used as a barrier layer, it is known that the diffusion of copper proceeds along the grain boundary. However, if the second barrier layer 5 and the first barrier layer 4
Is composed of polycrystalline grains, the second barrier layer 5
Further, the diffusion of copper is suppressed by the amorphous layer 6 generated by the interdiffusion of the first barrier layer 4.

It is known that the amorphous layer 6 is generated when the interdiffusion speed between the second barrier layer 5 and the first barrier layer 4 which are crystalline barrier layers is largely different from each other. The thickness can be controlled depending on the temperature and time of the heat treatment. Therefore, if the first barrier layer 4 and the second barrier layer 5 are in contact with each other in the groove 3A forming the wiring 7, An amorphous layer 6 having a substantially uniform thickness can be generated.

In addition, as the material of the first barrier layer 4, a metal having a higher oxide generation energy than that of the insulating layer 3 made of oxide is used. Generating an oxide of the material of the first barrier layer 4;
Strong adhesion can be generated between the insulating layer 3 and the first barrier layer 4.

Furthermore, by using a metal that does not form an alloy or a solid solution with copper as a material of the second barrier layer 5,
The resistance increase of the wiring 7 caused by the second barrier layer 5 can be suppressed, and the constituent elements of the second barrier layer 5 form an alloy with copper, and the generated energy is reduced by the first barrier. By making the energy of the alloy generated between the layer 4 and the second barrier layer 5 smaller than that of the alloy, good adhesion between the wiring 7 and the barrier layer 5 can be suppressed while suppressing an increase in the resistance of the wiring 7. Nature can be realized.

As described above, in the semiconductor device and the method of manufacturing the same according to the present invention, (1) at least one of the upper and lower surfaces and side surfaces of a wiring made of copper or a copper alloy (for example, a buried Cu wiring 16A) is covered. The barrier layer is formed of a laminate of a first barrier layer (for example, a first barrier layer 14 made of Si) and a second barrier layer (for example, a second barrier layer 15 made of Ta) made of different materials; In addition, an amorphous layer (for example, a Si-Ta amorphous layer 18) made of a constituent element of each material is provided between the first barrier layer and the second barrier layer.
Is characterized by intervening, or

(2) In the above (1), the wiring made of copper or copper alloy covered with the barrier layer is insulated by the interlayer insulating layer containing Si oxide (for example, the interlayer insulating layer 13 made of SiO ₂ ). Or that it is

(3) In the above (1) or (2),
The constituent elements of the different materials of the first barrier layer and the second barrier layer are different from each other in diffusion speed, or

(4) In any one of the above (1) to (3), the oxide forming energy of the material forming the first barrier layer in contact with the interlayer insulating layer is the oxide forming energy of the interlayer insulating film. Characterized by being equal to or greater than the energy, or

(5) In any one of the above (1) to (4), the first barrier layer in contact with the interlayer insulating layer may be made of Si, T
characterized by containing at least one element of the elements i, Zr and Hf, or

(6) In any one of the above (1) to (5), the constituent element of the second barrier layer in contact with the wiring made of copper or copper alloy does not form an alloy or a solid solution with copper. Characterized by the presence of, or

(7) In any one of the above (1) to (6), the second barrier layer in contact with the wiring made of copper or a copper alloy is made of at least one of the elements Ta, Ru, W and Os.
Characterized in that it contains different types of elements, or

(8) In any one of the above (1) to (5), the constituent element of the second barrier layer in contact with the wiring made of copper or copper alloy forms an alloy with copper, and Characterized in that the generated energy is small compared to the generated energy of the alloy generated between the first barrier layer and the second barrier layer, or

(9) In the above (8), the second barrier layer in contact with the wiring made of copper or copper alloy is made of Ti, Y, Z
characterized in that it contains at least one element among the elements of r, Al and Si, or

(10) A first layer for covering at least one of the upper and lower surfaces and side surfaces of a wiring made of copper or a copper alloy (for example, a Cu embedded wiring 16A) on an insulating layer (for example, an interlayer insulating film 13 made of SiO ₂ ). A barrier layer (for example, the first barrier layer 14 made of Si) and a second barrier layer made of a material different from the first barrier layer (for example, the second barrier layer 14 made of Ta)
And a heat treatment is performed to form an interface between the first barrier layer and the second barrier layer, and the first barrier layer and the second barrier layer are composed of the constituent elements of the first and second barrier layers. Amorphous layer (for example, Si-Ta amorphous layer 1)
And 8) generating a).

(11) In the above (10), an amorphous layer composed of a constituent element of the first barrier layer and a constituent element of the second barrier layer is provided at an interface between the first barrier layer and the second barrier layer. Or forming a wiring made of copper or a copper alloy on the second barrier layer after performing a heat treatment to generate

(12) A first for covering at least one of the upper and lower surfaces and side surfaces of the wiring made of copper or copper alloy on the insulating layer.
A step of sequentially laminating a second barrier layer made of a material different from that of the first barrier layer and a second barrier layer made of a material different from that of the first barrier layer, and forming a wiring made of copper or a copper alloy on the second barrier layer and then performing a heat treatment. Forming an amorphous layer composed of a constituent element of the first barrier layer and a constituent element of the second barrier layer at an interface between the first barrier layer and the second barrier layer. Or

(13) In any one of the above (10) to (12), the constituent elements of the first barrier layer and the second barrier may be provided at the interface between the first barrier layer and the second barrier layer. It is characterized in that the temperature of the heat treatment for forming the amorphous layer composed of the constituent elements of the layer is lower than the temperature at which the first barrier layer and the second barrier layer react to form a stable alloy.

According to the wiring structure employing the above means, the adhesion between the copper-based wiring and the insulating layer via the barrier layer is extremely good, and the grain boundary in the copper-based wiring is stabilized. No voids are generated even if the heat treatment is performed, and the diffusion of copper from the copper-based wiring is favorably suppressed by the presence of the amorphous layer in the barrier layer. Thus, there is no problem that the effective resistance of the copper-based wiring increases, and the electromigration resistance is sufficiently high.

[0052]

2 to 5 are cutaway side views of a main part of a semiconductor device in a process step for explaining an embodiment of the present invention. This will be described with reference to the drawings.

2 (A) 2- (1) For example, chemical vapor deposition (Si) on a Si semiconductor substrate (not shown).
n: CVD) is applied to the insulating layer 11 made of SiO ₂ having a thickness of, for example, 1 [μm], for example, by applying the CVD method to a thickness of 50 [nm]. Etch stop layer 12 of SiN, thickness 600
An interlayer insulating layer 13 of [nm] SiO ₂ is formed.

The interlayer insulating layer 13 is made of FSG (fluorine doped silicon) in addition to SiO _2.
cat glass, HSQ (hydrogen)
silsesquioxane), FSQ (fluor
o silsesquioxane) may be used.

FIG. 2 (B) 2- (2) The resist process in the lithography technique and the application of the plasma etching method make
Etching is performed on a portion of the interlayer insulating film 13 made of iO ₂ where a wiring is to be formed, thereby forming a groove (or hole) 13A having an opening width W of 0.3 μm.

The main data when performing this plasma etching is as follows. Applicable equipment: Inductively coupled plasma etching equipment Plasma frequency: 13.56 [MHz] Power: 1.2 [kW] Degree of vacuum: 10 [mTorr] Etching gas: mixed gas of C ₄ F ₈ and H ₂ Total gas Flow rate: 40 [sccm]

3 (A) 3- (1) First barrier layer made of polycrystalline Si having a thickness of 20 [nm] over the entire surface including the inside of groove 13A by applying the plasma CVD method. 14 is formed. In addition, the first barrier layer 1
4 may be an amorphous Si layer.

The main data obtained when performing the plasma CVD is as follows. Substrate temperature: 350 [° C] Source gas: monosilane (SiH ₄ ) Flow rate: 1 [ccm] Pressure: 100 [mTorr] High frequency power: 30 [W] Deposition rate: 5 [nm] / 20 [min]

See FIG. 3B. 3- (2) Ionized metal plasma
By applying the lplasma (IMP) method,
A second barrier layer 15 made of Ta having a thickness of 40 [nm] and a specific resistance of 150 [μΩcm] is formed on the entire surface of the first barrier layer 14.

The main data when performing this ionized metal plasma is as follows. Equipment used: DC magnetron sputtering equipment High frequency power: 6 [kW] to 8 [kW] Substrate temperature: 300 [° C]

When the ionized metal plasma method is performed, the width W is about 0.3 μm and the depth is 0.6 μm.
In the groove 13A, the width W is exactly 0.3 [μm] −20 × 2 [nm] obtained by subtracting the thickness of the first barrier layer 14, and the depth is the thickness of the first barrier layer 14. 0.6 [μm] minus
A thickness of 40 [n] is uniformly formed in the groove 13A of 20 [nm].
m], the second barrier layer 15 made of Ta can be formed.

In order to form the second barrier layer 15 in a groove or a hole having a larger aspect, it is better to use the CVD method.

Referring to FIG. 4A, 4- (1) the raw material is Cu (hfac) VTMS, and the base temperature is 200.
By applying a CVD method at [° C.], a buried layer 16 made of Cu and having a thickness of 50 [nm] is formed on the second barrier layer 15. The buried layer 16 is a seed layer for forming the Cu buried layer 16 thick by electrolytic plating. Here, Cu (hfac) VT
MS is, "Copper from H exa f luo
ro a cetyl a cetonato C opper
(1) V inyl t ri m ethyl s ilan
e ".

4- (2) By applying the electrolytic plating method, the buried layer 16 of Cu is formed so as to have a thickness of 1.5 μm on a flat surface, so that the groove 13A is formed. It is completely buried and almost flat over the entire surface.

The main data relating to the plating solution used in performing the electrolytic plating is as follows. Sulfuric acid Cu: 76 g / l Sulfuric acid: 180 g / l Chloride ion: 50 mg / l Additive: 5 ml / l

4 (B) 4- (3) By applying the CMP method, the surface of the Cu buried layer 16 is polished to form an insulating layer 13 outside the groove 13A.
Stop polishing when appears.

For this polishing, a standard slurry and pad manufactured by Rodale were used, and the polishing pressure was 50 PSI.
The polishing rate was 500 [nm / min].

As a result, the Cu buried layer 16 and the second
The barrier layer 15 and the first barrier layer 14 are removed except for those existing in the groove 13A.
Is formed.

Referring to FIG. 5, 5- (1) A cover film 17 made of SiN having a thickness of 50 [nm] is formed on the entire surface by applying the plasma CVD method.

5- (2) In an atmosphere of hydrogen + nitrogen, the temperature is set to 400 ° C.
The final heat treatment is performed at 450 ° C. for 30 minutes.

In this heat treatment, the temperature is sufficiently lower than the lower limit of the solid phase reaction temperature between Si and Ta, so that the first barrier layer 1
At the interface between 4 and the second barrier layer 15, an Si-Ta amorphous layer 18 was generated, and its thickness was 6 [nm] under the heat treatment conditions.

The present invention is not limited to the above embodiment,
Without departing from the requirements stated in the claims,
Many other modifications can be implemented.

For example, electrolytic plating is applied as a technique for forming a thick buried layer 16 of Cu to fill the groove 13A. In addition to this, the Cu layer is made thicker by applying long throw sputtering. About 1 [μm] and heat-treated in a hydrogen atmosphere to obtain Cu
Can be reflowed and embedded in the groove 13A, and the first barrier layer 14 and the second barrier layer 15
a, the temperature at the time of reflow is 500
Below [° C.], there is no adverse effect on the characteristics of the wiring structure.

In the above embodiment, the heat treatment for forming the amorphous layer 18 is performed as the final heat treatment step. However, the heat treatment is performed, for example, in the second barrier layer 15 described in the step 3- (2). Immediately after the formation of
This may be performed at any time, such as immediately after the Cu buried layer 16 described in (2) is formed thick, or immediately after the Cu buried layer 16 is polished in Step 4- (3) to form the Cu buried wiring 16A.

[0075]

In the semiconductor device and the method of manufacturing the same according to the present invention, the first barrier layer is made of a different material, wherein the barrier layers covering at least one of the upper and lower surfaces and the side surfaces of the wiring made of copper or copper alloy are different from each other. And an amorphous layer made of a constituent element of each material is interposed between the first barrier layer and the second barrier layer.

By adopting the above configuration, the adhesion between the copper-based wiring and the insulating layer via the barrier layer is extremely good.
Also, even if heat treatment for stabilizing the grain boundaries in the copper-based wiring is performed, no voids are generated, and the diffusion of copper from the copper-based wiring depends on the presence of the amorphous layer in the barrier layer. It is well suppressed, and there is no problem that the effective resistance of the copper-based wiring increases due to the presence of the barrier layer, and the electromigration resistance is sufficiently high.

[Brief description of the drawings]

FIG. 1 is a fragmentary side view showing a semiconductor device in the middle of a process for explaining the principle of the present invention.

FIG. 2 is a fragmentary side view showing a semiconductor device at a key step in the process for describing one embodiment of the present invention.

FIG. 3 is a fragmentary sectional side view showing a semiconductor device in a process key point for describing an embodiment of the present invention;

FIG. 4 is a fragmentary sectional side view showing a semiconductor device at a key point in a process for describing one embodiment of the present invention;

FIG. 5 is a fragmentary sectional side view showing a semiconductor device in a process key point for describing one embodiment of the present invention.

FIG. 6 is a fragmentary side view showing a semiconductor device in the middle of a process for explaining a conventional technique.

[Explanation of symbols]

 Reference Signs List 11 insulating layer 12 etching stop layer 13 interlayer insulating layer 13A groove (or hole) 14 first barrier layer 15 second barrier layer 16 Cu buried layer 16A Cu buried wiring 17 cover film 18 amorphous layer

Claims (13)

[Claims] A barrier layer covering at least one of upper and lower surfaces and side surfaces of a wiring made of copper or a copper alloy is formed of a laminate of a first barrier layer and a second barrier layer made of different materials, respectively. A semiconductor device, wherein an amorphous layer made of a constituent element of each material is interposed between the first barrier layer and the second barrier layer. 2. The semiconductor device according to claim 1, wherein the wiring made of copper or copper alloy covered with the barrier layer is insulated by an interlayer insulating layer containing Si oxide. 3. The semiconductor device according to claim 1, wherein constituent elements of different materials of the first barrier layer and the second barrier layer are different from each other in diffusion speed. . 4. The method according to claim 1, wherein the oxide forming energy of the material forming the first barrier layer in contact with the interlayer insulating layer is equal to or larger than the oxide forming energy of the interlayer insulating film. 2. The semiconductor device according to claim 1. 5. The method according to claim 1, wherein the first barrier layer in contact with the interlayer insulating layer is made of S
5. The method according to claim 1, wherein at least one of the elements i, Ti, Zr, and Hf is included.
13. The semiconductor device according to claim 1. 6. The element according to claim 1, wherein the constituent element of the second barrier layer in contact with the wiring made of copper or copper alloy does not form an alloy or a solid solution with copper. Semiconductor device. 7. The semiconductor device according to claim 1, wherein the second barrier layer in contact with the wiring made of copper or copper alloy contains at least one of Ta, Ru, W, and Os.
The semiconductor device according to any one of the above items. 8. An element constituting a second barrier layer in contact with a wiring made of copper or a copper alloy forms an alloy with copper, and the generated energy is between a first barrier layer and a second barrier layer. 6. The semiconductor device according to claim 1, wherein the energy is smaller than the energy of the alloy generated in said step. 9. The method according to claim 8, wherein the second barrier layer in contact with the wiring made of copper or copper alloy contains at least one of Ti, Y, Zr, Al and Si.
13. The semiconductor device according to claim 1. 10. A first barrier layer for covering at least one of upper and lower surfaces and side surfaces of a wiring made of copper or a copper alloy on an insulating layer, and a second barrier layer made of a material different from the first barrier layer. Are sequentially laminated, and a first heat treatment is performed.
A step of forming an amorphous layer composed of a constituent element of the first barrier layer and a constituent element of the second barrier layer at an interface between the first barrier layer and the second barrier layer. Device manufacturing method. 11. A heat treatment for forming an amorphous layer comprising a constituent element of the first barrier layer and a constituent element of the second barrier layer at an interface between the first barrier layer and the second barrier layer, and then performing a heat treatment. 11. The method for manufacturing a semiconductor device according to claim 10, further comprising the step of forming a wiring made of copper or a copper alloy on the second barrier layer. 12. A first barrier layer for covering at least one of upper and lower surfaces and side surfaces of a wiring made of copper or copper alloy on an insulating layer, and a second barrier layer made of a material different from the first barrier layer. And forming a wiring made of copper or a copper alloy on the second barrier layer, and then performing a heat treatment on the interface between the first barrier layer and the second barrier layer. Producing an amorphous layer composed of a constituent element and a constituent element of a second barrier layer. 13. A heat treatment for forming an amorphous layer composed of a constituent element of the first barrier layer and a constituent element of the second barrier layer at an interface between the first barrier layer and the second barrier layer has a first temperature. 13. The method according to claim 10, wherein the temperature is lower than a temperature at which the barrier layer and the second barrier layer react to form a stable alloy.