JP2009105289A - METHOD OF FORMING Cu WIRING - Google Patents

METHOD OF FORMING Cu WIRING Download PDF

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JP2009105289A
JP2009105289A JP2007276891A JP2007276891A JP2009105289A JP 2009105289 A JP2009105289 A JP 2009105289A JP 2007276891 A JP2007276891 A JP 2007276891A JP 2007276891 A JP2007276891 A JP 2007276891A JP 2009105289 A JP2009105289 A JP 2009105289A
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Prior art keywords
layer
forming
wiring
trench
hole
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Tatsuo Hatano
達夫 波多野
Atsushi Gomi
淳 五味
Yasushi Mizusawa
寧 水澤
Masamichi Hara
正道 原
Takashi Sakuma
隆 佐久間
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Priority to JP2007276891A priority Critical patent/JP2009105289A/en
Priority to PCT/JP2008/068290 priority patent/WO2009054268A1/en
Priority to TW97140653A priority patent/TW200931531A/en
Publication of JP2009105289A publication Critical patent/JP2009105289A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming Cu wiring, capable of filling up Cu reliably even into a minute trench or hole. <P>SOLUTION: In forming a Cu wiring in a Low-k film 2 having a trench 3 formed on a silicon substrate 1 via a barrier layer 4, a layer 5 to be wet constituted by a metal material to wet with Cu is formed on the barrier layer 4 through CVD, a Cu layer 6 is formed on the layer 5 to be wet through PVD, and after forming the Cu layer 6, the silicon substrate 1 is heated to allow the Cu layer 6 to flow into the trench 3 to be filled with Cu. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、例えば半導体ウエハ等の基板に形成されたトレンチまたはホールを有する低誘電率層間絶縁膜等の所定の層にバリア層を介してＣｕ配線を形成するＣｕ配線の形成方法に関する。   The present invention relates to a Cu wiring forming method for forming a Cu wiring through a barrier layer on a predetermined layer such as a low dielectric constant interlayer insulating film having a trench or a hole formed on a substrate such as a semiconductor wafer.

近時、半導体デバイスの高速化、配線パターンの微細化、高集積化の要求に対応して、配線間の容量の低下ならびに配線の導電性向上およびエレクトロマイグレーション耐性の向上が求められており、それに対応した技術として、配線材料にアルミニウム（Ａｌ）やタングステン（Ｗ）よりも導電性が高くかつエレクトロマイグレーション耐性に優れている銅（Ｃｕ）を用い、層間絶縁膜として低誘電率膜（Ｌｏｗ−ｋ膜）を用いたＣｕ多層配線技術が注目されている。   Recently, in response to demands for higher speeds of semiconductor devices, finer wiring patterns, and higher integration, there has been a demand for lower capacitance between wirings, improved wiring conductivity, and improved electromigration resistance. As a corresponding technology, copper (Cu), which has higher conductivity than aluminum (Al) and tungsten (W) and has excellent electromigration resistance, is used as a wiring material, and a low dielectric constant film (Low-k) is used as an interlayer insulating film. Cu multilayer wiring technology using a film) has attracted attention.

この際のＣｕ配線の形成方法としては、トレンチやホールが形成されたＬｏｗ−ｋ膜にＴａ、ＴａＮ、Ｔｉなどからなるバリア層をスパッタリングに代表される物理蒸着法（ＰＶＤ）で形成し、その上に同じくＰＶＤによりＣｕシード層を形成し、さらにその上にＣｕめっきを施す技術が知られている（例えば特許文献１）。   As a method for forming the Cu wiring at this time, a barrier layer made of Ta, TaN, Ti or the like is formed on the low-k film in which trenches and holes are formed by a physical vapor deposition method (PVD) represented by sputtering. A technique is also known in which a Cu seed layer is similarly formed on PVD and Cu plating is further formed thereon (for example, Patent Document 1).

しかしながら、半導体デバイスのデザインルールが益々微細化しており、今後の３２ｎｍノード以降においては、上記特許文献１に開示された技術では、ステップカバレッジが本質的に低いＰＶＤでＣｕシード層をトレンチやホール内に形成することが困難となり、したがって、ホール内にめっきを形成することも困難となることが予想される。   However, the design rules of semiconductor devices are becoming increasingly finer, and in the future 32 nm node and beyond, the technique disclosed in the above-mentioned Patent Document 1 uses a PVD having a low step coverage to place a Cu seed layer in a trench or hole. Therefore, it is expected that it is difficult to form a plating in the hole.

また、めっきプロセスにおいては微細配線を埋め込むにあたり、添加剤を必要とし、その管理には多大なコストがかかり、コストアップの要因となっている。さらに配線にその添加剤が残留し配線抵抗の上昇の要因ともなっている。
特開平１１−３４０２２６号公報 Further, in the plating process, an additive is required for embedding the fine wiring, and its management requires a great deal of cost, which causes an increase in cost. Further, the additive remains in the wiring, which causes an increase in wiring resistance.
Japanese Patent Laid-Open No. 11-340226

本発明はかかる事情に鑑みてなされたものであって、微細なトレンチまたはホールにも確実にＣｕを埋め込むことができるＣｕ配線の形成方法を提供することを目的とする。
また、めっきを用いることなく、またはめっきの使用を極力少なくして、Ｃｕ配線を形成することができるＣｕ配線の形成方法を提供することを目的とする。 The present invention has been made in view of such circumstances, and an object of the present invention is to provide a method for forming a Cu wiring that can reliably embed Cu in a fine trench or hole.
Moreover, it aims at providing the formation method of Cu wiring which can form Cu wiring, without using plating or reducing use of plating as much as possible.

上記課題を解決するため、本発明の第１の観点では、基板上に形成されたトレンチまたはホールを有する所定の層にバリア層を介してＣｕ配線を形成するＣｕ配線の形成方法であって、前記バリア層の上にＣＶＤによりＣｕが濡れる金属材料で構成された被濡れ層を形成する工程と、前記被濡れ層の上にＰＶＤによりＣｕ層を形成する工程と、Ｃｕ層を形成した後、基板を加熱してＣｕ層を流動させ、トレンチまたはホール内にＣｕを流し込む工程とを有することを特徴とするＣｕ配線の形成方法を提供する。   In order to solve the above problems, according to a first aspect of the present invention, there is provided a Cu wiring forming method for forming a Cu wiring through a barrier layer in a predetermined layer having a trench or a hole formed on a substrate, A step of forming a wet layer composed of a metal material on which Cu is wetted by CVD on the barrier layer, a step of forming a Cu layer by PVD on the wet layer, and a Cu layer; There is provided a method for forming a Cu wiring, comprising: heating a substrate to cause a Cu layer to flow, and pouring Cu into a trench or a hole.

この場合に、前記Ｃｕ層の厚さは、５〜５０ｎｍであることが好ましい。   In this case, the thickness of the Cu layer is preferably 5 to 50 nm.

本発明の第２の観点では、基板上に形成されたトレンチまたはホールを有する所定の層にバリア層を介してＣｕ配線を形成するＣｕ配線の形成方法であって、前記バリア層の上にＣＶＤによりＣｕが濡れる金属材料で構成された被濡れ層を形成する工程と、前記被濡れ層の上にＰＶＤによりＣｕ層を形成する工程と、Ｃｕ層を形成した後、基板を加熱してＣｕ層を流動させ、トレンチまたはホール内の途中までＣｕを流し込む工程と、その後、Ｃｕめっき層を形成し、トレンチまたはホールを完全に埋める工程とを有することを特徴とするＣｕ配線の形成方法を提供する。   According to a second aspect of the present invention, there is provided a Cu wiring forming method in which a Cu wiring is formed on a predetermined layer having a trench or a hole formed on a substrate through a barrier layer, and the CVD is performed on the barrier layer. Forming a wetted layer composed of a metal material that wets Cu by the step, forming a Cu layer by PVD on the wetted layer, forming a Cu layer, and then heating the substrate to form a Cu layer A Cu wiring forming method comprising: a step of flowing Cu into the trench or hole, and a step of forming a Cu plating layer and completely filling the trench or hole. .

この場合に、前記Ｃｕ層の厚さは、５〜３０ｎｍであることが好ましい。   In this case, the thickness of the Cu layer is preferably 5 to 30 nm.

上記第１、第２の観点において、前記被濡れ層は、Ｒｕで構成されていることが好ましい。また、前記基板を加熱する際の温度は、２５０〜３５０℃であることが好ましい。さらに、前記被濡れ層の厚さは、１〜５ｎｍであることが好ましい。   In the first and second aspects, the wettable layer is preferably made of Ru. Moreover, it is preferable that the temperature at the time of heating the said board | substrate is 250-350 degreeC. Furthermore, the thickness of the wetted layer is preferably 1 to 5 nm.

本発明によれば、バリア層の上に、ＰＶＤによるＣｕ層の形成に先立って、ステップカバレッジの良好なＣＶＤによりＣｕが濡れる金属材料で構成された被濡れ層を形成するので、微細なトレンチまたはホールにも容易に形成することができ、しかも、被濡れ層の上にＰＶＤによりＣｕ層を形成した際にＣｕ層が微細トレンチまたはホール内に入り込まなくても、その後の加熱によりトレンチやホールの周囲のＣｕ層が被濡れ層に沿ってトレンチまたはホール内に流れ込み、トレンチまたはホール内に確実にＣｕを充填させることができる。このように、純度の高いＰＶＤによるＣｕ層をトレンチまたはホール内に流動させてＣｕを充填するので、Ｃｕめっきは必須ではなく、また、Ｃｕめっきを用いたとしても補助的なものでよいため、めっきの添加剤等の問題を解消ないしは軽減することができる。   According to the present invention, a wet layer composed of a metal material that Cu gets wet by CVD with good step coverage is formed on the barrier layer prior to the formation of the Cu layer by PVD. Even when the Cu layer is formed on the wetted layer by PVD, the Cu layer does not enter the fine trench or the hole. The surrounding Cu layer flows into the trench or hole along the wetted layer, and the trench or hole can be reliably filled with Cu. Thus, since the Cu layer made of high-purity PVD is caused to flow into the trench or hole to fill the Cu, Cu plating is not essential, and even if Cu plating is used, it may be auxiliary. Problems such as plating additives can be eliminated or reduced.

以下、添付図面を参照して本発明の実施形態について具体的に説明する。
図１は本発明に係るＣｕ配線の形成方法の一例を説明するためのフローチャート、図２はこれらの工程を示す工程断面図である。 Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.
FIG. 1 is a flowchart for explaining an example of a Cu wiring forming method according to the present invention, and FIG. 2 is a process cross-sectional view showing these processes.

まず、図２（ａ）に示すように、シリコン基板１上にＬｏｗ−ｋ膜２を形成し、フォトリソグラフィによりトレンチ（またはホール）３を形成した後に全面にバリア層４を形成した構造を準備する（工程１）。ここで、バリア層４を構成する材料としては、Ｔａ、ＴａＮ、Ｔｉ等を挙げることができる。ＴａＮおよびＴａの積層膜であってもよい。   First, as shown in FIG. 2A, a structure is prepared in which a low-k film 2 is formed on a silicon substrate 1, a trench (or hole) 3 is formed by photolithography, and then a barrier layer 4 is formed on the entire surface. (Step 1). Here, examples of the material constituting the barrier layer 4 include Ta, TaN, and Ti. A stacked film of TaN and Ta may be used.

次に、図２（ｂ）に示すように、バリア層４の上に、ＣＶＤによりＣｕが濡れる金属材料で構成された被濡れ層５を形成する（工程２）。Ｃｕが濡れる金属材料とは、Ｃｕに対して親和性を有するものであり、格子定数がＣｕと近い金属が該当する。そのような点から、この被濡れ層５としては、Ｒｕが好ましい。ＲｕはＣｕに対する濡れ性が極めて高い材料であり、格子定数が２．３４オングストロームとＣｕの２．２３オングストロームに極めて近い。ＲｕのＣＶＤ成膜は、原料ガスとしてＲｕ３（ＣＯ）１２を用いて、圧力：１．３〜６６．５Ｐａ、温度：１５０〜２５０℃の条件で行うことができる。被濡れ層５を構成する金属材料として、他に、Ｉｒ、Ｃｏ等の貴金属系材料を好適に用いることができる。この被濡れ層５の厚さは１〜５ｎｍ程度であることが好ましい。また、この被濡れ層５は、Ｃｕとの親和性を確保する観点から高純度のものが好ましく、純度が９９％以上のものが好ましい。 Next, as shown in FIG. 2B, a wet layer 5 made of a metal material that Cu is wetted by CVD is formed on the barrier layer 4 (step 2). The metal material to which Cu gets wet has an affinity for Cu, and corresponds to a metal having a lattice constant close to that of Cu. From such a point, Ru is preferable as the wettable layer 5. Ru is a material with very high wettability to Cu, and its lattice constant is very close to 2.34 angstroms and 2.23 angstroms of Cu. Ru CVD film formation can be performed using Ru 3 (CO) 12 as a source gas under conditions of pressure: 1.3 to 66.5 Pa and temperature: 150 to 250 ° C. In addition, noble metal materials such as Ir and Co can be suitably used as the metal material constituting the wettable layer 5. The wet layer 5 preferably has a thickness of about 1 to 5 nm. In addition, the wettable layer 5 preferably has a high purity from the viewpoint of ensuring affinity with Cu, and preferably has a purity of 99% or more.

次に、図２（ｃ）に示すように、被濡れ層５の上にスパッタリング等のＰＶＤによりＣｕ層６を形成する（工程３）。スパッタリングでＣｕ層６を形成する場合には、スパッタリング装置にＣｕターゲットを設置し、チャンバ内の圧力：０．６７〜１３．３Ｐａ、温度：−３０〜３０℃の条件で常法に従って行うことができる。ＰＶＤはステップカバレッジが悪いため、トレンチ（またはホール）３内には入り込みにくく、特に線幅、すなわちホール径またはトレンチ幅が３２ｎｍよりも小さい場合には、図示するように、ほとんどその中にＣｕが入り込まない。   Next, as shown in FIG. 2C, a Cu layer 6 is formed on the wetted layer 5 by PVD such as sputtering (step 3). When forming the Cu layer 6 by sputtering, a Cu target is installed in the sputtering apparatus, and it is carried out in accordance with a conventional method under conditions of pressure in the chamber: 0.67 to 13.3 Pa and temperature: -30 to 30 ° C. it can. Since PVD has poor step coverage, it is difficult to enter the trench (or hole) 3. Especially when the line width, that is, the hole diameter or the trench width is smaller than 32 nm, as shown in FIG. Don't get in.

このようにしてＣｕ層６を形成後、シリコン基板１を加熱してＣｕ層６を流動させ、図２（ｄ）に示すように、トレンチ（またはホール）３内にＣｕを流し込む（工程４）。この場合の加熱温度は２５０〜３５０℃の範囲が好ましい。２５０℃より低いとＣｕが流動し難く、３５０℃より高くなるとＣｕが凝集しやすくなり、かつ下地のＬｏｗ−ｋ膜２などに悪影響を及ぼすおそれがある。より流動性を良好にする観点からは２６０℃以上が好ましい。また、凝集等の不都合をなくす観点からは、３００℃以下がより好ましい。   After forming the Cu layer 6 in this way, the silicon substrate 1 is heated to cause the Cu layer 6 to flow, and as shown in FIG. 2D, Cu is poured into the trench (or hole) 3 (step 4). . In this case, the heating temperature is preferably in the range of 250 to 350 ° C. When the temperature is lower than 250 ° C., Cu hardly flows, and when the temperature is higher than 350 ° C., Cu tends to aggregate, and the underlying Low-k film 2 may be adversely affected. From the viewpoint of improving fluidity, 260 ° C. or higher is preferable. Further, from the viewpoint of eliminating inconvenience such as aggregation, 300 ° C. or lower is more preferable.

このような加熱によるＣｕの流入によってトレンチ（またはホール）３を埋めるためには、トレンチ等の体積にもよるが、Ｃｕ層６の厚さは５〜５０ｎｍ程度が好ましい。   In order to fill the trench (or hole) 3 by the inflow of Cu by such heating, although depending on the volume of the trench or the like, the thickness of the Cu layer 6 is preferably about 5 to 50 nm.

この加熱処理は、例えば、チャンバ内のステージにシリコン基板を載置し、チャンバ内に不活性ガス、例えばＡｒガスやＮ２ガスやＨ２ガスを導入しつつ排気し、チャンバ内を１３３３Ｐａ程度の高真空に維持し、ステージに埋設された抵抗ヒータによりシリコン基板を加熱することにより行われる。 In this heat treatment, for example, a silicon substrate is placed on a stage in the chamber, an inert gas such as Ar gas, N 2 gas, or H 2 gas is introduced into the chamber and exhausted, and the inside of the chamber is about 1333 Pa. This is done by maintaining a high vacuum and heating the silicon substrate with a resistance heater embedded in the stage.

この工程４について図３を参照しながら具体的に説明する。図２（ｃ）の状態でシリコン基板１を加熱すると（図３（ａ））、Ｃｕ層６は流動し、トレンチ（またはホール）３の周囲部分のＣｕ層のＣｕが被濡れ層５に沿って、ホール３内に流れて行く（図３（ｂ）。そして、流れ込んだＣｕが徐々にトレンチ（またはホール）３を埋め込んで行き、図３（ｃ）の状態を経て、図２（ｄ）に示すようにトレンチ（またはホール）３内を完全にＣｕで埋め込んで、Ｃｕ配線層を形成する。このようにＣｕ層６のＣｕをトレンチ（またはホール）３内に流し込んでＣｕ配線層を形成するため、Ｃｕ層６はトレンチ（またはホール）３を埋め込むのに十分な厚さに形成する必要がある。   Step 4 will be specifically described with reference to FIG. When the silicon substrate 1 is heated in the state of FIG. 2C (FIG. 3A), the Cu layer 6 flows, and Cu in the Cu layer around the trench (or hole) 3 follows the wetted layer 5. Then, it flows into the hole 3 (FIG. 3B), and the Cu that has flowed in gradually fills the trench (or hole) 3 and goes through the state of FIG. As shown in Fig. 2, the Cu wiring layer is formed by completely filling the trench (or hole) 3 with Cu, and the Cu wiring layer is thus poured into the trench (or hole) 3 to form the Cu wiring layer. Therefore, the Cu layer 6 needs to be formed to a thickness sufficient to fill the trench (or hole) 3.

このようにＣｕが凝集せずにトレンチ（またはホール）３内に流れるのは、被濡れ層５を構成する材料がＲｕ等のＣｕに対して濡れ性、つまり親和性の良好な金属であり、加熱されたＣｕが被濡れ層５に濡れた状態で流動するからである。   Thus, Cu does not aggregate and flows into the trench (or hole) 3 because the material constituting the wetted layer 5 is a metal having good wettability, that is, good affinity for Cu such as Ru. This is because the heated Cu flows while wetted by the wetted layer 5.

本実施形態では、Ｃｕが被濡れ層５に沿って流動してトレンチ（またはホール）３内の被濡れ層５の全面にＣｕが形成され、引き続きトレンチ（またはホール）３をＣｕが埋めて行くので、ボイド等の欠陥を生じさせることなくＣｕを埋め込むことができる。   In the present embodiment, Cu flows along the wetted layer 5 to form Cu on the entire surface of the wetted layer 5 in the trench (or hole) 3, and then the Cu is filled in the trench (or hole) 3. Therefore, Cu can be embedded without causing defects such as voids.

また、被濡れ層５はステップカバレッジの良好なＣＶＤにより形成されるのでトレンチ（またはホール）３の内面全面に形成することができ、その上にＰＶＤによりＣｕ層６を形成した後、基板を加熱することによりＣｕが被濡れ層５に濡れた状態で被濡れ層５に沿ってホール３内に流動するので、極狭いホール内にもＣｕを埋め込むことができる。このため、従来のＰＶＤによるＣｕシード＋Ｃｕめっきでは困難であった線幅３２ｎｍよりも狭いＣｕ配線を高信頼性をもって形成することができる。また、Ｃｕ配線が極めて高純度のＰＶＤで形成されたもののみであり、Ｃｕめっきを使用しないため、Ｃｕ配線に添加剤が残留して配線抵抗が上昇するといったことが生じない。   Further, since the wetted layer 5 is formed by CVD with good step coverage, it can be formed on the entire inner surface of the trench (or hole) 3, and after the Cu layer 6 is formed thereon by PVD, the substrate is heated. By doing so, Cu flows into the hole 3 along the wetted layer 5 in a state in which the wetted layer 5 is wetted, so that Cu can be embedded in an extremely narrow hole. For this reason, Cu wiring narrower than the line width of 32 nm, which was difficult with Cu seed + Cu plating by conventional PVD, can be formed with high reliability. Further, since the Cu wiring is only made of extremely high-purity PVD and Cu plating is not used, the additive does not remain in the Cu wiring and the wiring resistance does not increase.

以上は、トレンチ（またはホール）３内をすべてＰＶＤで形成したＣｕ層６を流動させて埋め込む場合について示したが、Ｃｕ層６を十分な厚さで形成することが困難である場合、またはＣｕを埋め込むべきトレンチ（またはホール）の体積が大きい場合等、全てＣｕ層６の流動でまかなうことが困難な場合もある。そのような場合には、図４に示すように、Ｃｕ層６を流動させてＣｕをホール３の途中まで埋め込み（図４（ａ））、その後、補助的にＣｕめっき層７を形成する（図４（ｂ））ことが好ましい。これにより、Ｃｕ層６のみでは十分にホールを埋め込めない場合でも、Ｃｕ配線を形成することができる。この場合のＣｕ層６の流動する前の厚さは、５〜３０ｎｍ程度が好ましい。   The above shows the case where the Cu layer 6 formed of PVD is entirely flown and buried in the trench (or hole) 3, but it is difficult to form the Cu layer 6 with a sufficient thickness, or Cu In some cases, it is difficult to cover all by the flow of the Cu layer 6, for example, when the volume of the trench (or hole) to be embedded is large. In such a case, as shown in FIG. 4, the Cu layer 6 is made to flow and Cu is embedded in the middle of the hole 3 (FIG. 4A), and then a Cu plating layer 7 is formed as an auxiliary ( FIG. 4B is preferable. As a result, Cu wiring can be formed even if the Cu layer 6 alone cannot sufficiently fill the holes. In this case, the thickness of the Cu layer 6 before flowing is preferably about 5 to 30 nm.

この場合に、Ｃｕめっきは補助的に用いるのみで、その量は少ないから、Ｃｕめっきの添加剤にともなう配線抵抗の増大といった不都合を最少限に抑制することができる。   In this case, Cu plating is only used supplementarily, and since the amount thereof is small, inconvenience such as an increase in wiring resistance due to the additive of Cu plating can be minimized.

なお、本発明を実施するにあたっては、被濡れ層の形成、Ｃｕ層の形成、その後の加熱処理を全く別個の装置を用いて行ってもよいし、クラスタータイプのマルチチャンバシステムを用いて真空を破らずにこれらの処理の一部または全部を連続して行ってもよい。また、バリア層を形成するチャンバをマルチチャンバシステムに含めてもよい。   In carrying out the present invention, the formation of the wetted layer, the formation of the Cu layer, and the subsequent heat treatment may be performed using a completely separate apparatus, or a vacuum is applied using a cluster type multi-chamber system. Some or all of these processes may be performed continuously without breaking. A chamber for forming the barrier layer may also be included in the multi-chamber system.

次に、実際に本発明を実施した結果について説明する。
ここでは、まず、シリコン基板上に、厚さ２００ｎｍのＬｏｗ−ｋ膜（ＳｉＯＣ）を形成し、フォトリソグラフィによりＬｏｗ−ｋに、径がそれぞれ３０ｎｍ、６５ｎｍ、８５ｎｍのトレンチを形成し、その上に厚さ４ｎｍのＴｉバリア層をスパッタリングで形成した構造体を準備し、これらのバリア層の上に被濡れ層として厚さ２ｎｍのＲｕ膜を全面に形成し、さらにその上にスパッタリングによりＣｕ層を１０ｎｍの厚さで形成してサンプルを作製した。その後、これらサンプルをＡｒガス雰囲気中、２６０℃で加熱してＣｕ層をホール内に流動させた。その際の断面の走査型顕微鏡（ＳＥＭ）写真を図５に示す。図５に示すように、いずれの幅のトレンチも２６０℃の加熱により、トレンチ内にＣｕが充填されている部分が見られる。したがって、本発明によりトレンチ内にＣｕを埋め込んでＣｕ配線を形成することが可能であることが見出された。 Next, the result of actually carrying out the present invention will be described.
Here, first, a low-k film (SiOC) having a thickness of 200 nm is formed on a silicon substrate, and trenches having diameters of 30 nm, 65 nm, and 85 nm are formed in low-k by photolithography, and the trenches are formed thereon. A structure in which a Ti barrier layer having a thickness of 4 nm is formed by sputtering is prepared, a Ru film having a thickness of 2 nm is formed as a wet layer on these barrier layers, and a Cu layer is further formed thereon by sputtering. A sample was prepared by forming a thickness of 10 nm. Thereafter, these samples were heated at 260 ° C. in an Ar gas atmosphere to cause the Cu layer to flow into the holes. A scanning microscope (SEM) photograph of the cross section at that time is shown in FIG. As shown in FIG. 5, a trench filled with Cu is seen in the trenches of any width by heating at 260 ° C. Therefore, it was found that Cu wiring can be formed by embedding Cu in the trench according to the present invention.

次いで、シリコン基板上に厚さ２００ｎｍのＬｏｗ−ｋ膜（ＳｉＯＣ）を形成し、Ｌｏｗ−ｋに、幅がそれぞれ３０ｎｍ、５０ｎｍ、７０ｎｍのトレンチを形成し、その上に厚さ４ｎｍのＴｉバリア層をスパッタリングで形成した構造体を準備し、これらのバリア層の上に被濡れ層として厚さ２ｎｍのＲｕ膜を全面に形成し、さらにその上にスパッタリングによりＣｕ層を１０ｎｍの厚さで形成してサンプルを作製した。その後、これらサンプルをＡｒガス雰囲気中にて、それぞれ１５０℃、２００℃、２６０℃、３００℃、３５０℃で加熱してＣｕ層をホール内に流動させた。その際の平面の走査型顕微鏡（ＳＥＭ）写真を図６に示す。比較のため加熱前の成膜まま（ａｓ ｄｅｐｏ）のサンプルについても同様に図６に示す。図６に示すように、加熱温度が２００℃までは、状態がａｓ ｄｅｐｏと変わらず、Ｃｕの流れ込みが生じていないことが確認された。これに対して加熱温度が２６０℃以上でＣｕが流動してトレンチ内への流れ込みが生じているのがわかる。しかし、加熱温度３５０℃においては、トレンチ幅７０ｎｍのサンプルではＣｕが良好にトレンチ内に流れ込んでいるものの、トレンチ幅３０ｎｍおよび５０ｎｍではＣｕの凝集が生じていることがわかる。したがって、Ｃｕ層を形成した後の加熱は、２５０〜３５０℃が好ましい範囲であることが確認された。   Next, a low-k film (SiOC) having a thickness of 200 nm is formed on the silicon substrate, trenches having a width of 30 nm, 50 nm, and 70 nm are formed on the low-k, respectively, and a Ti barrier layer having a thickness of 4 nm is formed thereon. A 2 nm-thick Ru film is formed on the entire surface of these barrier layers as a wet layer, and a Cu layer is formed thereon by sputtering to a thickness of 10 nm. A sample was prepared. Thereafter, these samples were heated in an Ar gas atmosphere at 150 ° C., 200 ° C., 260 ° C., 300 ° C., and 350 ° C., respectively, to cause the Cu layer to flow into the holes. A planar scanning microscope (SEM) photograph at that time is shown in FIG. For comparison, a sample as-deposited before heating is also shown in FIG. As shown in FIG. 6, it was confirmed that until the heating temperature was 200 ° C., the state did not change from as depo and Cu did not flow. On the other hand, it can be seen that when the heating temperature is 260 ° C. or higher, Cu flows and flows into the trench. However, at a heating temperature of 350 ° C., Cu flows well into the trench in the sample having a trench width of 70 nm, but it can be seen that Cu aggregation occurs at the trench widths of 30 nm and 50 nm. Therefore, it was confirmed that the heating after forming the Cu layer is in a preferred range of 250 to 350 ° C.

なお、本発明は上記実施形態に限定されることなく、種々の変形が可能である。例えば、上記実施形態では、被エッチング層としてＬｏｗ−ｋ膜を用いた場合について示したが、これに限らず他の膜であってもよい。また、基板としてシリコン基板を用いた例について示したが、他の半導体基板であってもよいし、半導体基板以外の基板であってもよい。   In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. For example, in the above-described embodiment, the case where the Low-k film is used as the layer to be etched has been described. Further, although an example in which a silicon substrate is used as the substrate has been described, another semiconductor substrate or a substrate other than the semiconductor substrate may be used.

本発明に係るＣｕ配線の形成方法の一例を説明するためのフローチャート。The flowchart for demonstrating an example of the formation method of Cu wiring which concerns on this invention. 本発明に係るＣｕ配線の形成方法の一例を説明するための工程断面図。Process sectional drawing for demonstrating an example of the formation method of Cu wiring which concerns on this invention. 加熱した際のＣｕの流動挙動を説明するための断面図。Sectional drawing for demonstrating the flow behavior of Cu at the time of heating. 加熱によりＣｕをトレンチ内に流動させた後Ｃｕめっきを施す場合の手順を示す工程断面図。Process sectional drawing which shows the procedure in the case of performing Cu plating, after making Cu flow in a trench by heating. 本発明の方法をトレンチ幅を変えて実際に行った場合のサンプルの断面状態を示す走査型顕微鏡写真。The scanning photomicrograph which shows the cross-sectional state of the sample at the time of actually performing the method of this invention, changing trench width. 本発明の方法をトレンチ幅および加熱の際の温度を変えて実際に行った場合のサンプルの平面状態を示す操作型顕微鏡写真。The operation type | mold microscope picture which shows the planar state of the sample at the time of actually performing the method of this invention by changing the temperature in the case of trench width and a heating.

符号の説明Explanation of symbols

１；シリコン基板
２；Ｌｏｗ−ｋ膜
３；トレンチ（またはホール）
４；バリア層
５；被濡れ層
６；Ｃｕ層
７；Ｃｕめっき層 1; silicon substrate 2; low-k film 3; trench (or hole)
4; Barrier layer 5; Wetting layer 6; Cu layer 7; Cu plating layer

Claims (7)

基板上に形成されたトレンチまたはホールを有する所定の層にバリア層を介してＣｕ配線を形成するＣｕ配線の形成方法であって、
前記バリア層の上にＣＶＤによりＣｕが濡れる金属材料で構成された被濡れ層を形成する工程と、
前記被濡れ層の上にＰＶＤによりＣｕ層を形成する工程と、
Ｃｕ層を形成した後、基板を加熱してＣｕ層を流動させ、トレンチまたはホール内にＣｕを流し込む工程と
を有することを特徴とするＣｕ配線の形成方法。 A Cu wiring forming method for forming a Cu wiring through a barrier layer in a predetermined layer having a trench or a hole formed on a substrate,
Forming a wetted layer composed of a metal material on which Cu is wetted by CVD on the barrier layer;
Forming a Cu layer by PVD on the wetted layer;
A method of forming a Cu wiring, comprising: forming a Cu layer, heating the substrate to flow the Cu layer, and pouring Cu into the trench or hole. 前記Ｃｕ層の厚さは、５〜５０ｎｍであることを特徴とする請求項１に記載のＣｕ配線の形成方法。   The Cu wiring forming method according to claim 1, wherein the Cu layer has a thickness of 5 to 50 nm. 基板上に形成されたトレンチまたはホールを有する所定の層にバリア層を介してＣｕ配線を形成するＣｕ配線の形成方法であって、
前記バリア層の上にＣＶＤによりＣｕが濡れる金属材料で構成された被濡れ層を形成する工程と、
前記被濡れ層の上にＰＶＤによりＣｕ層を形成する工程と、
Ｃｕ層を形成した後、基板を加熱してＣｕ層を流動させ、トレンチまたはホール内の途中までＣｕを流し込む工程と、
その後、Ｃｕめっき層を形成し、トレンチまたはホールを完全に埋める工程と
を有することを特徴とするＣｕ配線の形成方法。 A Cu wiring forming method for forming a Cu wiring through a barrier layer in a predetermined layer having a trench or a hole formed on a substrate,
Forming a wetted layer composed of a metal material on which Cu is wetted by CVD on the barrier layer;
Forming a Cu layer by PVD on the wetted layer;
After forming the Cu layer, the substrate is heated to flow the Cu layer, and the Cu is poured halfway in the trench or hole;
And forming a Cu plating layer and completely filling the trench or the hole. 前記Ｃｕ層の厚さは、５〜３０ｎｍであることを特徴とする請求項３に記載のＣｕ配線の形成方法。   The Cu wiring forming method according to claim 3, wherein the Cu layer has a thickness of 5 to 30 nm. 前記被濡れ層は、Ｒｕで構成されていることを特徴とする請求項１から請求項４のいずれか１項に記載のＣｕ配線の形成方法。   5. The method for forming a Cu wiring according to claim 1, wherein the wetted layer is made of Ru. 6. 前記基板を加熱する際の温度は、２５０〜３５０℃であることを特徴とする請求項１から請求項５のいずれか１項に記載のＣｕ配線の形成方法。   The method for forming a Cu wiring according to any one of claims 1 to 5, wherein a temperature at which the substrate is heated is 250 to 350 ° C. 前記被濡れ層の厚さは、１〜５ｎｍであることを特徴とする請求項１から請求項６のいずれか１項に記載のＣｕ配線の形成方法。   The thickness of the said wetted layer is 1-5 nm, The formation method of Cu wiring of any one of Claims 1-6 characterized by the above-mentioned.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340227A (en) * 1998-05-25 1999-12-10 Fujitsu Ltd Semiconductor device and its manufacture
JP2002075994A (en) * 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
WO2006104853A1 (en) * 2005-03-31 2006-10-05 Tokyo Electron Limited Low-temperature chemical vapor deposition of low-resistivity ruthenium layers
JP2007214387A (en) * 2006-02-09 2007-08-23 Tokyo Electron Ltd Film depositing method, plasma film forming device, and storage medium

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340227A (en) * 1998-05-25 1999-12-10 Fujitsu Ltd Semiconductor device and its manufacture
JP2002075994A (en) * 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
WO2006104853A1 (en) * 2005-03-31 2006-10-05 Tokyo Electron Limited Low-temperature chemical vapor deposition of low-resistivity ruthenium layers
JP2007214387A (en) * 2006-02-09 2007-08-23 Tokyo Electron Ltd Film depositing method, plasma film forming device, and storage medium

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US9392690B2 (en) 2010-07-19 2016-07-12 Globalfoundries Inc. Method and structure to improve the conductivity of narrow copper filled vias
US10879113B2 (en) 2010-08-20 2020-12-29 Micron Technology, Inc. Semiconductor constructions; and methods for providing electrically conductive material within openings
JP2013534370A (en) * 2010-08-20 2013-09-02 マイクロン テクノロジー， インク． Semiconductor structure and method for providing a conductive material in an opening
US10121697B2 (en) 2010-08-20 2018-11-06 Micron Technology, Inc. Semiconductor constructions; and methods for providing electrically conductive material within openings
US9177917B2 (en) 2010-08-20 2015-11-03 Micron Technology, Inc. Semiconductor constructions
JP2012216765A (en) * 2011-01-27 2012-11-08 Tokyo Electron Ltd FORMATION METHOD OF Cu WIRING AND FILM-FORMING SYSTEM
US8399353B2 (en) 2011-01-27 2013-03-19 Tokyo Electron Limited Methods of forming copper wiring and copper film, and film forming system
JP2012169590A (en) * 2011-01-27 2012-09-06 Tokyo Electron Ltd FORMATION METHOD OF Cu WIRING, DEPOSITION METHOD OF Cu FILM, AND DEPOSITION SYSTEM
US8859422B2 (en) 2011-01-27 2014-10-14 Tokyo Electron Limited Method of forming copper wiring and method and system for forming copper film
JP2013074173A (en) * 2011-09-28 2013-04-22 Ulvac Japan Ltd Manufacturing method of semiconductor device and semiconductor device
JP2013120859A (en) * 2011-12-07 2013-06-17 Ulvac Japan Ltd Reflow method and semiconductor device manufacturing method
JP2013143442A (en) * 2012-01-10 2013-07-22 Ulvac Japan Ltd Device manufacturing method and manufacturing device
JP2013171940A (en) * 2012-02-20 2013-09-02 Ulvac Japan Ltd Semiconductor device manufacturing method
JP2014033139A (en) * 2012-08-06 2014-02-20 Ulvac Japan Ltd Device manufacturing method
JP2014036109A (en) * 2012-08-08 2014-02-24 Tokyo Electron Ltd Cu WIRING FORMATION METHOD
KR101662369B1 (en) * 2012-08-08 2016-10-04 도쿄엘렉트론가부시키가이샤 METHOD FOR FORMING Cu WIRING AND STORAGE MEDIUM
KR20140020203A (en) * 2012-08-08 2014-02-18 도쿄엘렉트론가부시키가이샤 Method for forming cu wiring and storage medium
JP2014086537A (en) * 2012-10-23 2014-05-12 Ulvac Japan Ltd METHOD OF FORMING Cu LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
JP2015018839A (en) * 2013-07-08 2015-01-29 株式会社アルバック Cu WIRING STRUCTURE FORMATION METHOD
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KR20170106461A (en) 2015-02-26 2017-09-20 도쿄엘렉트론가부시키가이샤 Method of forming Cu wiring and method of manufacturing semiconductor device
US10163699B2 (en) 2015-02-26 2018-12-25 Tokyo Electron Limited Cu wiring forming method and semiconductor device manufacturing method
JP2018519656A (en) * 2015-06-30 2018-07-19 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ Interconnect structure and method of manufacturing the same
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