JPH07307567A - Thin film multilayered wiring board and semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a thin film multilayered wiring board which is lessened in number of laminated layers keeping high in wiring density and still in strip- line structure or micro strip-line structure and where a thin film capacitor of high reliability is built in. CONSTITUTION:Conductive layers and interlayer insulating layers are alternately laminated on a board 21, and the conductive layers are mutually connected together for the formation of a thin film multilayered wiring board, wherein a power supply layer 22 and a lower ground layer 23 electrically isolated from the power supply layer 22 out of the conductive layers are formed on the same board 21, and an upper ground layer 26a connected to the lower ground layer 23 through the intermediary of an opening 30 bored in the lower ground layer 23 and a pad layer 26 electrically isolated from the upper ground layer 26a are formed on the uppermost interlayer insulating layer 28c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film multilayer wiring board and a semiconductor device, and more particularly to a thin film multilayer wiring board and a semiconductor device having a stripline structure or a microstripline structure.

[0002]

2. Description of the Related Art In recent years, in a computer that performs high-speed signal processing, a plurality of ICs are mounted in order to achieve high integration, reduce the number of assembling steps, facilitate assembly, and improve yield and reliability. As a wiring board for wiring between ICs, a thin film multilayer wiring board in which a plurality of conductive layers are laminated with an interlayer insulating layer interposed has come to be used.

In the thin-film multilayer wiring board, the signal layer is extrinsic due to the shielding effect of the ground layer and the power supply layer by sandwiching the signal layer between the ground layer and the power supply layer formed continuously or in a mesh shape in a wide range. There are a stripline structure that is less susceptible to noise and a microstripline structure that forms both a ground layer and a power supply layer between a signal layer and a substrate and shields the substrate side.

FIG. 7 is a sectional view showing a conventional thin film multilayer wiring board having a stripline structure. As shown in FIG. 7, the thin-film multilayer wiring board includes a ground layer (or power supply layer) 2 as a first layer and a first signal layer 3 as a second layer on a substrate 1.
a, 3b, the second signal layers 4a, 4b of the third layer, the power supply layer (or ground layer) 5 of the fourth layer, and the pad layer 6 of the fifth layer are inter-layer insulating layers 8a, 8b, 8c, 8d
Are formed by interposing. Here, the pad layer 6 on the uppermost interlayer insulating layer 8d has a rectangular shape and serves as a bonding pad layer or the like. In addition to this, a chip is mounted on the interlayer insulating layer 8d with a conductive resin interposed. The area of the die pad to be placed is secured.

The first signal layers 3a and 3b and the second signal layers 4a and 4b are made of strip-shaped conductive thin films, and are adjacent to each other in order to facilitate connection between the signal layers and to achieve high density. The layers are formed separately. Also, the ground layer 2
Is formed on the substrate 1 and the power supply layer 5 is formed on the interlayer insulating film 8c by a conductive thin film which is continuous or mesh-shaped over a wide range. Each conductive thin film is formed by sputtering, plating or the like. Furthermore, the first signal layer 3a,
By appropriately designing the width dimensions of the third signal layer 3b and the second signal layers 4a, 4b and the film thicknesses of the interlayer insulating films 8a, 8c, the first signal layer 3a, 3b and the second signal layer 4a, 4b and the ground can be formed. A distributed constant circuit formed between the layer 2 or the power supply layer 5 can match the characteristic impedance to efficiently transmit a signal at high speed.

Further, the interlayer insulating layers 8a, 8b, 8c, 8d
Photosensitive polyimide is used as a material for the interlayer insulating layers 8a, 8b, and
Via holes 9a, 9b, 9c formed in 8c, 8d,
The conductive layers are connected via 9d. For example,
The ground layer 2 and the first signal layers 3a and 3b are connected via the via holes 9a and 9b of the interlayer insulating layer 8a, and the first signal layers 3a and 3b and the second signal layers 4a and 4b are insulated from each other. Connection is made via via holes 9c and 9d formed in the layer 8b. Although not shown in the figure, the first signal layer 3
If necessary, the a, 3b and the second signal layers 4a, 4b and the power supply layer 5, and the power supply layer 5 and the like and the surface pad layers 6a, 6b are similarly connected.

Further, on the substrate 1, a thermal via hole 10 reaching the ground layer 2 through the interlayer insulating films 8a, 8b, 8c and 8d is formed in the area of the die pad, and each interlayer insulating film is provided in the thermal via hole 10. Layers 8a, 8b,
Each time 8c and 8d are stacked, the metal layers 3c, 4c and 5a,
6a are stacked. The heat generated by the operation of the IC chip placed on the die pad through the conductive resin is conducted to the ground layer 2 through these metal layers 3c, 4c, 5a and 6a, and dissipated.

[0008]

By the way, in the above-mentioned thin-film multilayer wiring board, five conductive layers are required in order to perform high-density wiring and to have a stripline structure. The same applies to the case of the microstrip line structure. In order to reduce the manufacturing cost, it is necessary to improve the manufacturing yield of the thin film multilayer wiring board or shorten the manufacturing procedure, and also to reduce the material cost. Therefore, it is desired to reduce the number of laminated conductive layers.

In particular, in a multi-chip module, it is desirable to incorporate a thin film capacitor 13 in a thin film multilayer wiring board as a bypass capacitor connected between the positive and negative terminals of a power source in order to reduce ground bounce (signal reflected wave). It is rare. Conventionally, as shown in FIG. 8, a power supply layer 11 connected to an upper power supply layer 5 via a via hole 14 and metal layers 3d and 4d is formed below the ground layer 2, and the power supply layer 11 and the ground layer 2 are formed. A SiO ₂ film formed by the CVD method or a polyimide film formed by the spin coating method is sandwiched between the capacitor and the film as a capacitance insulating film 12 to form a thin film capacitor 13.

However, if particles or the like adhere to the surface to be grown during the CVD film formation, the S
The iO ₂ film grows abnormally and pinholes are easily generated in the SiO ₂ film. Further, during spin coating, if particles or the like adhere to the surface to be grown, the polyimide solution does not adhere to those areas, and pinholes are likely to occur in the polyimide film.
For this reason, there is a risk that the power supply layer and the ground layer are short-circuited via the pinholes, which causes a problem that the yield is reduced, or a short circuit is caused during use, resulting in a reduction in reliability.

The present invention has been made in view of the problems of the conventional example, and aims to reduce the number of laminated layers while maintaining high-density wiring and a stripline structure or a microstripline structure, and to improve reliability. An object of the present invention is to provide a thin film multilayer wiring board and a semiconductor device in which a high-performance thin film capacitor is incorporated.

[0012]

[Means for Solving the Problems] First, in a thin film multilayer wiring substrate formed by alternately laminating conductive layers and interlayer insulating layers on the substrate and connecting the conductive layers to each other. A power source layer of the conductive layers and a ground layer electrically separated from the power source layer are formed on the same substrate, and connected to the ground layer through an opening formed on the ground layer. And a pad layer electrically separated from the upper ground layer, the upper ground layer being formed on the uppermost interlayer insulating layer. In the thin film multilayer wiring board according to the first invention, at least two signal layers are formed in different layers between the power supply layer and the ground layer and the upper ground layer. Achieved by the third The area including the opening covered with the upper ground layer is a mounting area of a semiconductor chip, which is achieved by the thin-film multilayer wiring board according to the first or second invention, and fourthly, In a thin-film multilayer wiring board having conductive layers and interlayer insulating layers alternately stacked on a substrate and connecting the conductive layers to each other, the capacitor section is formed on the substrate. A thin film comprising a power supply layer, a capacitance insulation film including a metal insulation film formed by oxidizing or nitriding a metal film on the power supply layer, and a ground layer formed on the capacitance insulation film. Achieved by multi-layer wiring board, 5th
And a conductive member having a slower rate of oxidation or nitridation than the metal film is used as the power supply layer.
A sixth aspect of the present invention is achieved by a thin film multilayer wiring board, and sixthly, by alternately laminating conductive layers and interlayer insulating layers on the board,
In a thin-film multilayer wiring board that is made by connecting the conductive layers to each other and has a built-in capacitor, the capacitor section oxidizes or nitrides a ground layer formed on the board and a metal film on the ground layer. And a power supply layer formed on the capacitance insulating film, and a thin film multilayer wiring board, and seventhly, as the ground layer, The thin film multilayer wiring board according to the sixth invention is characterized in that a conductive member whose oxidation or nitriding rate is slower than that of the metal film is used. Eighth, in the thin film multilayer wiring board, the ground layer An upper ground layer connected to the ground layer through an opening formed above and a conductive film formed in the opening, and electrically separated from the upper ground layer. A pad layer is formed on the uppermost interlayer insulating layer, which is achieved by the thin film multilayer wiring board according to the fourth, fifth, sixth or seventh invention, and ninthly, 9. The thin-film multilayer according to the eighth invention, wherein at least two signal layers are formed in different layers between the power supply layer or the ground layer and the upper ground layer and the pad layer. Tenthly, the thin film multilayer wiring according to the eighth or ninth invention, wherein the region including the opening, which is achieved by the wiring substrate and is covered with the upper ground layer, is a mounting region of a semiconductor chip. Achieved by the substrate, eleventh, third or tenth
According to another aspect of the present invention, there is provided a semiconductor device in which the semiconductor chip is mounted in a semiconductor chip mounting region of the thin film multilayer wiring substrate.

[0013]

In the thin-film multilayer wiring board of the present invention, since the power supply layer and the ground layer are formed on the same board, the number of layers is reduced compared to the conventional case where they are formed separately on different interlayer insulating layers. It can be reduced by one layer. In addition, the pad layer is formed in a non-formation region of the ground layer extending on the uppermost interlayer insulating layer. Therefore, since a special region for forming the pad layer is not required, high density can be maintained.

Further, since the ground layer is formed in the surface region on the interlayer insulating layer except the pad layer forming region and the power source layer is formed on the substrate side, the signal layer is sandwiched between the power source layer and the ground layer. It can be a stripline structure which is a different structure. Therefore, the power layer and the ground layer shield the signal layer from external noise. Moreover, since at least two signal layers are formed as different signal layers, the wiring between the signal layers can be facilitated, and the wiring density can be increased.

Further, since the power supply layer and the ground layer of the conductive layers laminated on the substrate are formed as adjacent conductive layers, the thin film capacitor connected between the positive terminal of the power supply and the ground terminal is connected to the thin film multilayer wiring board. It can be easily formed inside. Further, the capacitive insulating film is formed by oxidizing or nitriding the metal film. An insulating film or the like using, for example, thermal oxidation or anodic oxidation as the oxidation or the like is dense and has few pinholes. Further, when a thicker film is required, another insulating film, for example, a polyimide film or the like can be directly formed by coating without performing a photolithography process after oxidation. Therefore, since the generation of particles can be reduced, the generation of pinholes in other insulating films can be suppressed. This makes it possible to improve yield and reliability.

A silicon oxide film formed by thermal oxidation of a Ta ₂ O ₅ film, a polyimide film, a polysilicon film or the like as a capacitive insulating film, or a silicon nitride film formed by thermal nitridation of a polysilicon film or the like. Membranes can be used. Further, a semiconductor device can be manufactured by mounting the semiconductor chip on the mounting region of the semiconductor chip including the opening covered by the upper ground layer of the thin film multilayer wiring board.

In this semiconductor device, the heat generated by the application of electric power is dissipated to the substrate side, the external noise is prevented from reaching the signal layer by the power supply layer and the ground layer, and accurate signal processing can be performed.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. (1) Description of Thin-Film Multilayer Wiring Board and Semiconductor Device of First Embodiment FIG. 2C is a sectional view showing a thin-film multilayer wiring board according to an embodiment of the present invention. FIG. 3 is a plan view and FIG.
FIG. 4 is a sectional view taken along line AA of FIG. 3.

As shown in FIG. 2C, a power supply layer (conductivity of the first layer Cr film / Cu film / Cr film is formed on the insulating substrate 21 made of glass or ceramic or the substrate 21 made of silicon. The layer 22 is formed continuously or in a mesh shape over a wide range. Also, the same substrate 2
The power supply layer 22 is removed in the region on which the thermal via hole (opening) 30 is to be formed, and the ground layer (conductive layer) electrically separated from the power supply layer 22 in the non-formation region. 23 is formed.

Reference numeral 24b is a second signal layer (conductive layer) formed on the power supply layer 22 with an interlayer insulating layer 28a made of a polyimide film having a thickness of about 25 μm interposed therebetween. Also, 24a
Is a second connection power supply layer (conductive layer) of the second layer formed on the power supply layer 22 via an interlayer insulating layer 28a made of a polyimide film having a film thickness of about 25 μm. The via hole 29a is formed in the interlayer insulating layer 28a on the power supply layer 22, and the first connection power supply layer is formed.
24a is connected to the power supply layer 22 through the via hole 29a. Further, a thermal via hole 30 is formed in the interlayer insulating layer 28a on the ground layer 23, and the thermal via hole 3 is formed.
The first metal layer 24c connected to the ground layer 23 through 0
Are formed.

25b is a film thickness of about 25 μ on the first signal layer 24b.
The second signal layer (conductive layer) of the third layer is formed via the interlayer insulating layer 28b made of a polyimide film of m. Further, 25a is a second connection power supply layer (conductive layer) of the third layer formed on the same interlayer insulating layer 28b. A via hole 29b is formed in the interlayer insulating layer 28b on the first connection power supply layer 24a, and the second connection power supply layer 25a is connected to the first connection power supply layer 24a via the via hole 29b. First signal layer 24
b and the second signal layer 25b are formed to intersect with each other so as not to overlap as much as possible in order to reduce the parasitic capacitance. Further, a thermal via hole 30 is formed in the interlayer insulating layer 28b on the first metal layer 24c on the ground layer 23,
A second metal layer 25c connected to the first metal layer 24c on the ground layer 23 via the thermal via hole 30 is formed.

Reference numeral 26 is a fourth pad layer (conductive layer) formed on the second connection power supply layer 25a and the second signal layer 25b via an interlayer insulating layer 28c made of a polyimide film having a thickness of about 25 μm. ). Interlayer insulating layer 28 on the second signal layer 25b
A via hole is formed in c, and the pad layer 26 is connected to the second signal layer 24b via the via hole. Further, as shown in FIG. 3, adjacent pad layers are arranged in a zigzag pattern. This allows more signal layers to pass through between the adjacent pad layers. At this time, even more signal layers can be passed through by forming the via holes in the pad layer in a different direction from the via holes in the adjacent pad layer.

Further, the second metal layer 25 on the ground layer 23
A thermal via hole 30 is formed in the interlayer insulating layer 28c on the ground layer 2c via the thermal via hole 30.
A third metal layer 26a connected to the second metal layer 25c on the upper part 3 is formed. The third metal layer 26a is an interlayer insulating layer.
28c and is electrically separated from the pad layer 26 as an upper ground layer to be electrically connected to the interlayer insulating layer 28 around the pad layer 26.
Cover c.

Further, the third metal layer 26 on the interlayer insulating layer 28c
The area above the a and including the thermal via hole 30 becomes the die pad area 31. The IC chip is placed on the die pad region 31 via a conductive resin (conductive member), and the conductive resin and the first to third metal layers 24c, 25c, 26 are placed.
It is connected to the ground layer 23 via a. And IC
The heat generated by the operation of the chip is transmitted through the conductive resin and the first to third metal layers 24c, 25c and 26a to the substrate 2
Conduct to the 1 side and dissipate.

In the above thin film multilayer wiring board, the first
The signal layer 24b and the second signal layer 25b of the
Different layers are formed by a conductive layer composed of a Cu film / Cr film. Therefore, the wiring between the mutual signal layers 24b and 25b can be facilitated and the density can be increased. Furthermore,
An IC chip is mounted on a die pad region including the thermal via hole 30 covered by the upper ground layer 26a of the above-mentioned thin film multilayer wiring board to form a semiconductor device, and heat generated by the application of power is dissipated to the substrate 21 side, and a power supply layer is formed. 22 and the upper ground layer 26a prevent external noise from reaching the signal layer, and can perform accurate signal processing.

Further, the first signal layer 24b and the second signal layer
By properly designing the line width of 25b and the film thickness of the interlayer insulating layers 28a and 28b between these signal layers and the ground layer 26a or the power supply layer 22, the first signal layer 24b and the second signal layer
Signals can be efficiently transmitted at high speed by matching the characteristic impedance by a distributed constant circuit formed between 25b and the ground layer 26a or the power supply layer 22.

Polyimide is used as a material for the interlayer insulating layers 28a to 28c, and particularly the via holes 29a to 29 are used.
Photosensitive polyimide is used to directly perform patterning for forming d and the thermal via hole 30.
Next, with reference to FIGS. 1 (a) to 1 (d) to 2 (a) to 2 (c), a method for producing the above-mentioned thin film multilayer wiring board will be described. 1A to 1D and FIGS. 2A to 2C are cross-sectional views showing a method for producing a thin film multilayer wiring board.

First, as shown in FIG. 1A, a Cr film having a film thickness of about 0.1 μm, a Cu film having a film thickness of about 5 μm, and a film thickness of about 0.1 are formed on a substrate 21 made of silicon, glass or ceramics.
A 2 μm Cr film is sequentially formed by a plating method or a sputtering method. Then, by a photolithography technique using a mask and a dry etching technique, Cr film / Cu film /
By patterning the three conductive layers of the Cr film, the same substrate 2
The power supply layer 22 is formed on the first layer 1, and the ground layer 23 electrically separated from the power supply layer 22 is formed in a region where the power supply layer 22 is not formed.

Next, as shown in FIG. 1B, a photosensitive polyimide is applied by a spin coating method and heat-treated to form an interlayer insulating layer 28a having a film thickness of about 25 μm. Then, the power supply layer 22 is formed by a photolithography technique using an exposure mask.
Interlayer insulating layer 28a on the upper and ground layers 23 at necessary locations
After forming the opening, the polyimide on the upper edge of the opening is contracted by heating to form the via hole 29a and the thermal via hole 30 in which the entrance of the opening is widened.

Then, as shown in FIG. 1C, a Cr film having a film thickness of about 0.1 μm, a Cu film having a film thickness of 3 to 5 μm, and a Cr film having a film thickness of about 0.2 μm are formed by a plating method or a sputtering method.
Three conductive layers of the film are sequentially formed on the interlayer insulating film 28a.
Subsequently, the conductive layer is patterned, and the strip-shaped first connection power supply layer 24a is connected to the power supply layer 22 through the via hole 29a.
And a band-shaped first signal layer 24b separated from the first connection power supply layer 24a, and the thermal via hole 3 is formed.
The first metal layer 24c connected to the ground layer 23 through 0
To form.

Next, as shown in FIG. 1D, a photosensitive polyimide is applied by a spin coating method and heat-treated to form an interlayer insulating layer 28b having a film thickness of about 25 μm. Then, after forming an opening in the interlayer insulating layer 28b at a necessary position on the first connection power supply layer 24a and the first metal layer 24c by a photolithography technique using a mask, the opening is formed by heating. A via hole 29b and a thermal via hole 30 having a wide entrance are formed.

Then, as shown in FIG. 2A, a Cr film having a film thickness of about 0.1 μm, a Cu film having a film thickness of 3 to 5 μm, and a Cr film having a film thickness of about 0.2 μm are formed by a plating method or a sputtering method.
Three conductive layers of the film are sequentially formed on the interlayer insulating film 28b.
Subsequently, the conductive layer is patterned, and the band-shaped second connection power supply layer 25a connected to the first connection power supply layer 24a through the via hole 29b and the second signal layer separated from the second connection power supply layer 25a. 25b, and a second metal layer 25c connected to the first metal layer 24c on the ground layer 23 via the thermal via hole 30 is formed.

Next, as shown in FIG. 2B, photosensitive polyimide is applied by a spin coating method and heat-treated to form an interlayer insulating layer 28c having a film thickness of about 25 μm. Then, the second signal layer 25 is formed by a photolithography technique using a mask.
Interlayer insulating layer at a required position on the second metal layer 25c and on the second metal layer 25c
After forming the opening in 28c, heating is performed to form a via hole and a thermal via hole 30 in which the entrance of the opening is widened.

Then, as shown in FIG. 2 (c), a film thickness of approximately about 20 is formed on the interlayer insulating film 28c by a plating method or a sputtering method.
After a Cr film of 0.1 μm, a Cu film of 3 to 5 μm and a Cr film of about 0.2 μm are sequentially formed, a Ni film of about 2 μm and an Au film of about 1 μm are partially plated. Form sequentially. Subsequently, patterning is performed to form a rectangular pad layer 26 connected to the second signal layer 25b through the via hole, and the ground layer 23 is formed through the via hole.
A third metal layer 26a connected to the second metal layer 25c above and separated from the pad layer 26 and extending around the pad layer 26.
Are formed on the interlayer insulating layer 28c. The region including the thermal via hole 30 on the third metal layer 26a on the interlayer insulating layer 28c becomes the die pad region 31.

After that, an IC chip is placed on the die pad region 31 via a conductive resin (conductive member), and wire bonding is performed on a necessary pad layer to complete a semiconductor device. In this semiconductor device, the IC chip is connected to the ground layer 23 via the conductive resin and the first to third metal layers 24c, 25c and 26a. Then, heat generated by the operation of the IC chip is transferred to the conductive resin and the first
~ Conducting to the substrate 21 side through the third metal layers 24c, 25c, 26a, and dissipating.

As described above, according to the first embodiment, as shown in FIG. 2C, since the power supply layer 22 and the ground layer 23 are formed on the same substrate 21, different interlayer insulation is performed. The number of layers is 1 compared to the conventional method in which layers are formed separately.
Layers can be reduced. Therefore, it is possible to improve the manufacturing yield and reliability with the reduction of the number of manufacturing steps of the thin-film multilayer wiring board, and it is possible to reduce the manufacturing cost by reducing the number of manufacturing steps and materials.

The pad layer 26 is the uppermost interlayer insulating layer.
It is formed in the non-formation region of the upper ground layer 26a extending on 28c. Therefore, a special region for forming the pad layer 26 is not required, so that the high density can be maintained. Further, since the surface region on the interlayer insulating layer 28c other than the formation region of the pad layer 26 is covered with the upper ground layer 26a and the substrate 21 side is covered with the power supply layer 22, the signal layers 24b and 25b are connected to the power supply layer 22. And ground layer 23
It may be a stripline structure sandwiched between.
Therefore, the signal layer 24 is formed by the power supply layer 22 and the ground layer 23.
b and 25b are shielded from external noise. This increases the reliability of signal transmission in a circuit using this thin film multilayer wiring board.

Further, since the power supply layer 22 and the ground layer 23 are formed as adjacent conductive layers, a thin film capacitor 45 connected between the positive terminal of the power supply and the ground terminal, which will be described next, can be easily provided in the thin film multilayer wiring board. Can be built into. (2) Description of Thin-Film Multilayer Wiring Board of Second Embodiment FIG. 6A is a sectional view showing a thin-film multilayer wiring board of the second embodiment. The difference from the first embodiment is that the substrate 21 has a built-in thin film capacitor 45 and the power supply layer 22
That is, the ground layer 41 formed on the same substrate 21 as above is not formed on the same substrate 21 but is formed further below the power supply layer 22. As a result, the thin film capacitor 45 having the power supply layer 22 and the ground layer 41 as counter electrodes can be built in, and the equivalent circuit shown in FIG.
As shown in (b), the thin film capacitor 45 is connected between the positive terminal of the power supply and the ground terminal. Note that FIG. 6 (a)
In the figure, the same reference numerals as those in FIG. 2C indicate the same elements as those in FIG. 2C. In the second embodiment of the thermal via hole, as shown in FIG.
A TaN film 41 having a film thickness of about 1 to 3 μm and a film thickness of about 0.3 to
A Ta ₂ O ₅ film 42 having a thickness of 1 μm and a polyimide film 43 having a thickness of about 0.3 to 1 μm are sequentially formed. Further, the power supply layer 22 is formed on the polyimide film 43. Power layer 2
The layers above 2 have the same structure as the structure shown in the first embodiment.

According to the above, the TaN film 41 and the power supply layer 2
2 has a function as an electrode of the thin film capacitor 45, and the Ta ₂ O ₅ film 42 and the polyimide film 43 have a function as a capacitance insulating film 44. The thin film capacitor 45
The TaN film 41 having a function as an electrode on one side also has a function as a ground layer. Therefore, it is connected to the uppermost upper ground layer 26a.

In the above-described thin film capacitor 45, the Ta ₂ O ₅ film 42 as the capacitance insulating film 44 can be formed by thermal oxidation or anodic oxidation of the Ta film 42a, so that the film quality is fine and the inter-electrode between pin holes is formed. It is possible to prevent a short circuit. This improves the manufacturing yield and reliability of the thin film multilayer substrate. Next, FIGS. 4A to 4D and FIG.
A method of manufacturing the thin film multilayer substrate of the second embodiment will be described with reference to (a) and (b). 4 (a)-
6D, FIG. 5A, and FIG. 5B are enlarged cross-sectional views of the portion B of FIG. 6A.

First, as shown in FIG. 4A, a TaN film (ground layer) 41 having a film thickness of about 1 to 3 μm and a Ta film 42a having a film thickness of about 0.3 to 1 μm are sequentially formed on a substrate 21 by a sputtering method. To do. Then, as shown in FIG. 4B, the Ta film 42a is formed in an oxygen atmosphere at a temperature of 500 to 600 ° C.
Oxidize. At this time, the base of the Ta film 42a is the TaN film 4
Since it is 1, the Ta ₂ O ₅ film 42 is hardly oxidized and almost only the Ta film 42a is oxidized even if it is slightly excessively oxidized.
Is formed. Therefore, the film thickness of the Ta ₂ O ₅ film 42 is Ta
It depends on the initial thickness of the film 42a. Therefore, the film thickness can be accurately controlled.

Then, as shown in FIG. 4 (c), Ta ₂
A polyimide film 43 having a film thickness of about 0.3 to 1 μm is formed on the O ₅ film 42 by a spin coating method. Next, as shown in FIG. 4D, a Cr film / Cu film / Cr film is sequentially formed on the polyimide film 43 by a sputtering method or a plating method, and then patterned to form a Cr film / Cu film / Cr film. The opening 46 is formed. The remaining Cr film / Cu film / Cr film becomes the power supply layer 22.

Next, as shown in FIG. 5A, a photosensitive polyimide is applied by a spin coating method and heat-treated to form an interlayer insulating layer 28a having a film thickness of about 25 μm. Then, using the photolithography technique using the exposure mask, the Cr film /
An opening having a smaller diameter than the opening 46 of the Cr film / Cu film / Cr film is formed in the interlayer insulating layer 28a on the opening 46 of the Cu film / Cr film. Further, a via hole 29a is formed in the interlayer insulating layer 28a on the power supply layer 22.

Subsequently, the polyimide film 43 and the Ta ₂ O ₅ film 42 are etched and removed through the opening to form an opening, and the TaN film 41 is exposed at the bottom of the opening. Then
The polyimide film 43 on the upper edge of the opening is heated.
Is contracted to form a thermal via hole 30 having a wide opening. Next, the thermal via hole 30 and the via hole 29a are sequentially covered to form a Cr film / Cu film / Cr film, which is then patterned to form the first metal layer 24c connected to the ground layer 41, and Signal layer
24a is formed.

After that, through the same steps as those in the first embodiment,
As shown in FIG. 6A, a thin film multilayer wiring board having the thin film capacitor 45 built therein is formed. After that, an IC chip is placed on the die pad region 31 including the thermal via hole 30 covered with the upper ground layer 26a through a conductive resin (conductive member), and wire bonding is performed on a necessary pad layer to complete a semiconductor device. To do.

As described above, according to the second embodiment, T
The capacitive insulating film 44 is formed by thermally oxidizing the a film 42a. The thermal oxide film (Ta ₂ O ₅ film) 42 is dense and has few pinholes. Further, after thermally oxidizing the Ta film 42a, polyimide is applied without passing through a photolithography process. Therefore, since the generation of particles can be reduced, the generation of pinholes in the polyimide film 43 can be suppressed.

When an IC chip is mounted on the die pad region 31 to operate as a semiconductor device, the thin film capacitor 45 prevents ground bounce from the power source,
The IC chip and the circuit can be protected. In the second embodiment, the polyimide film 43 formed by the coating method and the Ta ₂ O ₅ film 42 formed by thermal oxidation are used as the capacitive insulating film 44, but other insulating films such as It is also possible to use a silicon oxide film formed by thermal oxidation of a polysilicon film or the like, or a silicon nitride film formed by thermal nitridation of a polysilicon film or the like.

Besides the thermal oxidation, it is also possible to form the capacitive insulating film by thermally nitriding the metal film. Further, as the oxidation method or the like, anodic oxidation or another oxidation method may be used.

[0049]

As described above, in the thin film multilayer wiring board of the present invention, since the power supply layer and the ground layer are formed on the same board, the number of layers is reduced and the number of manufacturing steps is reduced. The yield and reliability can be improved, and the manufacturing cost can be reduced by reducing the number of manufacturing steps and materials.

Further, since the pad layer is formed in the non-formed region of the ground layer extending on the uppermost interlayer insulating layer, even if it is formed on the interlayer insulating film common to the ground layer, a special region is formed. It is possible to maintain high density without requiring. Furthermore, since the ground layer is formed on the uppermost interlayer insulating layer and the power supply layer is formed on the substrate side, a stripline structure can be obtained. Therefore, the power supply layer and the ground layer allow the signal layer to be external. Shielded from noise. This increases the reliability of signal transmission in a circuit using this thin film multilayer wiring board.

Further, since at least two signal layers having different layers are formed as the signal layers, wiring connection between the signal layers can be facilitated, and wiring density can be increased. Further, among the conductive layers laminated on the substrate, the power supply layer and the ground layer are formed as adjacent conductive layers, so that a thin film capacitor connected between the positive terminal of the power supply and the ground terminal can be easily installed in the thin film multilayer wiring board. Can be formed.

Further, the capacitive insulating film is formed by thermally oxidizing or thermally nitriding the metal film. The thermal oxide film, etc. is dense and has few pinholes. Furthermore, when a thicker film is required, another insulating film can be directly formed after the thermal oxidation or the like without a photolithography process.
Therefore, the generation of particles can be reduced and the generation of pinholes in other insulating films can be suppressed. This makes it possible to improve yield and reliability.

Further, the semiconductor chip is mounted on a mounting area of the semiconductor chip including the opening covered with the upper ground layer of the thin film multilayer wiring board to form a semiconductor device, and heat generated in the semiconductor chip by applying power is removed. Dispersed to the board side,
With the power supply layer and the ground layer, it is possible to prevent external noise from reaching the signal layer and perform accurate signal processing.

[Brief description of drawings]

FIG. 1 is a cross-sectional view (No. 1) showing a method of manufacturing a thin-film multilayer wiring board according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view (No. 2) showing the method of manufacturing the thin-film multilayer wiring board according to the first embodiment of the present invention.

FIG. 3 is a plan view showing a thin-film multilayer wiring board according to a first embodiment of the present invention.

FIG. 4 is a cross-sectional view (No. 1) showing the method of manufacturing the thin-film multilayer wiring board according to the second embodiment of the present invention.

FIG. 5 is a sectional view (No. 2) showing the method of manufacturing the thin-film multilayer wiring board according to the second embodiment of the present invention.

FIG. 6 is a sectional view showing a thin-film multilayer wiring board according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a thin film multilayer wiring board according to a conventional example.

FIG. 8 is a sectional view showing a thin-film multilayer wiring board according to another conventional example.

[Explanation of symbols]

21 substrate, 22 power supply layer (conductive layer), 23 ground layer (conductive layer), 24a first connection power supply layer (conductive layer), 24b first signal layer (conductive layer), 24c first metal layer, 25a 2nd connection power supply layer (conductive layer), 25b 2nd signal layer (conductive layer), 25c 2nd metal layer, 26 pad layer (conductive layer), 26a 3rd metal layer (conductive layer; upper ground layer) ), 28a to 28c interlayer insulating layer, 29a to 29d via hole, 30 thermal via hole (opening), 31 die pad region, 41 TaN film (ground layer), 42 Ta ₂ O ₅ film, 43 polyimide film, 44 capacitance insulating film, 45 Thin film capacitor, 46 apertures.

Claims (11)

[Claims] 1. A thin film multilayer wiring board produced by alternately stacking conductive layers and interlayer insulating layers on a substrate and connecting the conductive layers to each other. A power layer and a ground layer electrically separated from each other are formed on the same substrate, an upper ground layer connected to the ground layer through an opening formed on the ground layer, and the upper ground layer. A thin film multi-layer wiring substrate, wherein an electrically separated pad layer is formed on the uppermost interlayer insulating layer. 2. The thin-film multilayer wiring according to claim 1, wherein at least two signal layers are formed in different layers between the power supply layer and the ground layer and the upper ground layer. substrate. 3. The thin-film multilayer wiring board according to claim 1, wherein a region including the opening, which is covered with the upper ground layer, is a semiconductor chip mounting region. 4. A thin-film multilayer wiring board having a built-in capacitor, which is produced by alternately stacking conductive layers and interlayer insulating layers on a substrate and connecting the conductive layers to each other, wherein the capacitor portion is the substrate. A power supply layer formed on the power supply layer, a capacitance insulation film including a metal insulation film formed by oxidizing or nitriding a metal film on the power supply layer, and a ground layer formed on the capacitance insulation film. A thin-film multilayer wiring board characterized by: 5. The thin-film multilayer wiring board according to claim 4, wherein a conductive member whose oxidation or nitriding speed is slower than that of the metal film is used as the power supply layer. 6. A thin-film multilayer wiring board having a built-in capacitor, which is produced by alternately stacking conductive layers and interlayer insulating layers on a substrate and connecting the conductive layers to each other, wherein the capacitor section is the substrate. A ground insulating layer formed on the ground layer, a capacitance insulating film including a metal insulating film formed by oxidizing or nitriding a metal film on the ground layer, and a power supply layer formed on the capacitance insulating film. A thin-film multilayer wiring board characterized by: 7. The thin-film multilayer wiring board according to claim 6, wherein a conductive member whose oxidation or nitridation rate is slower than that of the metal film is used as the ground layer. 8. In the thin film multilayer wiring board, an upper ground layer connected to the ground layer through an opening formed on the ground layer, and a pad layer electrically separated from the upper ground layer. 8. The thin film multilayer wiring board according to claim 4, claim 5, claim 6, or claim 7, wherein is formed on the uppermost interlayer insulating layer. 9. At least two layers are provided between the power supply layer or the ground layer and the upper ground layer and the pad layer.
9. The thin film multilayer wiring board according to claim 8, wherein the signal layers of the layers are formed in different layers. 10. The thin-film multilayer wiring board according to claim 8, wherein the region including the opening, which is covered with the upper ground layer, is a mounting region of a semiconductor chip. 11. A semiconductor device in which the semiconductor chip is mounted in a mounting region of the semiconductor chip of the thin-film multilayer wiring board according to claim 3 or 10.