JPH1145977A - Multichip module and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the development time and the manufacturing time of a multichip module having excellent high frequency characteristics, by forming the multichip module of laminated structure by the three layers of a top-face sealed substrate, a passive-element substrate and an active-element substrate. SOLUTION: A multichip module 1 is formed in the laminated structure of a top-face sealed substrate 2, a passive-element substrate 3 and an active- element substrate 4. The top-face sealed substrate 2 is formed in structure having a first insulating layer 6 and first adhesive layer 7 on the rear of a metal plate 5, and a hollowed-out region 8 is formed to parts of the first insulating layer 6 and the first adhesive layer 7. An inert gas is sealed into the hollowed-out region 8, and a sealing film 30 is formed onto a side face. Since each substrate-forming temperature condition is determined discretely by forming the top-face sealed substrate 2, the passive-element substrate 3 and the active- element substrate 4 by separate process respectively in the multichip module 1, the constraint of each substrate-forming temperature condition is reduced, and the substrates are manufactured easily.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module and a method of manufacturing the same, and more particularly, to a multi-chip module having a small size, excellent high-frequency characteristics and low power consumption, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Barrier chip components (various chip-shaped bare chip components having desired functions, ICs, and surface acoustic wave devices) are one means for miniaturizing and improving the performance of electronic devices.
(SAW) is collectively referred to as a bare chip component in this specification.)
A so-called multi-chip module is used in which a plurality of various passive elements such as a resistor, a capacitor and a coil are connected to each other to form one module.

As a means of reducing the thickness, increasing the density, and reducing the cost of a printed wiring board, a laminate is individually formed for each wiring layer, and a plurality of the laminates are laminated in a multilayer structure. A so-called build-up substrate is used to form a multilayer substrate.

For example, Conventional Example 1 (5th Microelectronics Symposium, June 1993, p. 123)
Describes a structure in which an epoxy resin film is applied to the entire surface on a glass epoxy substrate with a thin film resistor formed on the surface, a thin film capacitor and an IC chip are formed on this epoxy resin film, and they are connected to each other by multilayer wiring. Has been
The IC chip is connected face down (electrical connection is performed on the chip surface on the substrate side).

In the prior art 2 (Japanese Patent Laid-Open No. 5-47856), a package such as a ceramic printed board is provided with a plurality of stages (recesses), and a bare chip component is mounted in this stage by eutectic bonding or conductive bonding. Face-up (electrical connection is made on the chip surface opposite to the substrate) using a conductive adhesive, and an insulating film such as polyimide is formed on the entire surface of the package and bare chip parts by spin coating A structure in which connection surfaces formed on the surface of the package and pads on the upper surface of the bare chip component are connected to each other by a wiring pattern provided on the insulating film is described.

[0006] Further, in Conventional Example 3 (10th, Circuit Packaging Academic Lecture Meeting, March 1996, p. 81), a conductive polyimide paste was prepared by using a copper polyimide film with a thermoplastic polyimide adhesive as a substrate material. Describes a multi-layering process in which interlayers are connected by vias filled with, and a polyimide film multilayer substrate is constructed by batch lamination.

[0007]

In a multi-chip module in which a plurality of passive elements and bare chip parts are mounted on a substrate, a thin and small passive element is mounted, and the heat dissipation efficiency of a semiconductor chip with large power consumption is improved. Is a major issue.

For example, one of the conventional typical methods for forming a dielectric film of a capacitor is to form an SiO ₂ film at room temperature by using an ECR-CVD method as described in the above-mentioned prior art example 1. It is a method of forming. However, in this method, since the relative dielectric constant of the SiO ₂ film is small, a capacitor requiring a large capacitance such as a bypass capacitor has a large area (for example, 1 mm ² / 130p for a SiO ₂ film).
F).

As a dielectric film capable of obtaining a high dielectric constant, an STO (SrTiO ₃ ) film or the like is known, and is formed by a sputtering method or the like. However, since such a film needs to have a temperature at the time of film formation of about 200 to 350 ° C., it cannot be formed on an epoxy substrate, and has a heat-resistant temperature higher than the temperature at the time of film formation. For example, it is formed on an insulating film of an organic material or an inorganic material such as a polyimide resin having a heat resistance temperature of 350 ° C. or higher.

On the other hand, in the conventional mounting structure of a bare chip component by face-up, in which electrical connection is made on the upper surface of the bare chip component, as described in the above-mentioned conventional example 2, the package is made of an insulating substrate such as ceramic. Is used. However, generally, an insulating substrate has a thermal conductivity that is lower by one digit or more than a conductor and a semiconductor.
The generated heat cannot be effectively radiated to the outside through the substrate, and is not suitable for mounting a power amplifier or the like having a high output and a large power loss. Further, since the eutectic bonding or conductive adhesive layer on the back surface of the bare chip component is not electrically connected to the wiring pattern and the base is an insulator, a stable circuit operation in a high frequency region can be obtained. Absent.

As described above, in the conventional multi-chip module, since the dielectric constant of the dielectric film of the capacitor is small,
When a large-capacity capacitor such as a bypass capacitor is required, the required area of the capacitor becomes large, and the module becomes large. Further, when an insulating substrate is used as a package, there are problems such as low heat radiation performance and unstable circuit operation in a high frequency region.

An object of the present invention is to solve the above-mentioned conventional problems, to reduce the required area of a capacitor or the like, to obtain a sufficiently high heat radiation performance and to obtain a stable circuit operation in a high frequency region, and to provide such a multi-chip module. It is an object of the present invention to provide a build-up type multi-chip module manufacturing method capable of reducing module development time and manufacturing time.

[0013]

In order to achieve the above object, a multichip module according to the present invention comprises a top shield substrate having a metal plate and a passive element substrate having at least a resistor, a capacitor and a coil. A bare chip component, and a laminated structure with an active element substrate in which the bare chip component is arranged at least face up on a ground conductor layer formed on a base substrate. .

That is, in the present invention, the first insulating layer of the upper shield substrate has a hollow structure in a region corresponding to a coil forming region formed on the surface of the passive element substrate. Therefore, the coil formed on the surface of the passive element substrate can obtain good high-frequency characteristics by covering the surface with an inert gas having a dielectric constant close to that of air.

The passive element substrate may include a plurality of thin-film-shaped resistors and capacitors connected to the second insulating layer and the third insulating layer.
And a plurality of coils having a spiral shape are provided on the third insulating layer.
Therefore, since the various passive elements formed on the passive element substrate can be formed thin and small, the passive elements between the inter-substrate connection electrode provided on the lower surface of the second insulating layer of the passive element substrate and the various passive elements and the various passive elements can be formed. The wiring between the passive elements is shortened, which is also advantageous for high frequency characteristics.

Further, the active element substrate is provided with S
An i-wafer or a metal plate is used, a ground conductor layer is provided on the surface of the base plate, and a plurality of bare chip components are mounted face-up on the ground conductor layer using a conductive material. The bear chip component is embedded with a fourth insulating layer made of an insulating resin up to the electrode surface height of the bare chip component, and has a structure in which electric connection posts are formed inside the base plate and inside the fourth insulating layer, respectively. Metal plate or S as the base substrate
By using i, the thermal conductivity can be made much larger than that of the insulating substrate, which is extremely preferable for dissipating heat from the bare chip component. Further, since the bare chip component is mounted face-up on the ground conductor layer using a conductive material, it is advantageous in improving high frequency characteristics.

Further, a part of the signal connection post and the power supply post of the electric connection post inside the base plate are formed inside the electrode insulating layer made of insulating resin, and the electric connection inside the fourth insulating layer is formed. Since the structure is electrically connected to the post, the signal line post and the power supply line post are insulated and separated from the base plate.

Further, another portion of the electrical connection post inside the base plate, that is, a post for a ground wire, is formed inside an electrode insulating layer made of an insulating resin, and is electrically connected to the ground conductor layer. . Therefore, the post for the ground line can be formed simultaneously with the post for the signal line and the post for the power supply line.

Further, external electrodes are formed on the base plate surface on the back surface of the active element substrate and the electric connection post surface inside the base plate, respectively. For this reason, the multichip module of the present invention facilitates bonding of the ground line and the signal line to the motherboard on which they are mounted, and is advantageous for improving the heat conduction performance to the motherboard and improving the high frequency characteristics.

Further, the multi-chip module has a hermetic seal structure in which all side surfaces are covered with a shield film. Therefore, the metal plate of the upper shield substrate, the external electrodes on the back surface of the active element substrate, and the side shield film form a six-side shield structure, which is advantageous for improving high frequency characteristics.

The above-mentioned upper shield substrate, passive element substrate and active element substrate are processed in different processes, respectively, and thereafter, a predetermined layer arrangement, ie, an upper layer shield substrate in the upper layer, a passive element substrate in the middle layer, and an active element substrate in the lower layer are arranged. Are formed in a laminated structure by predetermined alignment. Therefore, the manufacturing period of each substrate can be shortened, and the design can be easily changed.

The above-mentioned upper shield substrate is a single-sided metal-plated laminated plate, and the first insulating layer and the adhesive layer are cut out by etching using a region corresponding to a coil forming region formed on the surface of the passive element substrate. Processing. Therefore, by laminating the upper shield substrate on the passive element substrate, the upper surface and side surfaces of the coil can be covered with an inert gas or the like.

In the passive element substrate, a plurality of resistors and capacitors are formed in a desired shape by a known thin film processing on a second insulating layer made of insulating resin, and a plurality of resistors and capacitors are formed on a third insulating layer made of insulating resin. Are formed by a combination of a thin film processing method and a plating method. A wiring pattern of a predetermined shape is formed on each of the inner layer and the front surface of the passive element substrate, and a wiring pattern of a predetermined shape, an interlayer connection electrode, and an adhesive layer are formed on the back surface of the passive element substrate. The interlayer connection electrodes are electrically connected by electrode posts.

If an organic polymer resin film such as a polyimide film is used as the second insulating layer, a resistor made of a WSiN film or the like and a capacitor made of a high-dielectric film such as STO can be used at 200 to 350 ° C. It is preferable because a film can be formed.

In the active element substrate, an Si substrate or a metallic substrate is used as a base substrate material, an earth conductor layer is provided on the surface thereof, and a plurality of bare chip parts are faced on the earth conductor layer using a conductive material. A fourth insulating layer made of an insulating resin is formed flat by a curtain coating method up to the electrode surface height of the bare chip component. This allows the base substrate to be used as a radiator for the bare chip component. Further, since the bare chip component is mounted on the ground conductor layer using a conductive material, it is preferable in terms of the high frequency performance of the bare chip component. Furthermore, by laminating the fourth insulating layer flat and exposing the electrode surface of the bare chip component to the same surface height, lamination with the active element substrate becomes easy.

The base substrate is provided with through holes for electrical connection posts in advance by an etching method, an insulating material made of an insulating resin is sealed therein, and a laser processing method or an etching method is applied to the insulating material. An electric connection post hole smaller than the through hole is formed, and the electric connection post is formed therein by a plating method or an embedding method. According to this processing method, it is easy to use a conductive metal plate or a semiconductive Si plate as the base substrate material.

Further, an external electrode is provided on a back surface of the base substrate, an external signal electrode is electrically insulated from the base substrate, and an external ground electrode is electrically connected to the base substrate.

As described above, the upper shield substrate, the passive element substrate, and the active element substrate formed by the respective processing means are subjected to a laminating process by a collective laminating method in an inert gas.
As a result, the inert gas can be sealed in the cutout region of the insulating layer provided on the upper shield substrate.

A laminated board having a multiplicity of multi-chip modules processed into a laminated structure covers the surface of the shield substrate and the back surface of the active element substrate with a plating-resistant resist or the like, respectively. An individual multi-chip module is cut out by cutting a scribe line provided on the external electrode pattern on the back surface of the element substrate. The cut out multi-chip module is subjected to a predetermined plating process on all the side surfaces by a plating method, and thereafter, the previously applied plating resistant resist and the like are removed. Such a multichip module of the present invention can be mass-produced simultaneously on a large substrate by batch processing, which is advantageous for cost reduction.

In the multichip module of the present invention, the passive element substrate may have a composite substrate structure. That is, a plurality of the bare chip components are mounted on the surface of the passive element substrate by flip-chip to form a composite substrate in which passive elements and active elements are mixedly mounted.

In the multichip module using the composite substrate, the first insulating layer of the upper shield substrate has a structure in which a region corresponding to a coil forming region formed on the surface of the composite substrate and a region corresponding to a mounting region of a bare chip component are hollowed out. And Therefore, the surfaces of the coil and the bare chip component can be covered with an inert gas having a dielectric constant close to air, and good high-frequency characteristics can be obtained.

In the above-mentioned composite substrate, a plurality of thin-film resistors and capacitors are provided inside the second insulating layer and the third insulating layer, and a plurality of spiral coils are provided on the third insulating layer. And a structure in which a plurality of the bare chip components are mounted on the third insulating layer by flip chips.

As the upper shield substrate, a single-sided metal-plated laminated plate is used, and the first insulating layer and the adhesive layer are mounted by flip-chip on a region corresponding to a coil forming region formed on the surface of the composite substrate and on the surface of the composite substrate. The mounting area of the bare chip component is cut out by an etching method. Therefore, by laminating the upper shield substrate on the composite substrate, the surface of the coil and the bare chip component can be covered with an inert gas or the like.

In the composite substrate, a plurality of resistors and capacitors are formed in a desired shape by a known thin film processing on a second insulating layer made of an insulating resin, and a plurality of resistors and capacitors are formed on a third insulating layer made of an insulating resin. A coil having a spiral shape is formed by a combination of a thin film processing method and a plating method, and a plurality of bare chip components are mounted by flip chips. Also, a wiring pattern of a predetermined shape is formed on each of the inner layer and the front surface of the passive element substrate, and a wiring pattern of a predetermined shape, an interlayer connection electrode, and an adhesive layer are formed on the back surface. The resistance, the capacitor, the coil, the wiring pattern, and the interlayer connection electrode are each electrically connected by an electrode post.

If an organic polymer resin film such as a polyimide film is used as the second insulating layer, a resistor formed of a WSiN film or the like and a capacitor formed of a high dielectric film such as an STO can be used at 200 to 350 ° C. It is preferable because a film can be formed. Further, it is preferable that the flip chip mounting of the bare chip component is performed at a temperature equal to or lower than various forming temperatures of the composite substrate.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a multichip module according to the present invention is formed by a three-layer structure of an upper shield substrate, a passive element substrate and an active element substrate.

The above-mentioned upper shield substrate is a layer having a first insulating layer made of epoxy or polyimide resin and a first adhesive layer made of epoxy or polyimide resin on the back surface of a metal plate made of Cu or the like. The first insulating layer and a part of the first adhesive layer are provided with a hollow region.

The passive element substrate is formed on the surface of a second insulating layer made of a high heat-resistant resin such as polyimide resin at a temperature lower than the heat-resistant temperature (for example, 350 ° C.) of the second insulating layer. A resistor made of a material (eg, WSiN film; sheet resistivity 100Ω / □, film thickness 200 nm), a capacitor made of a thin film such as STO, Cr / Cu /
A wiring layer made of Cr or the like and a third insulating layer made of an epoxy or polyimide resin are formed, and a plurality of electric wires made of a plating or paste of Cu or Ag are formed at predetermined positions of the second insulating layer. Connection posts are formed. Further, the surface of the third insulating layer is made of Cr
A wiring layer and a coil made of / Cu / Cr or the like are formed, and an interlayer electrode layer made of Cr / Cu / Cr or the like and a second adhesive made of an epoxy or polyimide resin are formed on the back surface of the second insulating layer. A layer is formed.

The active element substrate is a metal plate or Si
An earth conductor layer is formed on the surface of a base substrate made of a substrate, and a plurality of bare chip components are mounted face-up thereon using a eutectic solder such as Au / Sn or a conductive material made of a paste such as Ag. I have. Further, a fourth insulating layer made of an epoxy resin or the like is formed on the surface of the base substrate up to the surface height of the electrode of the bare chip component, and Cu or Cu is formed at a predetermined position of the fourth insulating layer. A plurality of electrical connection posts made of plating or paste of Ag or the like are formed.

In the base substrate, C is inserted into a plurality of through holes.
An electric connection post made of plating or paste of u or Ag is formed, and the electric connection post is electrically insulated from the base substrate by an insulating material made of epoxy or polyimide resin. Further, an external earth electrode made of Cr / Cu / Cr or the like is provided on the back surface of the base substrate, and a similar Cr / Cu is provided on the back surface of the insulating material.
An external signal electrode made of / Cr or the like is formed.

In addition, an inert gas such as N ₂ is sealed in a hollow region of the upper shield substrate, and a shield film such as Cr / Cu / Cr is formed on all side surfaces of the module.

In the multi-chip module of the present invention having such a structure, the metal plate of the upper shield substrate and the shield film are electrically connected to the external earth electrode.
In addition, the ground conductor layer in the active element substrate is electrically connected to an external ground electrode via an electric connection post.

One electrode surface of the capacitor in the passive element substrate is electrically connected to an external signal electrode through each wiring layer and an electric connection post. Further, another electrode surface of the capacitor is electrically connected to the electrode of the bare chip component through each wiring layer and an electrical connection post. Similarly, each electrode of the resistor is electrically connected to each electrode of each bare chip component at each wiring layer and electric connection post,
One electrode of the coil is electrically connected to the electrode of the bare chip component at each wiring layer and an electrical connection post.
The other electrode of the coil is electrically connected to an external signal electrode at each wiring layer and each electrical connection post.

The second embodiment of the multi-chip module according to the present invention has a laminated structure in which a top shield substrate, a passive element substrate, and an active element substrate are formed in separate processes and then arranged in a predetermined layer arrangement. is there.

The upper shield substrate has the metal plate made of Cu or the like, the first insulating layer made of an epoxy or polyimide resin or the like on the back surface, and the first adhesive layer made of an epoxy or polyimide resin or the like. By using a laminate having a three-layer structure, the hollow region is formed in a part of the first insulating layer and the adhesive layer by a known etching process. The hollow area corresponds to the area where the coil is formed on the passive element substrate.

The passive element substrate may be formed on the surface of the second insulating layer made of a highly heat-resistant resin such as polyimide resin at a temperature lower than the heat-resistant temperature (for example, 350 ° C.) of the second insulating layer. A resistor made of a material (eg, WSiN film; sheet resistivity: 100 Ω / □, film thickness: 200 nm), a capacitor made of a thin film such as STO, Cr / Cu / C
A wiring layer made of r or the like is sequentially formed in a desired shape by a known thin film processing method, and a third insulating layer made of an epoxy or polyimide resin is formed thereon. further,
On the surface of the third insulating layer, a wiring layer and a coil made of Cr / Cu / Cr or the like are formed into desired shapes by a combination of a known thin film processing method and a plating method.

Next, a hole for an electrical connection post having a predetermined shape is formed in a predetermined position from the back surface of the second insulating layer by a known etching method or laser processing, and a known plating method of Cu or Ag is performed. Alternatively, the electric connection post is formed by a paste filling method. Further, an interlayer connection electrode made of Cr / Cu / Cr or the like is formed in a desired shape on the back surface of the second insulating layer by a combination of a well-known thin film processing method and a plating method, and is formed around the interlayer connection electrode. A second adhesive layer made of an epoxy or polyimide resin is formed by the film forming method described above.

Here, it is preferable that what is formed in a later step is formed at a temperature lower than the heat-resistant temperature of that formed in an earlier step.

For the active element substrate, a metal plate or a Si substrate is used as a base substrate, a plurality of through holes for electric connection posts of a predetermined shape are formed in the base substrate by a known etching method, and epoxy or epoxy is formed in the through holes. An insulating material made of a polyimide resin or the like is filled by a known method, a hole is formed in the insulating material by a known laser process, and the electric connection is performed by a known plating method of Cu or Ag or a paste filling method. Form a post.

Next, an earth conductor layer is formed on the surface of the base substrate by a well-known thin film forming method and a plating method, and a plurality of bare chip components are formed thereon by eutectic solder such as Au / Sn or paste such as Ag. It is mounted face up using a conductive material consisting of Thereafter, a fourth insulating layer made of an epoxy-based resin or the like is formed flat on the surface of the base substrate to a surface height of the electrode of the bare chip component by a well-known curtain coating method, and the fourth insulating layer is formed. Drilling is performed at a predetermined position of the layer by a known laser processing to form a well-known Cu
Alternatively, a plurality of electrical connection posts are formed by a plating method such as Ag or a paste filling method.

Here, in order to reliably electrically connect the electrodes of the bare chip component and the electrical connection posts to the interlayer connection electrodes of the passive element substrate, the electrical connection posts are formed, and then the bare connection is formed. It is preferable that the surfaces of the electrodes, the electrical connection posts, and the fourth insulating layer of the chip component are ground, polished, or etched to surely expose the upper ends of the electrodes and the electrical connection posts. Further, it is preferable that what is formed in a later step be formed at a temperature lower than the heat resistance temperature of what is formed in an earlier step.

Next, Cr / Cu / C is applied to the back surface of the base substrate.
external earth electrode made of r, etc.
An external signal electrode made of / Cu / Cr or the like is simultaneously formed by a combination of a known thin film processing method and a plating method.

Next, the upper shield substrate, the passive element substrate, and the active element substrate are arranged at predetermined positions and in a layered structure, and are collectively pressed in a known inert gas such as N ₂ to form a laminated structure. Module board. Thus, the inert gas is sealed in the hollow area provided on the upper shield substrate.

Next, the front surface of the upper shield substrate of the module substrate formed with a number of multi-chip modules and the back surface of the active device substrate are covered with plating resistant resin, and the metal layer of the upper shield substrate and the active device substrate are previously covered. The scribe line formed on the back surface is cut into multi-chip modules of a predetermined size by a known module substrate cutting method.

Next, a shield film is formed on all sides of each of the multichip modules by a known plating method of Cr / Cu / Cr or the like, and then the plating resistant resin is removed by a known etching method. Thus, a desired multi-chip module is manufactured.

The third embodiment of the multichip module according to the present invention comprises a laminated structure of an upper shield substrate, a composite substrate on which a resistor, a capacitor, a coil and a bare chip component are mounted, and an active element substrate.

The hollow area of the upper shield substrate corresponds to the coil forming area and the bare chip component mounting area on the composite substrate.

In the composite substrate, a wiring layer and a coil are formed on a surface of a third insulating layer, a bare chip component is mounted on the wiring layer by flip-chip mounting, and the resistor and the capacitor are formed in an inner layer. ing.

In the active element substrate, a bare chip component is mounted on a base substrate by face-up mounting, and an external ground electrode and an external signal electrode are provided on the back surface.

The hollow area of the upper shield substrate is covered with an inert gas such as N ₂ . further,
A shield film is formed on all side surfaces of the module.

In the fourth embodiment of the multichip module according to the present invention, the upper shield substrate, the composite substrate, and the active element substrate are formed in different processes, respectively, and then have a laminated structure with a predetermined layer arrangement. .

In the upper shield substrate, a part of the first insulating layer and the part of the first adhesive layer that are cut out are formed in a region corresponding to the coil forming region and the bare chip component mounting region on the composite substrate.

In the composite substrate, the resistor and the capacitor are formed on the second insulating layer by a combination of a known thin film processing method and a plating method, and the coil is formed by a combination of a known thin film processing method and a plating method. Formed on the layer, the third
The bare chip component is mounted on the wiring layer on the surface of the insulating layer by flip chip mounting.

As the active element substrate, a metal plate or a Si substrate is used as a base substrate, a through hole for an electric connection post is formed in the base substrate, an insulating material is filled in the through hole, and an electric connection post is formed in the insulating material. To form

Next, an earth conductor layer is formed on the surface of the base substrate, and a plurality of bare chip parts are mounted face-up thereon using a conductive material. Thereafter, a fourth insulating layer is formed flat on the surface of the base substrate,
Electrical connection posts are formed at predetermined positions on the insulating layer.

Next, an external ground electrode is formed on the back surface of the base substrate, and an external signal electrode is formed on the back surface of the insulating material.

Next, the upper shield substrate, the passive element substrate, and the active element substrate are arranged at predetermined positions and in a layered structure.
A module substrate having a laminated structure is formed in an inert gas. Thereby, an inert gas can be sealed in the hollow area provided on the upper shield substrate.

Next, the front surface of the upper shield substrate and the back surface of the active element substrate of the module substrate, on which a number of multi-chip modules are formed, are covered with plating resistant resin, and are formed on the front surface and the back surface of the module substrate in advance. Cut on the scribe line.

Next, a shield film is formed on all side surfaces of each of the multi-chip modules, and thereafter, the plating-resistant resin is removed to manufacture a desired multi-chip module.

As described above, according to the multichip module of the present invention, the upper shield substrate, the passive element substrate, and the active element substrate are formed in different processes, so that the substrate forming temperature conditions can be individually determined. From
Restrictions on the respective substrate forming temperature conditions are reduced, and substrate fabrication becomes easier.

Further, in the resistor and the capacitor, on the insulating film made of an organic thermosetting resin having a small difference in thermal expansion coefficient from those of the passive elements, it is formed at a temperature lower than the heat resistant temperature of the insulating film. Therefore, there is no possibility that troubles such as peeling of the film and generation of cracks will occur.

Further, if a high dielectric film having a dielectric constant much larger than SiO ₂ , such as STO, is used as the dielectric film of the capacitor, the required area is much smaller than when SiO ₂ is used. A thinner capacitor is obtained. The thickness is preferably about 200 nm. When such a high dielectric material film is used, the capacitor can be made thin and small, so that a bypass capacitor (for example, 0.01 mm ²
/ 100 pF, the formation of the dielectric film thickness 200 nm) and a coupling capacitor (e.g. 0.001 mm ^2/10 pF, dielectric thickness 200 nm) is facilitated, the capacitor,
The resistor and the electrodes of the bare chip component can be connected with the shortest wiring length, and the area occupied by the capacitor is significantly smaller than that of the conventional module structure (for example, about 1/30 of the conventional one). A small multi-chip module structure can be realized.

Further, as the base substrate, a metal such as Cu, Al, Fe, or Ni having a low coefficient of thermal expansion and a high thermal conductivity, an alloy thereof, or a composite material thereof may be used.

Further, by mass-producing simultaneously on a large substrate by batch processing, cost reduction can be achieved.

Hereinafter, embodiments of the present invention will be described in more detail. FIG. 1 is a sectional view of the multi-chip module according to the first embodiment of the present invention. In the figure, a multichip module 1 has a laminated structure of an upper shield substrate 2, a passive element substrate 3, and an active element substrate 4.

The upper shield substrate 2 has a layered structure having a first insulating layer 6 and an adhesive layer 7 on the back surface of the metal plate 5, and a part of the first insulating layer 6 and the first adhesive layer 7. A hollow region 8 is provided.

In the passive element substrate 3, a resistor 10, a wiring layer 11, a capacitor 12 and a third insulating layer 13 are formed on the surface of a second insulating layer 9, and a plurality of passive elements are provided at predetermined positions on the second insulating layer 9. Are formed. The wiring layer 14 and the coil 15 are provided on the surface of the third insulating layer 13.
Is formed, and an electrode layer 16 and a second adhesive layer 17 are formed on the back surface of the second insulating layer 9.

In the active element substrate 4, an earth conductor layer 19 is formed on the surface of a base substrate 18, and a plurality of bare chip components 20 are mounted face-up thereon using a conductive material 21. Further, a fourth insulating layer 23 is formed on the surface of the base substrate 18 up to the surface height of the electrode 22 of the bare chip component 20, and a plurality of electric connection posts 24 are provided at predetermined positions of the fourth insulating layer 23. Is formed. An electric connection post 25 is formed in the through hole 26 in the base substrate 18, and the electric connection post 25 is electrically insulated from the base substrate 18 by an insulating material 27. Further, an external ground electrode 28 is formed on the back surface of the base substrate 18, and an external signal electrode 29 is formed on the back surface of the insulating material 27.

In the multichip module 1, an inert gas is sealed in the hollow region 8, and a shield film 30 is formed on a side surface.

In the multi-chip module 1 having such a structure, the metal plate 5 and the shield film 30 are electrically connected to the external earth electrode 28. The ground conductor layer 19 is connected to the external ground electrode 28 by the electric connection post 25-2.
Is electrically connected to

The upper electrode surface of the capacitor 12 is connected to the wiring layer 14, the wiring layer 11, the electrical connection post 31, and the wiring layer 1.
6, the electrical connection post 24, and the electrical connection post 25-1 are electrically connected to the external signal electrode 29-1.
The lower electrode surface of the capacitor 12 is electrically connected to the electrode 22 of the bare chip component 20-1 by the wiring layer 11, the electrical connection post 31, and the wiring layer 16.

Each electrode of the resistor 10 is connected to each of the electrodes 2 of the bare chip component 20-1 and the bare chip component 20-2 by the wiring layer 11, the electrical connection post 31, and the wiring layer 16.
2 are electrically connected to each other.

The central electrode of the coil 15 is electrically connected to the electrode 22 of the bare chip component 20-2 at the wiring layer 11, the electrical connection posts 31 and the wiring layer 16. The outer peripheral electrode of the coil 15 is electrically connected to the external signal electrode 29-2 by the wiring layer 14, the wiring layer 11, the electric connection post 31, the wiring layer 16, the electric connection post 24, and the electric connection post 25-1. It is connected to the.

FIG. 2 is a sectional view of a method for manufacturing a multi-chip module according to the second embodiment of the present invention. In the figure, a multichip module 1 has a laminated structure with a predetermined layer arrangement after an upper shield substrate 2, a passive element substrate 3, and an active element substrate 4 are formed in separate processes.

In FIG. 9A, the metal plate 5 and the first insulating layer 6
And a first adhesive layer 7 are laminated in a three-layer structure, and a cutout region 8 is formed in a part of the first insulating layer 6 and the first adhesive layer 7 by a well-known etching process. The shield substrate 2 is formed. The hollow region 8 corresponds to a region where the coil 15 is formed on the passive element substrate 3. Thus, the upper shield substrate 2 of FIG.

In FIG. 9B, a resistor 10, a wiring layer 11 and a capacitor 12 are sequentially formed in a desired shape on a surface of a second insulating layer 9 by a known thin film processing method, and a third insulating layer is formed thereon. The layer 13 is formed. Further, the wiring layer 14 and the coil 15 are formed in a desired shape on the surface of the third insulating layer 13 by a combination of a known thin film processing method and a plating method.

Next, a hole for the electrical connection post 31 having a predetermined shape is formed in a predetermined position from the back surface of the second insulating layer 9 by a known etching method or laser processing, and a known conductive material filling method or plating is performed. The electrical connection post 31 is formed by the method. Further, the electrode 16 is provided on the back surface of the second insulating layer 9.
Is formed into a desired shape by a combination of a known thin film processing method and a plating method, and a second adhesive layer 17 is formed around the electrode 16 by a known film forming method. Thus, FIG.
Was formed.

In FIG. 9C, a through hole 26 of an electric connection post 25 is formed in the base substrate 18 by a known etching method using a Si wafer as the base substrate 18.
Is filled with an insulating material 27, and a hole is formed in the insulating material 27 by a known laser processing to form the electric connection post 25 by a known conductive material filling method or a plating method.

Next, an earth conductor layer 19 is formed on the surface of the base substrate 18 and a plurality of bare chip components 20 are formed thereon.
Is mounted face up using the conductive material 21. After that, a fourth insulating layer 23 is formed on the surface of the base substrate 18 to a flat surface up to the surface height of the electrode 22 of the bare chip component 20 by a well-known curtain coating method, and is formed at a predetermined position on the fourth insulating layer 23. A plurality of electric connection posts 24 are formed by a known method of filling a conductive material or a plating method by making a hole by a known laser process.

Next, an external ground electrode 28 is formed on the back surface of the base substrate 18 and an external signal electrode 29 is formed on the back surface of the insulating material 27 at the same time by a combination of a known thin film processing method and a plating method. Thus, the active element substrate 4 shown in FIG.

In FIG. 9D, the upper shield substrate 2, the passive element substrate 3, and the active element substrate 4 described in FIGS. 9A to 9C are arranged at predetermined positions in a layered structure.

Thereafter, the upper shield substrate 2, the passive element substrate 3, and the active element substrate 4 are collectively pressed in a known inert gas to form a laminated structure. As a result, an inert gas is sealed in the insulating layer cutout region 8 provided on the upper shield substrate 2.

In FIG. 9E, the front surface of the upper shield substrate 2 and the back surface of the active element substrate 4 are covered with a plating resistant resin, and are cut into a predetermined module size by a known module substrate cutting method.

Next, a shield film 30 is formed on all sides of each module by a well-known plating method, and the metal plate 5, the shield film 30, and the external earth electrode 28 are electrically connected. Thereafter, the plating resistant resin is peeled off by a known etching method. Thus, the multi-chip module 1 of FIG. 2E was manufactured.

FIG. 3 is a sectional view of a multichip module according to a third embodiment of the present invention. In the figure, a multi-chip module 101 is a composite board 103 on which an upper shield substrate 102, a resistor 110, a capacitor 112, a coil 115, and a bare chip component 120-2 are mounted.
And a stacked structure of the active element substrate 104.

The upper shield substrate 102 includes a metal plate 105
Has a layer structure having a first insulating layer 106 and a first adhesive layer 107 on the back surface thereof, and a hollow region 108 is provided in a part of the first insulating layer 106 and the first adhesive layer 107. The hollow area 108 corresponds to the area where the coil 115 is formed on the composite substrate 103 and the area where the bare chip component 120-2 is mounted.

In the composite substrate 103, a wiring layer 114 and a coil 115 are formed on the surface of a third insulating layer 113, and a bare chip component 120-2 is mounted on the wiring layer 114 by flip-chip mounting.

The active element substrate 104 includes a base substrate 118
The bare chip component 120-1 is mounted thereon by face-up mounting, and the bare chip component 120-1 is covered with a fourth insulating layer 123. Are formed. Also,
Electrical connection posts 125 are formed in the through holes 126 in the base substrate 118, and the electrical connection posts 125 are
At 7, it is electrically insulated from the base substrate 118. Further, an external ground electrode 128 is provided on the back surface of the base substrate 118.
However, an external signal electrode 129 is formed on the back surface of the insulating material 127.

The hollow area 108 is filled with an inert gas such as N ₂ , and a shield film 30 is formed on all side surfaces of the module.

FIG. 4 is a sectional view of a method for manufacturing a multichip module according to a fourth embodiment of the present invention. In the figure, a multi-chip module 101 includes an upper shield substrate 102.
After the composite substrate 103 and the active element substrate 104 are formed in different processes, the laminated structure is formed in a predetermined layer arrangement.

FIG. 10A shows an upper shield substrate 102.
A hollow region 108 of a part of the first insulating layer 106 and the adhesive layer 107 is formed in a region corresponding to a region where the coil 115 is formed and a region where the bare chip component 120 is mounted on the composite substrate 103.

FIG. 9B shows a composite substrate 103 having a resistor 1
10, a capacitor 112, and a coil 115 are formed by a combination of a well-known thin film processing method and a plating method, and the bare chip component 12 is formed on the wiring layer 114 on the surface of the third insulating layer 113.
0 is mounted by flip chip mounting.

FIG. 10C shows the active element substrate 104.
An electric connection post 125 and a ground conductor layer 119 are formed on a base substrate 118, and a plurality of bare chip components 1 are formed thereon.
20 is mounted face up using the conductive material 121. Next, a fourth insulating layer 123 is formed on the surface of the base substrate 118 so as to fill the plurality of bare chip components 120, and a plurality of electrical connection posts 124 are formed at predetermined positions of the fourth insulating layer 123. Next, an external ground electrode 128 is formed on the back surface of the base substrate 118 and an external signal electrode 129 is formed on the back surface of the insulating material 127 at the same time.

In FIG. 10D, the upper shield substrate 102, the composite substrate 103, and the active element substrate 104 are arranged at predetermined positions and in a layered structure, and thereafter they are collectively pressed in a known inert gas. To form a laminated structure. Thus, an inert gas is sealed in the hollow area 108 provided in the upper shield substrate 2.

In FIG. 10E, the front surface of the upper shield substrate 102 and the back surface of the active element substrate 104 are covered with a plating resistant resin, and cut into a predetermined module size by a known module substrate cutting method.

Next, a shield film 130 is formed on all sides of each module 101 by a known plating method, and the metal plate 105, the shield film 130, and the external earth electrode 128 are electrically connected. Thereafter, the plating resistant resin is peeled off by a known etching method. Thus, the multi-chip module 101 was manufactured.

FIG. 5 shows an example of the circuit configuration of the multichip module according to the first embodiment of the present invention shown in FIG. In the figure, an input signal is input from the external electrode 29-1 and input to the bare chip component 20-1 via the capacitor 12. The output signal of the bear chip component 20-1 is input to the bare chip component 20-2 via the resistor 10. The output signal of the bear chip component 20-2 is output from the external electrode 29-2 to the outside via the coil 15.

FIG. 6 is a perspective view of the multi-chip module manufacturing method according to the second embodiment of the present invention shown in FIG. As shown in the figure, in this manufacturing method, a large number of multi-chip modules 1 are collectively formed on a large-area wafer-type substrate 18-1 or a rectangular substrate 18-2, and the module substrate 1 is previously formed.
8 scribe line 31 formed on the front or back surface
The above is cut into individual multichip modules 1.

As described above, in the embodiments up to FIG. 6, the structure in which a plurality of bare chip components 20 are mounted per module has been described. However, in the structure in which one bare chip component 20 is mounted per module. Also, a module manufacturing method as shown in FIG. 2 is effective.

[0110]

As is apparent from the above description, according to the present invention, the upper shield substrate and the passive element substrate or the composite substrate and the active element substrate can be processed in different processes, respectively, so that the manufacturing time can be shortened and the design changes. Becomes easier.

Further, since the coil surface and the bare chip component on the passive element substrate or the composite substrate can be covered with an inert gas, the coil and the bare chip component can obtain good high-frequency characteristics. Further, by using a high-dielectric material film such as STO as a dielectric film of a capacitor, the required area of the capacitor is significantly reduced as compared with the conventional one, and a multi-chip module with a small area is realized.

Further, by using a metal or a semiconductor having good thermal conductivity for the base substrate of the active element substrate, heat radiation from the bare chip component is extremely improved, and as a result,
It is now possible to mount bare chip components with high power consumption and high frequency specifications. Further, since the bare chip component is directly disposed on the ground conductor layer, the connection resistance between the back surface of the bare chip component and the ground conductor layer is minimized, and the circuit operation in a high frequency region is much more stabilized than before.

Further, since the upper shield substrate, the passive element substrate, and the active element substrate are formed in separate processes, the formation temperature conditions for each substrate are simplified, and especially the substrate material used for the passive element substrate and the thin film of the resistor and the capacitor are used. The choice of materials is expanded. In addition, since each substrate is formed at a temperature lower than the heat-resistant temperature of those formed in a later process but formed in an earlier process, troubles such as film peeling and cracking occur in each manufacturing process. There is no danger.

[Brief description of the drawings]

FIG. 1 is a sectional view of a multichip module according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a method for manufacturing a multi-chip module according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a multi-chip module according to a third embodiment of the present invention.

FIG. 4 is a sectional view of a method for manufacturing a multi-chip module according to a fourth embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of the first embodiment of the present invention.

FIG. 6 is a perspective view of a manufacturing method according to a second embodiment of the present invention.

[Explanation of symbols]

1: Multichip module, 2: Top shield substrate,
3 passive element substrate, 4 active device substrate, 5 metal plate, 8
... hollow area, 10 ... resistor, 12 ... capacitor, 15
... Coil, 18 ... Base board, 20 ... Bear chip part, 28 ... External ground electrode, 29 ... External signal electrode, 30
... Shield film.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Koji Yamada, Inventor 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Central Research Laboratory (72) Inventor Masahiro Suzuki 7-1-1, Omika-cho, Hitachi City, Ibaraki Pref.Hitachi, Ltd.Hitachi Research Laboratory (72) Inventor Hiroyuki Tenmei 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. Hitachi, Ltd., Production Technology Research Laboratory

Claims (21)

[Claims] 1. A multi-chip module comprising a plurality of resistors, capacitors and coils having a thin film shape and a plurality of bare chip components or IC chips having a bare chip component shape (hereinafter referred to as bare chip components). A top shield substrate having a metal plate,
A multi-chip module comprising a laminated structure of the passive element substrate having the resistor, the capacitor, and the coil, and the active element substrate having the bare chip component. 2. The multi-chip module according to claim 1, wherein the insulating layer of the upper shield substrate has a hollow structure corresponding to a coil forming region formed on the surface of the passive element substrate. . 3. The passive element substrate according to claim 1, wherein a plurality of resistors and capacitors are formed in a thin film shape on an inner layer, and a plurality of coils are formed in a spiral shape on an uppermost layer. A multi-chip module according to claim 1. 4. A plurality of bare chip components are mounted face up on a ground conductor layer provided on the surface of the active element substrate using a conductive material, and the plurality of bare chip components are mounted on the bare chip. 2. The multi-chip module according to claim 1, wherein the multi-chip module is embedded with an insulating layer made of an insulating resin up to a height of an electrode surface of the component. 5. The multi-device according to claim 1, wherein a base substrate of said active element substrate is made of a Si wafer or a metal plate, and electrical connection posts are formed inside said base substrate and inside said insulating layer. Chip module. 6. The multi-chip module according to claim 1, wherein external electrodes are formed on the surface of the insulating layer and the surface of the electrical connection post on the back surface of the base substrate of the active element substrate, respectively. 7. The multi-chip module according to claim 1, wherein an inert gas is sealed in a region where the insulating layer is provided in the upper shield substrate. 8. The multichip module according to claim 1, wherein a side surface of the multichip module is covered with a shield film. 9. An upper surface shield substrate having a metal plate;
A multi-layer structure comprising a passive element substrate having passive elements such as thin-film resistors and capacitors and coils, and an active element substrate having bare chip components in a predetermined layer arrangement. Manufacturing method of chip module. 10. The insulating layer and the adhesive layer of the upper shield substrate are formed by cutting a region corresponding to a coil forming region formed on the surface of the passive element substrate by an etching method. A method for manufacturing the multichip module according to the above. 11. The passive element substrate according to claim 1, wherein a plurality of resistors and capacitors are formed in a desired shape on an inner layer of the multilayer substrate made of insulating resin by a thin film processing method, and a plurality of coils are formed on the uppermost layer by the thin film processing method and plating. The method for manufacturing a multi-chip module according to claim 9, wherein the multi-chip module is formed into a spiral shape by a combination of methods. 12. The active element substrate, wherein a ground conductor layer is provided on a surface of a base substrate, and a plurality of bare chip components are mounted face-up on the ground conductor layer using a conductive material. The method for manufacturing a multi-chip module according to claim 9, wherein the insulating resin is formed into a flat film by a curtain coating method up to the electrode surface height. 13. The active element substrate according to claim 1, wherein the Si substrate or the metal plate is used as the base substrate, and the electrical connection posts are formed inside the base substrate and the insulating layer by a printing method, a plating method, or an etching method. The method for manufacturing a multi-chip module according to claim 12, wherein: 14. The method according to claim 13, wherein the active element substrate has external electrodes formed on the surface of the insulating layer on the back surface of the base substrate and on the surface of the electrical connection post. 15. The method for manufacturing a multi-chip module according to claim 9, wherein an inert gas is sealed in a region where the insulating layer is provided in the upper shield substrate. 16. The method according to claim 9, wherein a shield film is formed on all side surfaces of the multi-chip module by a plating method. 17. A multi-chip module having a plurality of thin-film resistors, capacitors, and coils, and a plurality of bare chip components, a top shield substrate having a metal plate, It is characterized in that it has a laminated structure of a composite substrate having a passive element such as a coil and a part of the bare chip component and an active element substrate having the rest of the bare chip component. Multi-chip module. 18. The upper shield substrate according to claim 17, wherein an insulating layer in a region corresponding to a coil forming region and a bare chip component mounting region formed on the surface of the composite substrate has a hollow structure. A multi-chip module according to claim 1. 19. A plurality of resistors and capacitors are formed in a thin film shape on an inner layer of the composite substrate, a plurality of coils are formed in a spiral shape on an uppermost layer, and a plurality of bare chip components are flipped. The multi-chip module according to claim 17, wherein the multi-chip module is mounted by a chip method. 20. A top shield substrate having a metal plate, a composite substrate having passive elements such as thin film resistors and capacitors and coils, and a plurality of bare chip components, and a plurality of bare chip components. A method for manufacturing a multi-chip module, comprising forming an active element substrate having a laminated structure with a predetermined layer arrangement. 21. The composite substrate, wherein a plurality of resistors and capacitors are formed in a desired shape on an inner layer of a multilayer substrate made of an insulating resin by a thin film processing method, and a plurality of coils are formed on an uppermost layer by a thin film processing method and a plating method. 21. The method of manufacturing a multi-chip module according to claim 20, wherein the multi-chip module is formed in a spiral shape by a combination of the above, and a plurality of bare chip components are mounted on another portion of the uppermost layer by a flip chip method.