CN113421861A - Multi-device packaging single structure based on multilayer concave embedded substrate - Google Patents

Multi-device packaging single structure based on multilayer concave embedded substrate Download PDF

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Publication number
CN113421861A
CN113421861A CN202110524294.8A CN202110524294A CN113421861A CN 113421861 A CN113421861 A CN 113421861A CN 202110524294 A CN202110524294 A CN 202110524294A CN 113421861 A CN113421861 A CN 113421861A
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chip
substrate
electrode
multilayer
multilayer substrate
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不公告发明人
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BEIJING 7Q TECHNOLOGY CO LTD
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BEIJING 7Q TECHNOLOGY CO LTD
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0215—Grounding of printed circuits by connection to external grounding means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention relates to a multi-device packaging single structure based on a multilayer concave embedded substrate, which comprises: the multilayer substrate comprises a multilayer substrate, a multilayer substrate signal wire, a multilayer substrate grounding wire, a bottom layer electrode and a grounding electrode; the lower surface of the multilayer substrate is provided with a concave embedding space, at least one chip and at least one active or passive device are placed in the concave embedding space, and the chip and the device are welded on an inner layer substrate of the concave embedding space of the multilayer substrate through a welding layer material; the first electrode of the device is connected with the bottom layer electrode through the multilayer substrate signal wire, and the second electrode of the device is connected with the chip through a chip electrode lead; the chip is respectively connected with the second electrode and the connecting electrode of the device through a chip electrode lead, and is connected with the multilayer substrate grounding wire through the connecting electrode. The structure has the following characteristics: the multilayer PCB is not easy to warp and peel; high processing cost of the SiP die and a processing period of a new structure are avoided; the cost is low.

Description

Multi-device packaging single structure based on multilayer concave embedded substrate
Technical Field
The invention relates to the technical field of multi-device packaging design by utilizing a substrate, in particular to a multi-device packaging single structure based on a multilayer concave embedded substrate, and particularly relates to a multi-chip CIB (chip in board) packaging single integrated structure based on different processes of the multilayer concave embedded substrate.
Background
Up to now, various devices and terminals relating to electronic information systems are required to be miniaturized, integrated, and multi-chip integrated in many cases depending on applications. Until now, a plurality of devices or a plurality of chips in different processes are realized by adopting an sip (system in package) packaging structure, and the appearance of the chip is like the same chip. SiP packaging requires a package substrate and a resin molding die. In the process of injection molding a plurality of (typically several hundreds of) SiP monomers into a SiP aggregate having a large area, the thermal expansion coefficients of the package substrate and the package resin are required to be close to each other so as to prevent warpage and peeling, which is one of the requirements for ensuring the quality of the cut-into-monomer SiP packages. However, the cost of the package substrate is higher than that of the lead frame for conventional plastic package, and the cost of the SiP mold is high, so that the low-cost integrated package of multiple devices is difficult to realize.
For example, chinese patent No. ZL201920060815.7 discloses a chip antenna monolithic structure based on a multi-layer recessed embedded substrate. The antenna is distributed on the upper surface of the substrate based on the subminiature substrate, the chip is packaged in the open concave embedding space below the substrate, and the subminiature integrated package and the antenna are integrated, wherein the electrode on the lower surface of the substrate is welded on the master mask. The single integrated structure of the chip and the antenna can be designed and processed into a required antenna structure on the surface layer of the multilayer substrate surface, a concave embedding space is formed at one part of the back layer of the multilayer substrate, the multilayer substrate is used as a packaging mother frame body, and the bare chip is packaged in the concave embedding space in a dispensing mode. The most important package of the invention is that the surface antenna and the chip of the concave embedding space form an integrated structure.
In many cases, the surface antenna and the chip embedded in the concave space are not used to form an integrated structure, so that the surface antenna needs to be removed and only the multilayer substrate is used as a packaging carrier of the multi-device. The present invention is therefore different from the above-mentioned patent. The packaging integration is realized in the concave embedding space only aiming at how to utilize the concave embedding space of the multilayer substrate so that devices manufactured by different processes.
Disclosure of Invention
In the integration process of multiple devices in different manufacturing processes, various packaging forms such as MCM, SiP, and chip stacking are produced. The MCM bare chip glue is irregular in shape and high in height; although the SiP has the characteristics of thin line wiring and many high-density Pin points, the low-cost popularization is limited due to the high cost of the packaging substrate and the die; although the chip stack package has a small volume, the cost is high, and the yield is difficult to guarantee due to the high technical requirements of the package. The multi-device packaging single structure based on the multilayer concave embedded substrate can exactly solve the problems and realize flexible design and processing with low cost and short period and large-scale industrial production.
Therefore, aiming at the requirements, the invention creatively designs a three-dimensional integrated packaging structure which can meet the requirements of terminal miniaturization, flexible design, low cost and thinness, and forms a miniaturized three-dimensional integrated packaging structure with multiple devices in the substrate to form a single packaging appearance. The purpose of the invention is realized by the following technical scheme.
Specifically, according to one aspect of the present invention, the present invention discloses a multi-device package single structure based on a multi-layer recessed embedded substrate, comprising:
the multilayer substrate comprises a multilayer substrate, a multilayer substrate signal wire, a multilayer substrate grounding wire, a bottom layer electrode and a grounding electrode; wherein the content of the first and second substances,
the lower surface of the multilayer substrate is provided with a concave embedding space, at least one chip and at least one active or passive device are placed in the concave embedding space, and the chip and the device are welded on an inner layer substrate of the concave embedding space of the multilayer substrate through welding layer materials;
the first electrode of the device is connected with the bottom layer electrode through the multilayer substrate signal wire, and the second electrode of the device is connected with the chip through a chip electrode lead;
the chip is respectively connected with the second electrode and the connecting electrode of the device through a chip electrode lead, and is connected with the multilayer substrate grounding wire through the connecting electrode.
Preferably, the chip is a bare chip.
Preferably, the recessed space is further filled with an encapsulation resin to cover the bare chip.
Preferably, the encapsulation resin does not exceed the horizontal line of the lower surface of the multilayer substrate.
Preferably, the chip is a packaged chip, the chip electrode lead is replaced by a chip pin, and the packaged chip is fixed to the second electrode and the connection electrode of the device by welding through the chip pin.
Preferably, the passive device comprises at least one of: and capacitors, inductors, resistors, crystal oscillators, sensitive material devices, thick films and thin films are attached to the surface.
Preferably, a layer of protective glue is coated on the top of the recessed space.
Preferably, the signal line of the multilayer substrate is connected with the bottom electrode through the corresponding interlayer connecting wire hole, and the ground line of the multilayer substrate is connected with the grounding electrode through the corresponding interlayer connecting wire hole.
The invention has the advantages that: the invention designs a monolithic structure based on the encapsulation and integration of a chip of a multilayer concave embedded substrate and other devices by utilizing a cheap circuit substrate, and the monolithic structure is encapsulated in the concave embedded part of the multilayer substrate. In addition, various electrodes are set on the outer frame of the groove on the back surface of the packaging substrate, so that the packaging substrate can be simply welded on the surface of other mother boards.
In addition, the invention designs a multi-device packaging single structure based on a multi-layer concave embedded substrate by utilizing a traditional low-cost PCB multi-layer substrate, a connection mode which takes the PCB substrate as flexible wiring can be designed in the concave embedded substrate, the surface mounting of various devices with different processes is realized in the concave embedded space, and the gluing and the heating molding are carried out in the concave embedded space. The structure has the following characteristics:
1. the SiP has a layout structure in which a lower portion is made of resin and an upper portion is made of a package substrate. Based on the outer frame structure of the multilayer concave embedded substrate, the device surface is pasted in the concave embedded space, and then the adhesive is dispensed and sealed. Therefore, in the outer frame structure of the multilayer concave embedded substrate, after the glue is dispensed and cured, the common multilayer PCB is not easy to warp and peel.
2. The high processing cost of the SiP die and the processing period of a new structure are avoided. The multi-device packaging monomer structure based on the multilayer concave embedded substrate can realize the substrate frame only by a common PCB processing technology. Flexible design, low cost and short process cycle (days), while custom SiP molds are typically up to months long.
3. The cost is low. The cost of a multi-device single structure package based on a multi-layer concave embedded substrate is only a fraction of that of an equivalent SiP structure package.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1-1 is a schematic view of a multi-device package singulation architecture based on a first embodiment of a multi-layer recessed substrate;
fig. 1-2 is a schematic top view of a multi-device package singulation structure based on a multi-layer recessed substrate;
FIGS. 1-3 are schematic top-down views of a multi-device package singulation structure based on a multi-layer recessed substrate;
FIG. 2 is a schematic view of a packaged chip multi-device package singulation architecture based on a second embodiment of a multi-layer recessed substrate;
fig. 3 is a schematic view of a packaged chip multi-device package singulation structure based on a third embodiment of a multi-layer recessed substrate.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the integration process of multiple devices in different manufacturing processes, various packaging forms such as MCM, SiP, and chip stacking are produced. The MCM bare chip glue is irregular in shape and high in height; although the SiP has the characteristics of thin line wiring and many high-density Pin points, the low-cost popularization is limited due to the high cost of the packaging substrate and the die; although the chip stack package has a small volume, the cost is high, and the yield is difficult to guarantee due to the high technical requirements of the package. The multi-device packaging single structure based on the multilayer concave embedded substrate can exactly solve the problems and realize flexible design and processing with low cost and short period and large-scale industrial production.
Therefore, aiming at the requirements, the invention creatively designs a three-dimensional integrated packaging structure which can meet the requirements of terminal miniaturization, flexible design, low cost and thinness, and forms a miniaturized three-dimensional integrated packaging structure with multiple devices in the substrate to form a single packaging appearance. The purpose of the invention is realized by the following technical scheme.
The invention of the system structure aims to design a low-cost miniaturized chip and multi-device carrier structure and realize the low-cost flexible configurable function of circuits among different chip devices.
Referring to fig. 1-1, fig. 1-1 is a schematic view of a multi-device package singulation structure based on a multi-layer recessed substrate, and the present invention is intended to form a recessed space 2-3 on a bottom surface of the multi-layer substrate 1-1. The bare chip 2-2-0 is soldered on the inner substrate of the multilayer substrate via the die-bonding layer material 2-2-1. Access to substrate electrode lines 1-18 (also ground electrodes) is provided via chip electrode leads 2-2-2, electrodes 1-16 and interlayer wiring holes 1-17, depending on design wiring requirements. The bare chip 2-2-0 and the device 2-31 are connected by a link multilayer substrate wiring 1-19. Of course, the electrodes 1-16, 1-19, interlayer wiring holes 1-17 (with multi-layer substrate ground lines in the holes), and peripheral substrate electrodes 1-18 (also ground electrodes), etc. can be freely designed on the bottom surface of the substrate according to the system requirements of the chip device. 1-11 and 1-12 are insulating layers, and 1-4 are interlayer connecting holes (a plurality of layers of substrate signal wires are arranged in the holes) for connecting the bottom layer electrodes 1-5 and the electrodes of the device. 2-31-1 is a device welding layer material, and the device 2-31 is welded on an inner layer substrate of the multilayer substrate.
After the assembly of the chip and the device and the mounting of the device are completed, the concave embedding space of the substrate is filled with packaging resin 3-1, and the resin is cured by heating.
Further, it is emphasized that the encapsulation resin 3-1 in the recessed space of the multilayer substrate must not exceed the recessed space interface 4-1.
The structure diagrams are shown in fig. 1-2 and 1-3, which show top and bottom views of a chip-antenna-integrated substrate structure in an actual device. The upper surface is a flat substrate, the bottom layer electrodes 1-5, the grounding electrodes 1-18 and the like of the substrate are welded with other mother boards, and certainly, a plurality of substrate peripheral electrodes of the bottom layer electrodes 1-5, the grounding electrodes 1-18 and the like can be freely designed on the bottom surface of the substrate according to the system requirements of signal lines, grounding lines and power lines of chip devices.
In the practical design of the system of the present invention, the packaged chip can also be purchased, for example, a multi-device package single structure diagram containing the packaged chip based on a multi-layer recessed embedded substrate is shown in fig. 2, and the device can be a packaged chip 2-2-0, and is fixed on the recessed embedded metal connecting lines 1-16 and 1-19 inside the substrate through chip pins 2-2-1 by welding, and then filled with resin 3-1.
In the practical design of the system of the invention, the packaged chip is also purchased, such as a multi-device package single structure diagram containing the packaged chip based on a multilayer concave embedded substrate, namely, as shown in fig. 3, the device can be a packaged chip 2-2-3, and is fixed on the concave embedded part metal connecting lines 1-16 and 1-19 in the substrate through chip pins 2-2-4 in a welding way without additionally filling resin 3-1. In addition, in order to prevent the SMT chips and devices which are surface mounted from falling off due to the weight of the chips and the devices when the SMT chips and the devices are surface mounted on the mother board again, a layer of protective glue 5-1 can be coated on the multiple layers of concave embedding.
The embodiment designs a multi-device packaging single structure based on a multi-layer concave embedded substrate by using a cheap circuit substrate. The chip and the device with the structure are assembled in the concave embedding part of the multilayer substrate, the auxiliary circuit arrangement between the chip and the device can be carried out by utilizing the substrate, the manufacture of a lead frame and a packaging mold of a new structure package is not needed, a plurality of devices containing the chip are placed in the concave embedding part of the common substrate, and the design of a multi-substrate and the lead is flexible. The chip in the recessed substrate may be a bare chip or a chip packaged with resin. The cost and the manufacturing period can be reduced, which is the basic characteristic and the advantage of the invention.
The invention can flexibly test a small amount of samples (Pilot) at low cost. And rapid, initial, pilot-scale assessment of system-level functionality and performance can be performed. The performance discrete characteristic of each batch of chips is adjusted, and the optimization function of the chips is realized by flexibly performing parameter configuration adjustment through the selection of chip peripheral circuit devices arranged in the concave embedding.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (8)

1. A multi-device package singulation structure based on a multi-layer recessed substrate, comprising:
the multilayer substrate comprises a multilayer substrate, a multilayer substrate signal wire, a multilayer substrate grounding wire, a bottom layer electrode and a grounding electrode; wherein the content of the first and second substances,
the lower surface of the multilayer substrate is provided with a concave embedding space, at least one chip and at least one active or passive device are placed in the concave embedding space, and the chip and the device are welded on an inner layer substrate of the concave embedding space of the multilayer substrate through welding layer materials;
the first electrode of the device is connected with the bottom layer electrode through the multilayer substrate signal wire, and the second electrode of the device is connected with the chip through a chip electrode lead;
the chip is respectively connected with the second electrode and the connecting electrode of the device through a chip electrode lead, and is connected with the multilayer substrate grounding wire through the connecting electrode.
2. The multi-device package singulated structure based on multilayer recessed substrate as claimed in claim 1, wherein:
the chip is a bare chip.
3. The multi-device package singulated structure based on multilayer recessed substrate as claimed in claim 2, wherein:
the concave embedding space is further filled with packaging resin to cover the bare chip.
4. The multi-device package singulated structure based on multilayer recessed substrate as claimed in claim 3, wherein:
the encapsulation resin does not exceed the horizontal line of the lower surface of the multilayer substrate.
5. The multi-device package singulated structure based on multilayer recessed substrate as claimed in claim 1, wherein:
the chip is a packaged chip, the chip electrode lead is replaced by a chip pin, and the packaged chip is welded and fixed to the second electrode and the connecting electrode of the device through the chip pin.
6. The multi-device package singulated structure based on multilayer recessed substrate as claimed in claim 1, wherein: the passive device includes at least one of: and capacitors, inductors, resistors, crystal oscillators, sensitive material devices, thick films and thin films are attached to the surface.
7. The multi-device package singulated structure based on multilayer recessed substrate as claimed in claim 5, wherein: and a layer of protective glue is coated on the top of the concave embedding space.
8. The multi-device package singulated structure based on multilayer recessed substrate as claimed in claim 1, wherein: the multilayer substrate signal wire is connected with the bottom layer electrode through the corresponding interlayer connecting wire hole, and the multilayer substrate grounding wire is connected with the grounding electrode through the corresponding interlayer connecting wire hole.
CN202110524294.8A 2021-05-13 2021-05-13 Multi-device packaging single structure based on multilayer concave embedded substrate Pending CN113421861A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1145977A (en) * 1997-07-28 1999-02-16 Hitachi Ltd Multichip module and manufacture thereof
CN109712947A (en) * 2019-01-14 2019-05-03 北京七芯中创科技有限公司 A kind of antenna component singulation structure based on the recessed embedded substrate of multilayer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1145977A (en) * 1997-07-28 1999-02-16 Hitachi Ltd Multichip module and manufacture thereof
CN109712947A (en) * 2019-01-14 2019-05-03 北京七芯中创科技有限公司 A kind of antenna component singulation structure based on the recessed embedded substrate of multilayer

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