JP2656120B2 - Manufacturing method of package for integrated circuit - Google Patents

Manufacturing method of package for integrated circuit

Info

Publication number
JP2656120B2
JP2656120B2 JP1244766A JP24476689A JP2656120B2 JP 2656120 B2 JP2656120 B2 JP 2656120B2 JP 1244766 A JP1244766 A JP 1244766A JP 24476689 A JP24476689 A JP 24476689A JP 2656120 B2 JP2656120 B2 JP 2656120B2
Authority
JP
Japan
Prior art keywords
integrated circuit
film
substrate
wiring board
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1244766A
Other languages
Japanese (ja)
Other versions
JPH03106061A (en
Inventor
隆治 今井
六郎 神戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Tokushu Togyo KK
Original Assignee
Nippon Tokushu Togyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Tokushu Togyo KK filed Critical Nippon Tokushu Togyo KK
Priority to JP1244766A priority Critical patent/JP2656120B2/en
Publication of JPH03106061A publication Critical patent/JPH03106061A/en
Application granted granted Critical
Publication of JP2656120B2 publication Critical patent/JP2656120B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、基板上に多層配線板を介して集積回路を搭
載する集積回路用パッケージの製造方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for manufacturing an integrated circuit package in which an integrated circuit is mounted on a substrate via a multilayer wiring board.

[従来の技術] 誘電率が小さい、例えばポリイミド樹脂を絶縁膜とし
た多層配線板の上に集積回路を搭載し、信号の高速化を
図った集積回路用パッケージが知られている。
2. Description of the Related Art There is known an integrated circuit package in which an integrated circuit is mounted on a multilayer wiring board having a small dielectric constant, for example, using a polyimide resin as an insulating film to increase the signal speed.

[発明が解決しようとする課題] 誘電率の小さい絶縁体は、一般に熱伝導率が悪い。ポ
リイミド樹脂を例に示すと、一般に基板に用いられるア
ルミナセラミックに比較して、熱伝導率が1/100と小さ
い。
[Problems to be Solved by the Invention] An insulator having a small dielectric constant generally has poor thermal conductivity. Taking polyimide resin as an example, the thermal conductivity is 1/100 smaller than that of alumina ceramics generally used for substrates.

このため、集積回路が発生した熱の放熱率が低く、搭
載される集積回路は、熱的な制限を受ける。
Therefore, the heat release rate of the heat generated by the integrated circuit is low, and the integrated circuit to be mounted is thermally limited.

そこで、例えば、搭載される集積回路に、直接、加熱
器を接合する構造が考えられる。これは、集積回路をフ
ェースダウン(配線面がパッケージの表面に向く)で、
パッケージに搭載し、集積回路の裏面に放熱器をかねた
封止用キャップを接合するものである。
Therefore, for example, a structure in which a heater is directly joined to an integrated circuit to be mounted is considered. This means that the integrated circuit is face down (the wiring side faces the surface of the package)
It is mounted on a package, and a sealing cap serving as a radiator is joined to the back surface of the integrated circuit.

しかるに、このタイプは、封止用キャップをパッケー
ジに取り付けた際に、集積回路と封止用キャップとが熱
的に結合する必要があるため、集積回路や、封止用キャ
ップ等に高度な寸法管理が要求される。つまり、集積回
路に放熱器を接合するものものは、実装、組付上に技術
的な問題点を備えていた。
However, in this type, when the sealing cap is attached to the package, the integrated circuit and the sealing cap need to be thermally coupled. Management is required. In other words, those in which the radiator is joined to the integrated circuit have technical problems in mounting and assembling.

本発明の目的は、集積回路の実装、組付が容易で、か
つ集積回路が発生する熱の放熱性に優れた集積回路用パ
ッケージの提供にある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit package that is easy to mount and assemble an integrated circuit and that has excellent heat dissipation of heat generated by the integrated circuit.

[課題を解決するための手段] 上記の目的を達成するために、本発明の集積回路用パ
ッケージの製造方法は、次の技術的手段を採用する。
Means for Solving the Problems In order to achieve the above object, a method for manufacturing an integrated circuit package of the present invention employs the following technical means.

集積回路用パッケージは、熱伝導性に優れた基板と、
この基板の表面に設けられ、低誘電率の絶縁膜と導体膜
とからなる配線膜を、多数積層した多層配線板とを具備
し、この多層配線板の表面に、集積回路が搭載される。
Integrated circuit packages consist of a substrate with excellent thermal conductivity,
A multi-layer wiring board is provided on the surface of the substrate and has a multiplicity of wiring films composed of an insulating film having a low dielectric constant and a conductor film. An integrated circuit is mounted on the surface of the multi-layer wiring board.

前記多層配線板は、前記基板から前記集積回路に達す
る放熱用ビアを備え、この放熱用ビアを備えた前記多層
配線板は、次の第1工程後、第2工程ないし第5工程を
順次繰り返して形成される。
The multilayer wiring board includes a heat dissipation via extending from the substrate to the integrated circuit, and the multilayer wiring board including the heat dissipation via sequentially repeats the second to fifth steps after the next first step. Formed.

前記基板の表面に電解メッキの下地となる導電性の下
地膜を形成する第1工程。
A first step of forming a conductive base film serving as a base for electrolytic plating on the surface of the substrate;

この下地膜の表面に導電性の導電膜を電解メッキ法に
よって選択的に形成する第2工程。
A second step of selectively forming a conductive film on the surface of the base film by electrolytic plating;

前記導電膜の表面に、導体柱を電解メッキ法によって
形成する第3工程。
A third step of forming a conductive pillar on the surface of the conductive film by an electrolytic plating method.

不要な前記下地膜を取り除き、この下地膜と前記導電
膜とからなる前記導体膜を、前記導体柱とともに低誘電
率の絶縁材料で覆い、この絶縁材料の表面を研磨して前
記絶縁膜を形成する第4工程。
The unnecessary base film is removed, the conductive film including the base film and the conductive film is covered with an insulating material having a low dielectric constant together with the conductive pillar, and the surface of the insulating material is polished to form the insulating film. The fourth step to be performed.

この絶縁膜の表面に、前記導体柱に接続する下地膜を
形成する第5工程。
A fifth step of forming a base film connected to the conductor pillar on the surface of the insulating film.

[作用] 多層配線板の表面に搭載された集積回路が発熱する
と、集積回路が発生した熱が、放熱用ビアを介して基板
に伝わる。基板は、熱伝導性に優れるため、放熱用ビア
から伝えられた熱を、効率的に放熱する。
[Operation] When the integrated circuit mounted on the surface of the multilayer wiring board generates heat, the heat generated by the integrated circuit is transmitted to the substrate via the heat dissipation via. Since the substrate has excellent thermal conductivity, the substrate efficiently dissipates heat transmitted from the heat dissipation via.

[発明の効果] 本発明は、多層配線板の表面に、集積回路を搭載する
ので、集積回路の発生した熱が、放熱用ビアを介して基
板より効率的に放熱される。この結果、集積回路の搭載
方法を複雑化することなく、搭載される集積回路が発生
する熱を、効率的に放熱することができる。
[Effect of the Invention] In the present invention, since the integrated circuit is mounted on the surface of the multilayer wiring board, the heat generated by the integrated circuit is efficiently radiated from the substrate via the heat radiation via. As a result, heat generated by the integrated circuit to be mounted can be efficiently radiated without complicating the mounting method of the integrated circuit.

[実施例] 次に、本発明の集積回路用パッケージの製造方法を、
図に示す一実施例に基づき説明する。
Example Next, a method for manufacturing a package for an integrated circuit of the present invention will be described.
Description will be made based on one embodiment shown in the drawing.

(第1の実施例の構成) 第1図ないし第11図は、本発明の第1実施例を示し、
第1図は、集積回路を搭載した集積回路用パッケージの
断面図を示す。
(Configuration of First Embodiment) FIGS. 1 to 11 show a first embodiment of the present invention.
FIG. 1 is a sectional view of an integrated circuit package on which an integrated circuit is mounted.

集積回路用パッケージ1は、基板2と、この基板2の
一方の面に形成された多層配線板3とを備え、この多層
配線板3の表面に集積回路4が1つ、あるいは複数搭載
されている。
The integrated circuit package 1 includes a substrate 2 and a multilayer wiring board 3 formed on one surface of the substrate 2. One or a plurality of integrated circuits 4 are mounted on the surface of the multilayer wiring board 3. I have.

○基板2は、熱伝導性に優れた絶縁性材料(例えばアル
ミナ、窒化アルミニウム等)よりなる多層配設基板2で
ある。具体的に、アルミナを用いた基板2を例に示す。
アルミナを主原料として作成されたグリーンシートに配
線パターン5をプリントする。次いで、このグリーンシ
ートを複数積載し、加湿雰囲気の水素炉中で、高温焼成
して形成されている。そして、基板2内の配線パターン
5は、下述する多層配線板3の導通用ビア6と任意に接
続される。また、基板2内の配線パターン5は、基板2
に固着された複数のピン7に接続されている。
The substrate 2 is a multi-layer substrate 2 made of an insulating material having excellent thermal conductivity (eg, alumina, aluminum nitride, etc.). Specifically, a substrate 2 using alumina is shown as an example.
The wiring pattern 5 is printed on a green sheet made of alumina as a main material. Next, a plurality of the green sheets are stacked and fired at a high temperature in a hydrogen furnace in a humid atmosphere. The wiring pattern 5 in the substrate 2 is arbitrarily connected to the conductive via 6 of the multilayer wiring board 3 described below. The wiring pattern 5 in the substrate 2 is
Are connected to a plurality of pins 7 fixed to the respective pins.

○多層配線板3は、低誘電率の絶縁材料(例えば、ポリ
イミド樹脂)よりなる絶縁膜8と、導体膜10とからなる
配線層11を多数積層したものである。
The multilayer wiring board 3 is formed by laminating a large number of wiring layers 11 each including an insulating film 8 made of an insulating material having a low dielectric constant (for example, polyimide resin) and a conductive film 10.

この多層配線板3は、基板2の表面から、搭載される
集積回路4に達する放熱用ビア12が、複数形成されてい
る。つまり、放熱用ビア12は、熱伝導性に優れた略棒体
で、搭載される集積回路4と、基板2とを熱的に連結す
る手段である。
The multilayer wiring board 3 is provided with a plurality of heat dissipation vias 12 extending from the surface of the substrate 2 to the integrated circuit 4 to be mounted. In other words, the heat dissipation via 12 is a substantially rod body having excellent thermal conductivity and is a means for thermally connecting the integrated circuit 4 to be mounted and the substrate 2.

次に、この放熱用ビア12の製造工程を、第2図ないし
第11図を用いて説明する。
Next, a manufacturing process of the heat dissipation via 12 will be described with reference to FIGS.

a1)まず、基板2の表面に、電解メッキの下地となる導
電性の下地膜13(例えば、Crの薄膜の表面にCuの薄膜を
形成した2層の金属膜)をスパッタリングにより形成す
る(第2図参照)。
a1) First, a conductive base film 13 (for example, a two-layer metal film in which a Cu thin film is formed on the surface of a Cr thin film) serving as a base for electrolytic plating is formed on the surface of the substrate 2 by sputtering. 2).

b1)下地膜13の上に、フォトレジスト14を塗布し、パタ
ーン感光を行った後、現像処理により導体膜10が形成さ
れる部分のみ、フォトレジスト14を除去する(第3図参
照)。なお、導体膜10の幅は、下述する導体柱15の径と
ほぼ同じか、あるいは導体柱15の径より僅かに広く形成
される。
b1) A photoresist 14 is applied on the base film 13, and after pattern exposure is performed, the photoresist 14 is removed only in a portion where the conductor film 10 is formed by a development process (see FIG. 3). The width of the conductor film 10 is formed to be substantially the same as the diameter of the conductor pillar 15 described below, or slightly larger than the diameter of the conductor pillar 15.

c1)フォトレジスト14が除去された部分に、電解電解メ
ッキによってCuや、Cu−Niによる、導電膜16を形成する
(第4図参照)。
c1) A conductive film 16 made of Cu or Cu-Ni is formed by electrolytic electrolytic plating on the portion where the photoresist 14 has been removed (see FIG. 4).

d1)次いで、フォトレジスト17を塗布し、露光、現像工
程を経て、口径20〜200μmのビアホールを形成する
(第5図参照)。
d1) Next, a photoresist 17 is applied, and through exposure and development processes, a via hole having a diameter of 20 to 200 μm is formed (see FIG. 5).

e1)導電性および熱伝導性に優れるCuの電解メッキによ
って、d1)で形成されたビアホール内に、導電柱15を形
成する(第6図参照)。
e1) Conductive pillars 15 are formed in the via holes formed in d1) by electrolytic plating of Cu having excellent conductivity and thermal conductivity (see FIG. 6).

f1)不要なフォトレジスト17を除去した後、エッチング
処理によって、不要な下地膜膜13を除去する(第7図参
照)。この工程によって、下地膜13および導電膜16から
なる導体膜10が形成される。
f1) After removing the unnecessary photoresist 17, the unnecessary underlying film 13 is removed by etching (see FIG. 7). Through this step, the conductor film 10 including the base film 13 and the conductive film 16 is formed.

g1)導体柱15を覆うよう、誘電率が低く、耐熱性にも優
れた絶縁材料であるポリイミド樹脂18を塗布し、硬化さ
せる(第8図参照)。
g1) A polyimide resin 18 which is an insulating material having a low dielectric constant and excellent heat resistance is applied so as to cover the conductor pillars 15 and cured (see FIG. 8).

h1)硬化したポリイミド樹脂18の表面を研磨して、導体
柱15の頭部を露出させる(第9図参照)。この工程によ
って厚さ、例えば20μmの絶縁膜8が形成される。
h1) The surface of the cured polyimide resin 18 is polished to expose the head of the conductor post 15 (see FIG. 9). By this step, an insulating film 8 having a thickness of, for example, 20 μm is formed.

つまり、上記a1)〜h1)までの工程で、配線層11が1
層形成される。
That is, in the steps a1) to h1), the wiring layer 11
A layer is formed.

i1)絶縁膜8の表面に、下地膜13をスパッタリングによ
り形成し、続いて、フォトレジスト19を塗布し、パター
ン感光を行った後、現像処理により導体膜10が形成され
る部分のみ、フォトレジスト19を除去する(第10図参
照)。
i1) A base film 13 is formed on the surface of the insulating film 8 by sputtering, a photoresist 19 is applied, pattern exposure is performed, and then only the portion where the conductor film 10 is formed by the development process is subjected to photoresist. 19 is removed (see FIG. 10).

その後、上記のc1)〜i1)の工程を繰り返すことによ
って、配線層11が積層され、基板2の表面から、搭載さ
れる集積回路4に達する放熱用ビア12を複数備えた多層
配線板3が形成される。
Thereafter, by repeating the above-described steps c1) to i1), the wiring layer 11 is laminated, and the multilayer wiring board 3 having a plurality of heat dissipation vias 12 reaching the integrated circuit 4 from the surface of the substrate 2 is obtained. It is formed.

つまり、上記a1)が本発明の第1工程を示し、上記b
1)、c1)が本発明の第2工程を示し、上記d1)、e1)
が本発明の第3工程を示し、上記f1)、g1)、h1)が本
発明の第4工程を示し、上記i1)が本発明の第5工程を
示す。
That is, the above a1) represents the first step of the present invention, and the above b)
1) and c1) represent the second step of the present invention, and the above d1) and e1)
Indicates the third step of the present invention, f1), g1) and h1) indicate the fourth step of the present invention, and i1) indicates the fifth step of the present invention.

j1)そして、多層配線板3の表面は、最後のi1)の工程
で、フォトレジスト19が除去された部分に、導電膜16を
形成する。その後、不要なフォトレジスト19、および下
地膜13の不要部分を除去する(第11図参照)。
j1) Then, on the surface of the multilayer wiring board 3, a conductive film 16 is formed in the portion where the photoresist 19 has been removed in the last step i1). Thereafter, unnecessary portions of the photoresist 19 and the base film 13 are removed (see FIG. 11).

なお、集積回路4が搭載される部分の多層配線板3の
表面は、導体膜10によって覆われ、集積回路4とボンデ
ィングワイヤ20を介して接続される導通用の導体膜10と
ともに、金電解メッキが施されている。
The surface of the multilayer wiring board 3 where the integrated circuit 4 is mounted is covered with a conductive film 10 and, together with the conductive film 10 for conduction which is connected to the integrated circuit 4 via the bonding wires 20, is subjected to gold electrolytic plating. Is given.

また、上記の放熱用ビア12は、多層配線板3内の信号
用、電源用、あるいはアース用の導通用ビア6と、同時
に形成される。
The heat dissipation vias 12 are formed at the same time as the signal, power, or ground conduction vias 6 in the multilayer wiring board 3.

上記よりなる集積回路用パッケージ1は、放熱用ビア
12が配された部分の多層配線板3の表面に、ICや、LS
I、あるいは超LSI等の集積回路4が搭載される。そし
て、搭載された集積回路4は、ボンディングワイヤ20に
よって、多層配線板3の表面の導通用の導体膜10に接続
され、導通用ビア6、基板2内の配線パターン5を介し
て、基板2に固着されたピン7と電気的に接続される。
そして、集積回路4が搭載された集積回路用パッケージ
1は、封止用キャップ21が取り付けられ、集積回路4が
封止される。
The integrated circuit package 1 having the above structure is provided with a heat dissipation via.
IC, LS, etc. are placed on the surface of the multilayer wiring board 3 where the 12 is disposed.
An integrated circuit 4 such as I or super LSI is mounted. Then, the mounted integrated circuit 4 is connected to the conductive film 10 on the surface of the multilayer wiring board 3 by bonding wires 20, and is connected to the substrate 2 via the conductive via 6 and the wiring pattern 5 in the substrate 2. Is electrically connected to the pin 7 fixed to the
Then, the sealing package 21 is attached to the integrated circuit package 1 on which the integrated circuit 4 is mounted, and the integrated circuit 4 is sealed.

(実施例の作用) 多層配線板3に形成された放熱用ビア12の作用を説明
する。
(Operation of Embodiment) The operation of the heat dissipation via 12 formed in the multilayer wiring board 3 will be described.

多層配線板3の表面に搭載された集積回路4が発熱す
ると、集積回路4が発生した熱が、集積回路4の搭載部
分に形成された導体膜10、複数の放熱用ビア12を介して
基板2に伝わる。具体的には、集積回路4の熱が、表面
の導体膜10、導体柱15、導体膜10、導体柱15、導体膜10
…と伝わり、最後に熱が基板2に伝わる。基板2は、熱
伝導性に優れ、面積も多層配線板3に比較して広い。こ
のため、放熱用ビア12から伝えられた熱を、基板2が効
率的に空気中に放熱する。
When the integrated circuit 4 mounted on the surface of the multilayer wiring board 3 generates heat, the heat generated by the integrated circuit 4 is transferred to the substrate via the conductor film 10 formed on the mounting portion of the integrated circuit 4 and the plurality of heat dissipation vias 12. Transfer to 2. Specifically, the heat of the integrated circuit 4 is transferred to the conductor film 10, the conductor pillar 15, the conductor film 10, the conductor pillar 15, and the conductor film 10 on the surface.
, And finally heat is transmitted to the substrate 2. The substrate 2 has excellent thermal conductivity and an area larger than that of the multilayer wiring board 3. Therefore, the substrate 2 efficiently radiates the heat transmitted from the heat radiation via 12 into the air.

(実施例の効果) 例えば、発熱量の多い集積回路4を搭載しても、発生
した熱は、複数の放熱用ビア12を介して基板2に伝えら
れ、基板2によって効率的に放熱される。このため、従
来に比較して、搭載可能な集積回路4の範囲が広がる。
(Effects of the Embodiment) For example, even when the integrated circuit 4 generating a large amount of heat is mounted, the generated heat is transmitted to the substrate 2 through the plurality of heat radiation vias 12 and is efficiently radiated by the substrate 2. . For this reason, the range of the integrated circuit 4 that can be mounted is expanded as compared with the related art.

搭載される集積回路4の搭載方法は、従来と同じフェ
ースアップ(配線面が表面に向く)であるため、ボンデ
ィングワイヤ20を容易に接合することができる。また、
集積回路4の裏面が多層配線板3に接合されるため、集
積回路4を集積回路用パッケージ1へ容易に搭載するこ
とができる。
The mounting method of the integrated circuit 4 to be mounted is the same face-up as the conventional one (the wiring surface faces the surface), so that the bonding wires 20 can be easily bonded. Also,
Since the back surface of the integrated circuit 4 is bonded to the multilayer wiring board 3, the integrated circuit 4 can be easily mounted on the integrated circuit package 1.

また、発生する熱を効率的に放熱するため、高速処理
日の集積回路4を、高密度に搭載することが可能とな
る。この結果、軽量、小型で、高速、高機能な電気回路
を実現できる。
In addition, since the generated heat is efficiently dissipated, the integrated circuits 4 on the high-speed processing day can be mounted at a high density. As a result, a lightweight, compact, high-speed, high-performance electric circuit can be realized.

さらに、放熱用ビア12は、導通用ビア16と同時に形成
される。このため、放熱用ビア12を形成するための特別
な装置が不要となるとともに、放熱用ビア12のための製
造工程も不要となる。この結果、放熱用ビア12を備えた
集積回路用パッケージ1を、低いコストで提供できる。
Further, the heat dissipation via 12 is formed simultaneously with the conduction via 16. For this reason, a special device for forming the heat dissipation via 12 is not required, and a manufacturing process for the heat dissipation via 12 is also unnecessary. As a result, the integrated circuit package 1 having the heat dissipation vias 12 can be provided at low cost.

(第2実施例) 第12図ないし第19図は、本発明の第2実施例を示す。
本実施例は、多層配線板(第1実施例参照)の製造方法
の変形例を示す(第4工程の変形例)。本実施例は、要
求される絶縁膜8が比較的厚く、電解メッキによる導体
柱15の形成では、十分な高さが得られない場合に好適な
ものである。なお、上記実施例と同一符号は、同一機能
物を示す。
(Second Embodiment) FIGS. 12 to 19 show a second embodiment of the present invention.
This embodiment shows a modification of the method for manufacturing the multilayer wiring board (see the first embodiment) (a modification of the fourth step). This embodiment is suitable when the required insulating film 8 is relatively thick and a sufficient height cannot be obtained by forming the conductor pillars 15 by electrolytic plating. Note that the same reference numerals as those in the above embodiment indicate the same functional objects.

a2)第1実施例のa1)〜f1)と同様な工程で、基板2の
表面に、導体膜10と導体柱15とが形成される(第12図参
照)。
a2) In the same steps as a1) to f1) of the first embodiment, a conductor film 10 and a conductor pillar 15 are formed on the surface of the substrate 2 (see FIG. 12).

b2)次いで、導体柱15が埋没し、十分な厚さのポリイミ
ド樹脂18を塗布し、硬化させる(第13図参照)。
b2) Next, the conductor pillars 15 are buried, and a sufficiently thick polyimide resin 18 is applied and cured (see FIG. 13).

c2)硬化したポリイミド樹脂18の表面を研磨する(第14
図参照)。この工程によって厚さ、例えば30μmの絶縁
膜8が形成される。この実施例では、絶縁膜8が厚いた
め、絶縁膜8の表面から、導体柱15は露出しない。
c2) Polish the surface of the cured polyimide resin 18 (No. 14)
See figure). Through this step, an insulating film 8 having a thickness of, for example, 30 μm is formed. In this embodiment, since the insulating film 8 is thick, the conductor pillar 15 is not exposed from the surface of the insulating film 8.

d2)絶縁膜8の表面に、プラズマエッチング用マスクと
して、アルミニウム薄膜22をスパッタリングにより形成
する(第15図参照)。
d2) On the surface of the insulating film 8, an aluminum thin film 22 is formed by sputtering as a plasma etching mask (see FIG. 15).

e2)アルミニウム薄膜22の上に、フォトレジスト23を塗
布し、パターン感光を行った後、現像処理により導体柱
15の上方部分のみ、フォトレジスト23を除去する(第16
図参照)。
e2) A photoresist 23 is coated on the aluminum thin film 22 and subjected to pattern exposure.
The photoresist 23 is removed only in the upper part of the 15 (16th
See figure).

f2)続いて、エッチング処理によって、不要なアルミニ
ウム薄膜22を除去する(第17図参照)。
f2) Subsequently, unnecessary aluminum thin film 22 is removed by etching (see FIG. 17).

g2)さらに、O2プラズマエッチングによって、不要なフ
ォトレジスト23、および導体柱15の上部の絶縁膜8の一
部を除去する(第18図参照)。この処理によって、導体
柱15の頭頂部が露出する。
g2) Further, unnecessary photoresist 23 and part of the insulating film 8 on the conductor pillar 15 are removed by O 2 plasma etching (see FIG. 18). By this processing, the top of the conductor pillar 15 is exposed.

h2)そして、アルミニウム薄膜22を除去し、絶縁膜8の
表面に第1実施例のi1)、j1)と同じ工程で、下地膜13
および導電額16からなる導体膜10を形成する(第19図参
照)。
h2) Then, the aluminum thin film 22 is removed, and the base film 13 is formed on the surface of the insulating film 8 in the same step as i1) and j1) of the first embodiment.
Then, a conductor film 10 made of a conductive frame 16 is formed (see FIG. 19).

そして、上記の工程を繰り返すことによって、配線層
11が積層され、複数の放熱用ビア12を備えた多層配線板
3が形成される。
Then, by repeating the above steps, the wiring layer
11 are laminated to form a multilayer wiring board 3 having a plurality of heat dissipation vias 12.

(第3実施例) 第20図ないし第24図は、本発明の第3実施例を示す。
本実施例も、多層配線板(第1実施例参照)の製造方法
の変形例を示す(第4工程の変形例)。本実施例は、導
体膜10の表面に形成される膜の密着度合いを高くしたも
のである。なお、上記実施例と同一符号は、同一機能物
を示す。
(Third Embodiment) FIGS. 20 to 24 show a third embodiment of the present invention.
This embodiment also shows a modification of the method for manufacturing the multilayer wiring board (see the first embodiment) (a modification of the fourth step). In the present embodiment, the degree of adhesion of the film formed on the surface of the conductor film 10 is increased. Note that the same reference numerals as those in the above embodiment indicate the same functional objects.

a3)第1実施例のa1)〜h1)と同様な工程で、表面の研
磨された配線層11が形成される(第20図参照)。
a3) In the same steps as a1) to h1) of the first embodiment, a wiring layer 11 having a polished surface is formed (see FIG. 20).

b3)研磨された配線層11の表面に、再度絶縁膜8と同素
材のポリイミド樹脂を塗布し、所定の温度で硬化させ、
絶縁薄膜24を形成する(第21図参照)。
b3) A polyimide resin of the same material as the insulating film 8 is applied again on the polished surface of the wiring layer 11 and cured at a predetermined temperature.
An insulating thin film 24 is formed (see FIG. 21).

c3)その絶縁薄膜24の表面に、フォトレジスト25を塗布
する(第22図参照)。
c3) A photoresist 25 is applied to the surface of the insulating thin film 24 (see FIG. 22).

d3)露光、現像工程、および絶縁薄膜24のエッチング工
程を経て、導体柱15の頭頂部を露出させる(第23図参
照)。
d3) Exposure, development, and etching of the insulating thin film 24 expose the top of the conductive pillar 15 (see FIG. 23).

e3)次いで、フォトレジスト25を除去し、ポリイミド樹
脂を硬化させる(第24図参照)。これにより、研磨され
た絶縁膜8の表面に、絶縁薄膜24が形成され、結果とし
て、表面に絶縁薄膜24を備えた配線層11が形成される。
e3) Next, the photoresist 25 is removed, and the polyimide resin is cured (see FIG. 24). Thus, the insulating thin film 24 is formed on the polished surface of the insulating film 8, and as a result, the wiring layer 11 having the insulating thin film 24 on the surface is formed.

そして、上記の工程を繰り返すことによって、配線層
11が積層され、複数の放熱用ビア12を備えた多層配線板
3が形成される。
Then, by repeating the above steps, the wiring layer
11 are laminated to form a multilayer wiring board 3 having a plurality of heat dissipation vias 12.

(変形例) なお、本実施例では、基板2によって集積回路4の熱
を放熱させた例を示したが、基板2に放熱器を取り付
け、放熱用ビア12を介して基板2に伝えられた熱を放熱
器によって効率的に空気中に放熱させても良い。
(Modification) In the present embodiment, an example in which the heat of the integrated circuit 4 is radiated by the substrate 2 is shown. However, a radiator is attached to the substrate 2, and the heat is transmitted to the substrate 2 via the heat radiation via 12. The heat may be efficiently radiated into the air by the radiator.

また、実施例中に記載した数値(厚みや、幅、径、高
さなど)や材質は、一例を示したものであって、これら
の数値や材質に本発明が限定されるものではない。
The numerical values (thickness, width, diameter, height, etc.) and materials described in the examples are merely examples, and the present invention is not limited to these numerical values and materials.

【図面の簡単な説明】[Brief description of the drawings]

第1図ないし第11図は本発明の第1実施例を示すもの
で、第1図は集積回路を搭載した集積回路用パッケージ
の断面図、第2図ないし第11図は放熱用ビアの製造工程
を示す説明図である。 第12図ないし第19図は第2実施例で示す放熱用ビアの製
造工程の説明図である。 第20図ないし第24図は第3実施例を示す放熱用ビアの製
造工程の説明図である。 図中 1……集積回路用パッケージ 2……基板、3……多層配線板 4……集積回路、8……絶縁膜 10……導体膜、11……配線層 12……放熱用ビア、13……下地膜 15……導体柱、16……導電膜
1 to 11 show a first embodiment of the present invention. FIG. 1 is a sectional view of an integrated circuit package on which an integrated circuit is mounted, and FIGS. It is explanatory drawing which shows a process. FIG. 12 to FIG. 19 are explanatory views of the manufacturing process of the heat dissipation via shown in the second embodiment. FIG. 20 to FIG. 24 are explanatory views of the manufacturing steps of the heat dissipation via showing the third embodiment. In the figure, 1 ... Package for integrated circuit 2 ... Board, 3 ... Multilayer wiring board 4 ... Integrated circuit, 8 ... Insulating film 10 ... Conductor film, 11 ... Wiring layer 12 ... Heat dissipation via, 13 …… underlayer 15 …… conducting pillars, 16 …… conductive film

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】熱伝導性に優れた基板と、この基板の表面
に設けられ、低誘電率の絶縁膜と導体膜とからなる配線
層を、多数積層した多層配線板とを具備し、この多層配
線板の表面に、集積回路が搭載される集積回路用パッケ
ージにおいて、 前記多層配線板は、前記基板から前記集積回路に達する
放熱用ビアを備え、 この放熱用ビアを備えた前記多層配線板は、次の第1工
程後、第2工程ないし第5工程を順次繰り返して形成さ
れることを特徴とする集積回路用パッケージの製造方
法。 前記基板の表面に電解メッキの下地となる導電性の下地
膜を形成する第1工程。 この下地膜の表面に導電性の導電膜を電解メッキ法によ
って選択的に形成する第2工程。 前記導電膜の表面に、導体柱を電解メッキ法によって形
成する第3工程。 不要な前記下地膜を取り除き、この下地膜と前記導電膜
とからなる前記導体膜を、前記導体柱とともに低誘電率
の絶縁材料で覆い、この絶縁材料の表面を研磨して前記
絶縁膜を形成する第4工程。 この絶縁膜の表面に、前記導体柱に接続する下地膜を形
成する第5工程。
1. A multi-layer wiring board comprising a substrate having excellent thermal conductivity and a plurality of wiring layers provided on a surface of the substrate and comprising an insulating film having a low dielectric constant and a conductive film. An integrated circuit package on which an integrated circuit is mounted on a surface of a multilayer wiring board, wherein the multilayer wiring board includes a heat dissipation via extending from the substrate to the integrated circuit, and the multilayer wiring board including the heat dissipation via Is a method for manufacturing a package for an integrated circuit, which is formed by sequentially repeating the second to fifth steps after the first step. A first step of forming a conductive base film serving as a base for electrolytic plating on the surface of the substrate; A second step of selectively forming a conductive film on the surface of the base film by electrolytic plating; A third step of forming a conductive pillar on the surface of the conductive film by an electrolytic plating method. The unnecessary base film is removed, the conductive film including the base film and the conductive film is covered with an insulating material having a low dielectric constant together with the conductive pillar, and the surface of the insulating material is polished to form the insulating film. The fourth step to be performed. A fifth step of forming a base film connected to the conductor pillar on the surface of the insulating film.
JP1244766A 1989-09-20 1989-09-20 Manufacturing method of package for integrated circuit Expired - Fee Related JP2656120B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1244766A JP2656120B2 (en) 1989-09-20 1989-09-20 Manufacturing method of package for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1244766A JP2656120B2 (en) 1989-09-20 1989-09-20 Manufacturing method of package for integrated circuit

Publications (2)

Publication Number Publication Date
JPH03106061A JPH03106061A (en) 1991-05-02
JP2656120B2 true JP2656120B2 (en) 1997-09-24

Family

ID=17123588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1244766A Expired - Fee Related JP2656120B2 (en) 1989-09-20 1989-09-20 Manufacturing method of package for integrated circuit

Country Status (1)

Country Link
JP (1) JP2656120B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007227881A (en) * 2005-11-14 2007-09-06 Tdk Corp Composite wiring board, and method of manufacturing same

Also Published As

Publication number Publication date
JPH03106061A (en) 1991-05-02

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