JPH06326471A - Multilayered wiring board - Google Patents

Abstract

PURPOSE:To provide a multilayered wiring board wherein the whole surface of a board can be effectively used, large thermal conductivity is obtained, viaholes are devided into a plurality of layers without generating unevenness on the surface, and the cost is reduced. CONSTITUTION:In a multilayered wiring board having contacts 1, 5 for connecting wiring layers with one another which are separated to be at least two or more layers, a wide conductive pattern 3 which contains the enveloping region of viaholes 2, 4 formed between the wiring layers is formed on a halfway wiring layer through which the contacts pass. Patterns 2, 4 which do not overlap between adjacent wiring layers are formed by using the viaholes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board,
In particular, it relates to a thermal via hole for heat dissipation.

[0002]

2. Description of the Related Art Various IC parts are mounted on the surface of a multilayer wiring board such as a silicon wafer board or a printed board.
In order to dissipate heat generated from these IC components through the substrate, a thermal via hole is formed in the IC component mounting portion of the substrate.

An example of a conventional thermal via hole is shown in FIG. An insulating layer 12 is provided on a substrate 13, and a plurality of wiring patterns 11 are formed inside. A pad pattern 16 is formed on the surface of the insulating layer 12. On the pad pattern 16, a lead terminal of an IC component (not shown) is soldered or a wire is bonded. The via hole 10 is formed in order to dissipate the heat from the IC component or the like through the substrate 13.

On the other hand, as another heat dissipation method in the conventional multilayer wiring board, as shown in FIG. 5, a structure in which the IC chip 14 is embedded in the board has been used. This structure forms a recess 15 in the insulating layer 12 on the substrate 13
The IC chip 14 is embedded in the inside to transfer heat to the side of the substrate 13 to be dissipated.

[0005]

However, in the conventional thermal via hole shown in FIG. 4, since the upper and lower parts are communicated with each other by one continuous via hole 10, the inside of the via hole 10 is made of a metal having a large heat transfer coefficient. There was a problem that it was necessary to bury it and the cost increased. In this case, if the diameter is simply changed for each of the plurality of insulating layers to form a narrow via hole portion, when patterning the metal sequentially for each layer to connect the via holes,
This causes a problem that the surface of the substrate is not flattened and unevenness is caused, which hinders component mounting.

Further, in the chip burying structure shown in FIG. 5, there is a problem that the wiring pattern cannot be formed in the recess 15 and the effective use area of the substrate is reduced.

The present invention has been made in view of the above-mentioned drawbacks of the prior art. It is possible to effectively use the entire surface of the substrate, obtain a large heat transfer coefficient, and divide the via hole into a plurality of layers without causing unevenness on the surface. An object of the present invention is to provide a multi-layer wiring board with reduced cost.

[Means for Solving the Problems]

In order to achieve the above-mentioned object, in the present invention, in a multilayer wiring board having a contact connecting wiring layers separated by at least two layers or more, a wiring layer formed in the middle of the contact is formed between wiring layers. In addition to forming a wide conductive pattern including the envelope area of the via hole, the via hole forms a pattern that does not overlap between adjacent wiring layers.

In a preferred embodiment, the via hole formed between the wiring layers is formed in a circular shape between the first wiring layers and in a ring shape excluding the circular portion between the wiring layers adjacent to the first wiring layer. . .

In another preferred embodiment, the via holes formed between the wiring layers have a checkered shape between the first wiring layers and a checkerboard formed between the first wiring layers between the wiring layers adjacent to the first wiring layer. It is formed in a checkered shape that is complementary to the shape.

When manufacturing the multilayer wiring board according to the present invention, the manufacturing process includes the steps of forming an insulating layer on the board, forming a first conductor pattern on the insulating layer, and the first step. Patterning and forming a part of the heat conduction via hole in the outer area of the conductor pattern in the region, and forming a part of the via hole on the pattern having the same shape as the first conductor pattern. Forming a second conductor pattern, patterning and forming a remaining portion within the outline of the via hole on the second conductor pattern, and forming the first portion on the pattern of the remaining portion of the via hole. Forming a third conductor pattern having the same shape as the conductor pattern of FIG.

[0012]

[Function] The via hole is formed by dividing a wide conductor pattern including the outer shape (envelope) of the via hole, and the pattern shapes of adjacent via holes sandwiching the conductor pattern of the intermediate layer are mutually non-overlapping shapes. Thus, the pattern surface of the pad conductor pattern formed on the uppermost surface is flattened.

[0013]

1 is a sectional view of a thermal via hole portion of a multilayer wiring board according to an embodiment of the present invention. For example, a first insulating layer 8 made of polyimide is provided on a substrate 9 made of, for example, a silicon wafer or aluminum, and a second insulating layer 7 and a third insulating layer 6 also made of polyimide are laminated thereon. A first conductor pattern 5 made of a metal such as aluminum or copper is formed on the first insulating layer 8. The first conductor pattern 5 is a wide pattern including the outer shape envelope of the thermal via hole. A first-layer via hole 4 made of the same metal is formed on the first conductor pattern 5, and a second conductor pattern 3, a second-layer via hole 2 and a third conductor pattern 1 are sequentially formed thereon. Stacked. The first, second and third conductor patterns 5, 3, 1 have the same shape. The second
The via holes 2 and 4 of the first layer and the second layer, which are stacked with the conductor pattern 3 sandwiched therebetween, have mutually non-overlapping patterns. That is, the first layer via hole 4 constitutes a part of the outer shape of the entire via hole,
The remaining portion constitutes the second-layer via hole 2.

FIG. 2 is a plan view showing the pattern shape of each layer in the via hole portion of the multilayer wiring board having the above structure. In this example, the first, second and third conductor patterns 5, 3, 1
Are squares, as shown in FIGS. Further, the via hole 4 of the first layer has a checkered pattern composed of four small squares as shown in FIG. 7D, and the via hole 2 of the second layer has, as shown in FIG. The checkerboard pattern has a checkerboard pattern corresponding to the checkerboard pattern of the first-layer via hole 4, and the black and white portions are reversed. By using such a pattern shape, unevenness is formed in the via hole portion (surface of the second conductor pattern 3) in the intermediate layer according to the shape of the lower via hole 4, but this unevenness is formed on the upper side. Is canceled by the complementary shape of the via hole 2 and the third conductor pattern 1 on the uppermost surface is flattened.

In the multilayer wiring board having the above structure, the lead terminals of the IC component (not shown) are solder-bonded onto the uppermost conductor pattern 1 and the wiring pattern (via the intermediate or lowermost conductor patterns 3 and 5) (Not shown) to form a predetermined circuit. Further, the heat generated from the electronic components mounted on the surface of the substrate such as IC components is transferred to the substrate 9 side through the conductor patterns 1 and 3.5 and the via holes 2 and 4 which are made of metal having a high thermal conductivity, and are transferred to the outside. Be dissipated in.

The process for manufacturing a multilayer wiring board having such a structure is as follows. First, the first insulating layer 8 is formed on the substrate 9 using photosensitive polyimide. Next, a metal such as aluminum or copper is vapor-deposited on the entire surface of the insulating layer 8, and a rectangular first conductor pattern 5 is formed by etching by photolithography using a mask.
Next, the second insulating layer 7 is formed by spin coating of polyimide, and the first is formed by photolithography using a mask.
The via hole 4 of the layer is opened. After that, metal is vapor-deposited on the entire surface, and this is etched using the same mask as the first conductor pattern 5 to form the second conductor pattern 3.
To form. Next, the third insulating layer 6 is formed by spin coating of polyimide, and this is etched by photolithography to open the via hole 2 of the second layer. Next, metal is vapor-deposited on the entire surface, and this is etched using the same mask as the first conductor pattern 5 to form the first conductor pattern 1. As a result,
A laminated structure shown by is obtained. By repeating the same process, the conductor pattern can be further laminated on the upper side.

FIG. 3 is a plan view of each layer of a multilayer thermal via hole according to another embodiment of the present invention. The patterns of the respective layers shown in FIGS. 3A to 3E are shown in FIG.
To (E). In the example of FIG. 3, the first-layer via hole 4 is circular, and the second-layer via hole 2 is formed in an annular shape having an inner hole corresponding to the circle. By stacking such circular and complementary annular via hole patterns, a flattening of the uppermost conductor pattern 1 can be achieved as in the above-described embodiment. Other configurations and operational effects are the same as in the example of FIG.

The shape of the via hole is not limited to the rectangular checkered pattern or the circular shape described above, and various shapes that do not overlap each other can be used. Also, the number of layers to be divided is not limited to two, and the outer shape of one thermal via hole may be formed as a whole by dividing into three or more layers that do not overlap.

[0019]

As described above, in the present invention, the thermal via hole is divided into a multi-layer structure without impairing the flatness of the surface layer to reduce the cost without adding a new process and to manufacture. The reliability of the process can be increased. In addition, the metals in the upper and lower layers are always in contact with each other to suppress an increase in thermal resistance, and heat is efficiently dissipated.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a thermal via hole portion of a multilayer wiring board according to an embodiment of the present invention.

FIG. 2 is a plan view showing a pattern shape of each layer of a thermal via hole of a multilayer wiring board according to an example of the present invention.

FIG. 3 is a plan view showing a pattern shape of each layer of a thermal via hole of a multilayer wiring board according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view of an example of a conventional multilayer wiring board.

FIG. 5 is a cross-sectional view of another example of a conventional multilayer wiring board.

[Explanation of symbols]

1: Third conductor pattern, 2: Second layer via hole, 3: Second conductor pattern, 4: First layer via hole, 5: First conductor pattern, 6: Third insulating layer 7: second insulating layer, 8: first insulating layer, 9:
substrate.

Claims (4)

[Claims] 1. A multi-layer wiring board having contacts connecting wiring layers separated by at least two layers, wherein a wiring layer in the middle of passing the contacts has a wide conductive pattern including an envelope region of a via hole formed between the wiring layers. And a via hole is formed in a pattern that does not substantially overlap between adjacent wiring layers. 2. The via hole formed between the wiring layers is formed in a circular shape between the first wiring layers and in a ring shape excluding the circular portion between the wiring layers adjacent to the first wiring layer. The multilayer wiring board according to claim 1. 3. The via hole formed between the wiring layers has a checkered shape between the first wiring layers and a checkerboard shape formed between the first wiring layers between the wiring layers adjacent to the first wiring layer. The multilayer wiring board according to claim 1, wherein the multilayer wiring board is formed in a checkerboard pattern. 4. A step of forming an insulating layer on a substrate, a step of forming a first conductor pattern on the insulating layer, and a step of forming a via hole for heat conduction in the region on the first conductor pattern. Patterning and forming a part within the outer shape range, forming a second conductor pattern having the same shape as the first conductor pattern on a part of the pattern of the via hole, and the second conductor Patterning and forming the remaining portion of the via hole in the outer shape range of the via hole; and forming a third conductor pattern of the same shape as the first conductor pattern on the pattern of the remaining portion of the via hole. A method of manufacturing a multilayer wiring board, comprising: