US7307852B2 - Printed circuit board and method for manufacturing printed circuit board - Google Patents

Printed circuit board and method for manufacturing printed circuit board Download PDF

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Publication number
US7307852B2
US7307852B2 US11/062,672 US6267205A US7307852B2 US 7307852 B2 US7307852 B2 US 7307852B2 US 6267205 A US6267205 A US 6267205A US 7307852 B2 US7307852 B2 US 7307852B2
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United States
Prior art keywords
printed circuit
circuit board
capacitor
resin
formed
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US11/062,672
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US20050157478A1 (en
Inventor
Yasushi Inagaki
Motoo Asai
Dongdong Wang
Hideo Yabashi
Seiji Shirai
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Ibiden Co Ltd
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Ibiden Co Ltd
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Publication date
Priority to JP11-248311 priority Critical
Priority to JP24831199 priority
Priority to JP11-360306 priority
Priority to JP36030699 priority
Priority to JP2000-103731 priority
Priority to JP2000103730 priority
Priority to JP2000103732 priority
Priority to JP2000-103733 priority
Priority to JP2000-103730 priority
Priority to JP2000103731 priority
Priority to JP2000103733 priority
Priority to JP2000-103732 priority
Priority to JP2000/221352 priority
Priority to JP2000221354 priority
Priority to JP2000-221354 priority
Priority to JP2000221353 priority
Priority to JP2000-221351 priority
Priority to JP2000221351 priority
Priority to JP2000-221349 priority
Priority to JP2000-221353 priority
Priority to JP2000221352 priority
Priority to JP2000221349 priority
Priority to US09/830,361 priority patent/US6876554B1/en
Priority to PCT/JP2000/005972 priority patent/WO2001019149A1/en
Priority to US11/062,672 priority patent/US7307852B2/en
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of US20050157478A1 publication Critical patent/US20050157478A1/en
Application granted granted Critical
Publication of US7307852B2 publication Critical patent/US7307852B2/en
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02Mountings
    • H01G2/06Mountings specially adapted for mounting on a printed-circuit support
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/224Housing; Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
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    • H01G4/248Terminals the terminals embracing or surrounding the capacitive element, e.g. caps
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    • H01G4/40Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
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    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/162Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of H01L27/00 - H01L49/00 and H01L51/00, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. IMC (insert mounted components)
    • H05K1/183Components mounted in and supported by recessed areas of the printed circuit board
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    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. IMC (insert mounted components)
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. IMC (insert mounted components)
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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Abstract

Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Description

TECHNICAL FIELD

The present invention relates to a printed circuit board on which electric elements, such as IC chips, are mounted. More specifically, the present invention relates to a printed circuit board incorporating capacitors therein, and a method for manufacturing the same.

BACKGROUND ART

In a computer, the length of electric wiring between the power supply and the IC chip is usually long, and therefore, the loop inductance at this electric wiring is extremely large. The variation in the voltage at which the IC is driven in high-speed operation mode becomes very large accordingly, possibly causing malfunction of the IC. In addition, it becomes difficult to stabilize the voltage of the power supply. In an attempt to avoid these troubles, a capacitor is mounted on the surface of the printed circuit board as an auxiliary device for assisting the power supply operation.

Specifically, the loop inductance which causes the variation in voltage depends on the length of electric wire from a power supply shown in FIG. 72(A) to a power supply terminal 272P of an IC chip 270 through a power supply line in a printed circuit board 300, and the length of electric wire from a ground terminal 272E in the IC chip 270 to the power supply through a ground line in the printed circuit board 300 from the power supply. The loop inductance can be reduced by narrowing the distance between the electric wires through which a current in a reverse direction to each other flows, for example, the distance between the power supply line and the ground line.

Therefore, as shown in FIG. 72(B), a chip capacitor 298 is mounted on the surface of the printed circuit board 300, thereby shortening the length of electric wire between the power supply line and the ground line in the printed circuit board 300 which connects the IC chip 270 to the chip capacitor 292 to be the power supply source, as well as narrowing the distance between the electric wires.

However, the degree of the voltage drop, which causes the variation in the IC driving voltage, depends on the frequency at which the IC chip is driven. As the frequency at which the IC chip is driven increases, it becomes impossible to reduce the loop inductance even if the chip capacitor is mounted on the surface of the printed circuit board 300 as is conducted in the case shown in FIG. 72(B). As a result, it becomes difficult to sufficiently suppress the variation in the IC driving voltage.

In this situation, the present inventors have conceived to mount a chip capacitor inside the printed circuit board. As a method for embedding a capacitor into a substrate, techniques described in Japanese Unexamined Patent Publications Nos. 6-326472, 7-263619, 10-256429, 11-45955, 11-126978, 11-312868 and the like may be employed.

Japanese Unexamined Patent Publication 6-326472 discloses a technique in which a capacitor is embedded in a substrate made of resin such as glass epoxy. This structure reduces the noise in the power supply, and eliminates the need of the space for mounting the chip capacitor, thereby reducing the size of insulating substrate. Japanese Unexamined Patent Publication No. 7-263619 discloses a technique in which a capacitor is embedded into to a substrate made of ceramics or alumina. The capacitor is connected between the power supply layer and the ground layer. This structure shortens the length of electric wire and reduces the inductance of the electric wire.

However, these prior art techniques described above cannot satisfactorily shorten the distance between the IC chip and the capacitor, and also cannot reduce the inductance at the higher frequency domain of the IC chip to a level required at present. In particularly, a buildup multi-layer printed circuit board made of resin has problems such as disconnection between the terminal of the chip capacitor and the via hole, the peeling of the chip capacitor from the interlayer resin insulating layer, and the generation of cracks in the interlayer resin insulating layer, resulted from the difference in thermal expansion coefficients between the capacitor made of ceramics, and the core substrate and the interlayer resin insulating layer made of resin. These problems hinder the printed circuit board from having high reliability over a long period of time.

The present invention has been made to solve the above-described problems of the prior arts, and the objective thereof is to provide a printed circuit board capable of reducing a loop inductance and having high reliability, and a method for manufacturing the same.

DISCLOSURE OF THE INVENTION

In order to achieve the above purpose, according to claim 1, a printed circuit board is characterized by comprising a core substrate, and a resin insulating layer and a conductor circuit laminated on the core substrate, wherein a cavity is formed in the core substrate, and a plurality of capacitors are accommodated in the cavity.

In the invention recited in claim 1, a large cavity is formed in a core substrate, and a plurality of capacitors are accommodated in the cavity. With this arrangement, a plurality of capacitors can be reliably provided within the core substrate. The capacitors can be provided at places close to each other in the cavity, the package density of the capacitors can be increased. Since a plurality of capacitors are mounted within the cavity, the plurality of capacitors are aligned to the same heights with each other. A resin layer can be formed on the core substrate into a uniform thickness, and via holes can be stably formed. Since the cavity is formed in such a manner as to have a large area, the capacitors can be provided at accurate positions. As a result, an interlayer resin insulating layer and a conductor circuit can be properly formed on the core substrate, thereby lowering the rate of generating defective printed circuit boards.

The cavity is preferably filled with a resin. The resin eliminates a space between the capacitors and the core substrate. As a result, the behavior of the capacitors incorporated in the core substrate becomes small. In addition, even if the stress is generated caused by the capacitors, the stress can be alleviated by the resin charged in the space. The resin also has an effect of adhering the capacitors to the core substrate, and lowering a migration between the capacitors and the core substrate.

In the invention recited in claim 2, a resin is charged between the capacitors in the cavity. With this arrangement, the capacitors can be fixed in the cavity after deciding their positions in the capacitors. The thermal expansion coefficient of the resin is made to be smaller than a thermal expansion coefficient of the core substrate, that is, is set to the value close to that of the chip capacitor made of ceramics. In this manner, even if internal stress is generated between the core substrate and the capacitors caused by the difference in the thermal expansion coefficients therebetween, cracks and peelings do not easily occur in the core substrate. As a result, high reliability can be attained. In addition, no migration is generated, and the connection with the capacitors is stabilized.

In the invention recited in claim 3, a through hole is formed between the capacitors in the resin layer, and a signal line does not pass through the chip capacitors. This structure eliminates the problems that the impedance becomes discontinuous by the high dielectric body to generate a reflection, and that the transmission is delayed by passing through the high dielectric body.

The through holes enable the establishment of an electric connection between the front surface and the back surface of the printed circuit board. In addition, a wire can be provided below the capacitors through the buildup layer, and pins and BGAs for the capacitors can be provided.

In the invention recited in claim 4, an electric connection for electrodes formed with a metal film of the capacitors is established by via holes formed by plating. The electrodes of the chip capacitor are made by metallizing, and have pits and projections on their surfaces. However, the surfaces become smooth by formation of the metal film, and the via holes are then formed on the smooth surfaces. In this manner, when penetrating openings are formed in the resin coating the electrodes, no resin remains, and a reliability of the connection between the via holes and the electrodes can be increased. Furthermore, since the via holes are made by plating into the electrodes formed with the copper plated film, the electrodes are firmly connected to the via holes. No disconnection occurs between the electrodes and via holes even when a heat cycle test is conducted.

The metal film formed on the electrodes of the capacitors preferably includes any one of metals selected from the group consisting of copper, nickel, and noble metals. Tins and zinc are not preferable, because if the capacitors incorporated in the printed circuit board have a film including these metals formed on their electrodes, a migration is easily generated at a connection with the via holes.

The surfaces of the chip capacitors may be roughened. The rough surface contributes to an increased adhesion between the chip capacitors made of ceramic, and a connection layer and a resin insulating layer made of resin, thereby avoiding the resin insulating layer from peeling from the interface with the chip capacitors even when a heat cycle test is conducted.

In the invention recited in claim 6, the chip capacitors are accommodated in the printed circuit board in the state where at least a part of the electrodes of each capacitor is uncoated with a coating layer and exposed to the outside. An electric connection for the electrode exposed from the coating layer is established. The metal exposed from the coating layer includes copper as a main component, because the connection resistance can be lowered.

In the invention recited in claim 7, a chip capacitor in which electrodes are formed along an inside of the outer edge thereof is used. With this arrangement, a large space can be used for external electrodes even if a conduction is established through the via holes, and therefore, the broadened range of alignment is allowed. As a result, a problem of disconnection is eliminated.

In the invention recited in claim 8, a chip capacitor in which electrodes are formed in matrix is used. It becomes easy to accommodate a large chip capacitor in a core substrate. Therefore, it becomes possible to increase an electrostatic capacity, and a problem concerning electricity can be solved. In addition, warpage is hard to generate in the printed circuit board even if the printed circuit board undergoes various thermal histories.

A plurality of chip capacitors from each of which a plurality of pieces are to be obtained may, be coupled into one piece unit and used. In this manner, an electrostatic capacity can be properly adjusted and the IC chip can be properly operated.

In the invention recited in claim 9, a capacitor is mounted on the surface of the printed circuit board on top of the capacitors accommodated in the substrate. Since the capacitors are accommodated within the printed circuit board, the distance between the IC chip and each capacitor is shortened. In addition, the loop inductance can be lowered, and electric power can be instantaneously provided. On the other hand, since a capacitor is provided on the surface of the printed circuit board as well, a capacitor having a large capacity can be mounted. In this manner, large electric power can be easily supplied to the IC chip.

A method for manufacturing a printed circuit board according to claim 10 is characterized by comprising at least the following steps (a) to (c):

(a) forming a cavity in a core substrate;

(b) mounting a plurality of capacitors in the cavity; and

(c) charging a resin between the capacitors.

In the invention recited in claim 10, a large cavity is formed in a core substrate. With this arrangement, a plurality of capacitors can be reliably provided in the core substrate. In addition, since a plurality of capacitors are mounted in the cavity, the plurality of capacitors are aligned to the same heights with each other. As a result, the surface of the core substrate becomes flat and smooth. In addition, the cavity is formed in such a manner as to have a large area, the capacitors can be located at accurate positions. The interlayer resin insulating layer and the conductor circuit can be properly formed on the core substrate without impairing the flatness and smoothness of the core substrate. Therefore, the rate of generating defective printed circuit boards can be lowered. In addition, a resin is charged between the capacitors, the capacitors can be fixed in the cavity after the positions of capacitors are determined within the cavity.

In the invention recited in claim 11, a pressure is applied to the upper surfaces of the plurality of capacitors in the cavity, or tapped to align the chip capacitors into the same heights with each other. By this process, even if chip capacitors having largely different sizes from each other are provided in the cavity, they are aligned into the completely same heights with each other. As a result, the core substrate can has a flat and smooth surface. The interlayer resin insulating layer and the conductor circuit as upper layers can be properly formed on the core substrate without impairing the flatness and smoothness of the core substrate, and therefore, the rate of generating defective printed circuit boards can be lowered.

In the invention recited in claim 12, a through hole is formed between the capacitors in the resin layer. A signal line does not pass through the chip capacitors. This structure eliminates the problems that the impedance becomes discontinuous by the high dielectric body to generate a reflection, and that the transmission is delayed by passing through the high dielectric body. The through holes enable the establishment of the electric connection between the top and bottom surfaces of the printed circuit board. It is possible to provide wires under the capacitors through the buildup layer, and therefore, pins and BGAs of the capacitors can be provided.

A method for manufacturing a printed circuit board according to claim 13 is characterized by comprising at least the following steps (a) to (c):

(a) forming penetrating openings in a resin material having a core material impregnated with a resin;

(b) attaching a resin material to the resin material formed with the penetrating openings to form a core substrate having a cavity;

(c) mounting a plurality of capacitors in the cavity of the core substrate; and

(d) charging a resin between the capacitors.

In the invention recited in claim 13, a large cavity is formed in a core substrate. With this arrangement, a plurality of capacitors can be reliably provided in the core substrate. In addition, since a plurality of capacitors are mounted in the cavity, the plurality of capacitors are aligned to the same heights with each other. As a result, the surface of the core substrate becomes flat and smooth. In addition, the cavity is formed in such a manner as to have a large area, the capacitors can be located at accurate positions. The interlayer resin insulating layer and the conductor circuit can be properly formed on the core substrate without impairing the flatness and smoothness of the core substrate. Therefore, the rate of generating defective printed circuit boards can be lowered. In addition, a resin is charged between the capacitors, the capacitors can be fixed in the cavity after the positions of capacitors are determined within the cavity.

In the invention recited in claim 14, a pressure is applied to the upper surfaces of the plurality of capacitors in the cavity, or tapped to align the chip capacitors into the same heights with each other. By this process, even if chip capacitors having largely different sizes from each other are provided in the cavity, they are aligned into the completely same heights with each other. As a result, the core substrate can has a flat and smooth surface. The interlayer resin insulating layer and the conductor circuit can be properly formed on the core substrate without impairing the flatness and smoothness of the core substrate, and therefore, the rate of generating defective printed circuit boards can be lowered.

In the invention recited in claim 15, since through holes are formed between the capacitors in the resin layer, a signal line does not pass through the chip capacitors. This structure eliminates the problems that the impedance becomes discontinuous by the high dielectric body to generate a reflection, and that the transmission is delayed by passing through the high dielectric body. The through holes enables the establishment of the electric connection between the top and bottom surfaces of the printed circuit board. It is possible to provide wires under the capacitors through the buildup layer, and therefore, pins and BGAs of the capacitors can be provided.

In order to solve the above problem, a printed circuit board according to claim 16 is characterized by comprising a core substrate, and a resin insulating layer and a conductor circuit laminated on the core substrate,

wherein the core substrate incorporates a connection layer formed by an insulating resin layer including at least one or more layer, and an accommodation layer accommodating a capacitor in its spot-faced section.

It means the circuit formed by buildup method where an interlayer resin insulating layer is formed on the core substrate, and via holes or through holes are formed in the interlayer resin insulating layer to form a conductor circuit as a conductive layer. As the buildup layer, a semi-additive method or a fully-additive method may be employed.

In the invention recited in claim 16, capacitors are mounted within the printed circuit board. In this manner, the distance between the IC chip and each capacitor is shortened, and the loop inductance can be lowered. The core substrate incorporates one or more connection layers and an accommodation layer for accommodating the capacitors. Since the capacitors are accommodated within the accommodation layer having large thickness, the thickness of the core substrate does not become large. The thickness of the printed circuit board does not become large even if the interlayer resin insulating layer and the conductor circuit are laminated on the core substrate.

It is desirable to fill the cavity with a resin. As a result, the behavior of the capacitors incorporated in the core substrate becomes small. In addition, even if the stress is generated caused by the capacitors, the stress can be alleviated by the resin. The resin also has an effect of adhering the capacitors to the core substrate, and lowering a migration between the capacitors and the core substrate.

In the invention recited in claim 17, an accommodation layer is constituted by a resin substrate having a core material impregnated with a resin. As a result, sufficiently high strength can be given to the core substrate.

In the invention recited in claim 18, the connection layer and the capacitors accommodated in the accommodation layer are connected to each other through a conductive adhesive. In this manner, the electrical connection with the capacitors and the adhesion between the capacitors and the connection layer can be assured. The conductive adhesive may be a material having both conductivity and adhesiveness such as a solder (Sn/Pb, Sn/Sb, Sn/Ag, Sn/Ag/Cu), conductive pastes, and resins impregnated with metal particles.

The space created between the conductive adhesive and the capacitor is preferably filled with a resin, because, in this manner, the behavior derived from the capacitors can be alleviated and the migration of the conductive adhesive can be prevented.

In the invention recited in claim 19, a circuit which is connected to the conductive adhesive is provided between the connection layer and the accommodation layer. In this manner, a connection with the capacitors can be reliably established through the circuit. By providing a circuit constituted by a metal layer between the connection layer and the accommodation layer, the warpage of the core substrate can be prevented.

In the invention recited in claim 20, an external substrate (i.e. daughter board, mother board) to be connected to the back surface of the printed circuit board is connected to the terminals of the capacitor through the via holes formed in the connection layer and the through holes formed in the core substrate. That is, although the accommodation layer having a core material is hard to process, though holes are formed in the accommodation layer so that the terminals of the capacitors are not directly connected to the outside surface. As a result, the reliability of the connection can be increased.

In the invention recited in claim 21, a wiring for connecting an IC chip and an external substrate is provided between capacitors, and a signal line does not pass through the chip capacitors. This structure eliminates the problems that the impedance becomes discontinuous by the high dielectric body to generate a reflection, and that the transmission is delayed by passing through the high dielectric body. By mounting a capacitor for power supply, large electric power can be easily supplied to the IC chip. Furthermore, noise generated when a signal is transmitted in the printed circuit board can be reduced.

In addition, by providing a wiring for connection, it becomes possible to provide a wiring below the capacitors. In this manner, a wiring has an increased degree of freedom, thereby attaining high density and small size.

In the invention recited in claim 22, a chip capacitor in which electrodes are formed along an inside of the outer edge thereof is used. With this arrangement, a large space can be used for external electrodes even if a conduction is established through the via holes, and therefore, the broadened range of alignment is allowed. As a result, a problem of disconnection is eliminated.

In the invention recited in claim 23, a chip capacitor in which electrodes are formed in matrix is used. It becomes easy to accommodate a large chip capacitor in a core substrate. Therefore, it becomes possible to increase an electrostatic capacity, and a problem concerning electricity can be solved. In addition, warpage is hard to generate in the printed circuit board even if the printed circuit board undergoes various thermal histories.

A plurality of chip capacitors from each of which a plurality of pieces are to be obtained may be coupled to each other into one piece unit and used. In this manner, an electrostatic capacity can be properly adjusted and the IC chip can be properly operated.

In the invention recited in claim 24, a capacitor is mounted on the surface of the printed circuit board on top of the capacitors accommodated in the substrate. Since the capacitors are accommodated within the printed circuit board, the distance between the IC chip and each capacitor is shortened. In addition, the loop inductance can be lowered, and electric power can be instantaneously provided. On the other hand, since a capacitor is provided on the surface of the printed circuit board as well, a capacitor having a large capacity can be mounted. In this manner, large electric power can be easily supplied to the IC chip.

In the invention recited in claim 25, the chip capacitor mounted on the surface of the printed circuit board has an electrostatic capacity same or larger than the electrostatic capacity of the chip capacitor incorporated in the printed circuit board. In this manner, there is no shortage of power supply at a high frequency domain, and the IC chip reliably exhibits a desired operation.

In the invention recited in claim 26, the chip capacitor mounted on the surface of the printed circuit board has an inductance same or smaller than the inductance of the chip capacitor incorporated in the printed circuit board. In this manner, there is no shortage of power supply at a high frequency domain, and the IC chip reliably exhibits a desired operation

The surface of the chip capacitor may be subjected to roughening treatment. The rough surface contributes to an increased adhesion between the chip capacitor made of ceramic and a connection layer and a resin insulating layer made of resin, thereby avoiding the connection layer and the interlayer resin insulating layer from peeling from the interface with the chip capacitors even when a heat cycle test is conducted.

In the invention recited in claim 27, copper is provided around the respective chip capacitors. In this manner, no migration is generated in the capacitors incorporated in the printed circuit board. In addition, the capacitors never peel from the resin charged between the capacitors, and no cracks are created. The accommodation characteristic is enhanced, and as a result, there is no deterioration in electric characteristics.

In the invention recited in claim 28, a resin is charged between the spot-faced section of the core substrate and the capacitor. The thermal expansion coefficient of the resin is set to the value lower than the thermal expansion coefficient of the core substrate, that is, is set to the value close to that of the chip capacitor made of ceramics. In this manner, even if internal stress is generated between the core substrate and the resin insulating layer, and the chip capacitor caused by the difference in the thermal expansion coefficients therebetween, cracks and peelings do not easily occur. As a result, high reliability can be attained. In addition, the generation of migration can be prevented.

A method for manufacturing a printed circuit board according to claim 29 is characterized by comprising at least the following steps (a) to (c):

(a) forming a circuit pattern on a resin plate on its one side or both sides, and connecting a capacitor to the circuit pattern through an adhesive material;

(b) attaching a resin substrate formed with a cavity for accommodating the capacitor to the resin plate to form a core substrate; and

(c) forming openings extending to electrodes of the capacitor in the resin plate to form via holes.

In the method for manufacturing a printed circuit board of the invention recited in claim 29, it becomes possible to accommodate chip capacitors in a core substrate. As a result, a printed circuit board having a lowered loop inductance can be provided.

In the method for manufacturing a printed circuit board of the invention recited in claim 30, a resin substrate accommodating capacitors and a resin plate are attached to each other by applying a pressure from both sides to form a core substrate. Thus-formed core substrate has a flat surface. As a result, an interlayer resin insulating layer and a conductor circuit having high reliability can be laminated on the core substrate.

In the method for manufacturing a printed circuit board of the invention recited in claim 31, a through hole for an IC chip and an external substrate is provided between capacitors. A signal line does not pass through the chip capacitors 20 made of ceramics. This structure eliminates the problems that the impedance becomes discontinuous by the high dielectric body to generate a reflection, and that the transmission is delayed by passing through the high dielectric body. By mounting a capacitor for power supply, it becomes possible to easily provide large electric power to the IC chip.

In order to solve the above-described problems, in the invention recited in claim 32, a printed circuit board incorporates a core substrate, and a resin insulating layer and a conductor circuit laminated to a core substrate. The core substrate incorporates a connection layer formed by an insulating resin layer including at least one or more layer, and an accommodation layer formed by a resin layer accommodating capacitors and including two or more layers.

It means the circuit formed by buildup method where an interlayer resin insulating layer is formed on the core substrate, and via holes or through holes are formed in the interlayer resin insulating layer to form a conductor circuit as a conductive layer. As the buildup layer, a semi-additive method or a fully-additive method may be employed.

In the invention recited in claim 32, capacitors are mounted within the printed circuit board. In this manner, the distance between the IC chip and each capacitor is shortened, and the loop inductance can be lowered. The core substrate incorporates one or more connection layers and an accommodation layer for accommodating the capacitors. Since the capacitors are accommodated within the accommodation layer having large thickness, the thickness of the core substrate does not become thick. The thickness of the printed circuit board does not become thick even if the interlayer resin insulating layer and the conductor circuit are laminated on the core substrate.

It is desirable to fill the cavity with a resin. As a result, the behavior of the capacitors incorporated in the core substrate becomes small. In addition, even if the stress is generated caused by the capacitors, the stress can be alleviated by the resin. The resin also has an effect of adhering the capacitors to the core substrate, and lowering a migration between the capacitors and the core substrate.

A printed circuit board according to clam 33 is characterized by comprising a resin insulating layer and a conductor circuit laminated to the core substrate,

wherein the core substrate incorporates a connection layer formed by an insulating resin layer including at least one or more layer, and an accommodation layer formed by a resin layer accommodating a capacitor and including two or more layers, and vias for establishing a connection with the capacitor are formed on both sides of the core substrate.

In the invention recited in claim 33, capacitors are mounted within the printed circuit board. In this manner, the distance between the IC chip and each capacitor is shortened, and the loop inductance can be lowered. The core substrate is constituted by at least one or more connection layer and an accommodation layer for accommodating the capacitors. Since the capacitors are accommodated within the accommodation layer having large thickness, the thickness of the core substrate does not become large. The thickness of the printed circuit board does not become large even if the interlayer resin insulating layer and the conductor circuit are laminated on the core substrate. Furthermore, since vias to be connected to the capacitors are formed on both sides, the wire length from the capacitors to the IC chip and the external substrate is shortened.

In the invention recited in claim 36, a wiring for connecting an IC chip and an external substrate is provided between capacitors, and a signal line does not pass through the chip capacitors. This structure eliminates the problems that the impedance becomes discontinuous by the high dielectric body to generate a reflection, and that the transmission is delayed by passing through the high dielectric body. By mounting a capacitor for power supply, large electric power can be easily supplied to the IC chip. Furthermore, by providing a capacitor for ground, noise generated when a signal is transmitted in the printed circuit board can be reduced.

In addition, by providing a wiring for connection, it becomes possible to provide a wiring below the capacitors. In this manner, a wiring has an increased degree of freedom, thereby attaining high density and small size.

In the invention recited in claim 37, a chip capacitor in which electrodes are formed along an inside of the outer edge thereof is used. With this arrangement, a large space can be used for external electrodes even if a conduction is established through the via holes, and therefore, the broadened range of alignment is allowed. As a result, a problem of disconnection is eliminated.

In the invention recited in claim 38, a chip capacitor in which electrodes are formed in matrix is used. It becomes easy to accommodate a large chip capacitor in a core substrate. Therefore, it becomes possible to increase an electrostatic capacity, and a problem concerning electricity can be solved. In addition, warpage is hard to generate in the printed circuit board even if the printed circuit board undergoes various thermal histories.

A plurality of chip capacitors from each of which a plurality of pieces are to be obtained may be coupled to each other into one piece unit and used. In this manner, an electrostatic capacity can be properly adjusted and the IC chip can be properly operated.

In the invention recited in claim 39, a capacitor is mounted on the surface of the printed circuit board on top of the capacitors accommodated in the substrate. Since the capacitors are accommodated within the printed circuit board, the distance between the IC chip and each capacitor is shortened. In addition, the loop inductance can be lowered, and electric power can be instantaneously provided. On the other hand, since a capacitor is provided on the surface of the printed circuit board as well, a capacitor having a large capacity can be mounted. In this manner, large electric power can be easily supplied to the IC chip.

In the invention recited in claim 40, the chip capacitor mounted on the surface of the printed circuit board has an electrostatic capacity same or larger than the electrostatic capacity of the chip capacitor incorporated in the printed circuit board. In this manner, there is no shortage of power supply at a high frequency domain, and the IC chip reliably exhibits a desired operation.

In the invention recited in claim 41, the chip capacitor mounted on the surface of the printed circuit board has an inductance same or larger than the inductance of the chip capacitor incorporated in the printed circuit board. In this manner, there is no shortage of power supply at a high frequency domain, and the IC chip reliably exhibits a desired operation.

In the invention recited in claims 42 and 43, an electric connection for electrodes formed with a metal film of the capacitors is established by via holes formed by plating. The electrodes of the chip capacitor are made by metallizing, and have pits and projections on their surfaces. However, the surfaces become smooth by formation of the metal film, and the via holes are then formed on the smooth surfaces. In this manner, when penetrating openings are formed in the resin coating the electrodes, no resin remains, and a reliability of the connection between the via holes and the electrodes can be increased. Furthermore, since the via holes are made by plating into the electrodes formed with the copper plated film, the electrodes are firmly connected to the via holes. No disconnection occurs between the electrodes and via holes even when a heat cycle test is conducted.

The metal film formed on the electrodes of the capacitors preferably includes any one of metals selected from the group consisting of copper, nickel, and noble metals. Tins and zinc are not preferable, because if the capacitors incorporated in the printed circuit board have a film including these metals formed on their electrodes, a migration is easily generated at a connection with the via holes.

The surfaces of the chip capacitors may be roughened. The rough surface contributes to an increased adhesion between the chip capacitor made of ceramic, and a connection layer and a resin insulating layer made of resin, thereby avoiding the resin insulating layer from peeling from the interface with the chip capacitor even when a heat cycle test is conducted.

In the invention recited in claim 44, the chip capacitors are accommodated in the printed circuit board in the state where at least a part of the electrodes of each capacitor is uncoated with a coating layer and exposed to the outside. An electric connection for the electrode exposed from the coating layer is established. The metal exposed from the coating layer preferably includes copper as a main component, because the connection resistance can be lowered.

In the invention recited in claim 45, the thermal expansion coefficient of the insulating adhesive is set to the value lower than the thermal expansion coefficient of the accommodating layer, that is, is set to the value close to that of the chip capacitor made of ceramics. In this manner, even if internal stress is generated between the core substrate and the resin insulating layer, and the chip capacitor caused by the difference in the thermal expansion coefficients therebetween, cracks and peelings do not easily occur when a heat cycle test is conducted. As a result, high reliability can be attained.

A method for manufacturing a printed circuit board according to claim 46 is characterized by comprising at least the following steps (a) to (e):

(a) forming penetrating openings for accommodating a capacitor in a first resin material having a core material impregnated with a resin;

(b) attaching a second resin material to the first resin material formed with the penetrating openings to form an accommodation layer having a section for accommodating a capacitor;

(c) accommodating the capacitor in the accommodation layer;

(d) attaching a third insulating resin layer to the accommodation layer formed in the step (c) to form a core substrate; and

(e) forming openings extending to electrodes of the capacitor in the third insulating resin layer to form via holes.

A method for manufacturing a printed circuit board according to claim 47 is characterized by comprising at least the following steps (a) to (e):

(a) forming penetrating openings for accommodating a capacitor in a first resin material having a core material impregnated with a resin;

(b) providing a capacitor to the second resin material at a position corresponding to a section for accommodating a capacitor in the resin material;

(c) attaching the first resin material subjected to the step (a) and the second resin material subjected to the step (b) to each other to form an accommodation layer accommodating the capacitor;

(d) attaching a third insulating resin layer to the accommodation layer to form a core substrate; and

(e) forming openings in the third insulating resin layer extending to electrodes of the capacitor to form via holes.

A method for manufacturing a printed circuit board according to claim 48 is characterized by comprising at least the following steps (a) to (f):

(a) forming penetrating openings for accommodating a capacitor in a first resin material having a core material impregnated with a resin;

(b) providing a capacitor to the second resin material at a position corresponding to a section for accommodating a capacitor in the resin material;

(c) attaching the first resin material subjected to the step (a) and the second resin material subjected to the step (b) to each other to form an accommodation layer accommodating the capacitor;

(d) attaching a third insulating resin layer to the accommodation layer to form a core substrate;

(e) forming openings in the third insulating resin layer extending to electrodes of the capacitor to form via holes; and

(f) forming a conductive film in the penetrating openings of the first resin material and the openings of the third resin material to form via holes.

In the method for manufacturing a printed circuit board of the invention recited in claims 46 and 47, it becomes possible to accommodate chip capacitors in a core substrate. As a result, a printed circuit board having a lowered loop inductance can be provided.

In the method for manufacturing a printed circuit board of the invention recited in claim 48, it becomes possible to accommodate chip capacitors in a core substrate. As a result, a printed circuit board having a lowered loop inductance can be provided. Since via holes are formed on both surfaces of the core substrate, the wire length from the capacitors to the IC chip and the external substrate is shortened.

In the method for manufacturing a printed circuit board of the invention recited in claim 49, a resin substrate accommodating capacitors and a resin plate are attached to each other by applying a pressure from both sides to form a core substrate. Thus-formed core substrate has a flat surface. As a result, an interlayer resin insulating layer and a conductor circuit having high reliability can be laminated on the core substrate.

A printed circuit board according to claim 50 is characterized by comprising a core substrate, and a resin insulating layer and a conductor circuit laminated to the core substrate,

wherein the core substrate incorporates an accommodating layer having penetrating openings in each of which a capacitor is accommodated, and connection layers each made of an insulating resin layer and provided on the front surface and the back surface of the accommodation layer.

It means the circuit formed by buildup method where an interlayer resin insulating layer is formed on the core substrate, and via holes or through holes are formed in the interlayer resin insulating layer to form a conductor circuit as a conductive layer. As the buildup layer, a semi-additive method or a fully-additive method may be employed.

In the invention recited in claim 50, capacitors are mounted within the printed circuit board. In this manner, the distance between the IC chip and each capacitor is shortened, and the loop inductance can be lowered. The core substrate incorporates at least one or more connection layers and an accommodation layer for accommodating the capacitors. Since the capacitors are accommodated within the accommodation layer having large thickness, the thickness of the core substrate does not become large. The thickness of the printed circuit board does not become large even if the interlayer resin insulating layer and the conductor circuit are laminated on the core substrate.

Since via holes are formed on both surfaces of the core substrate, the power supply located on the substrate connected to the outside and the capacitors accommodated in the substrate can be connected to each other in a shortest distance. With this arrangement, a voltage can be instantaneously supplied from the power supply to the IC chip, and the voltage for driving the IC can be promptly stabilized.

The cavity is preferably filled with a resin. The resin eliminates a space between the capacitors and the core substrate. As a result, the behavior of the capacitors incorporated in the core substrate becomes small. In addition, even if the stress is generated caused by the capacitors, the stress can be alleviated by the resin. The resin also has an effect of adhering the capacitors to the core substrate, and lowering a migration between the capacitors and the core substrate.

In the invention recited in claim 51, an accommodation layer is constituted by a resin substrate having a core material impregnated with a resin. As a result, sufficiently high strength can be given to the core substrate.

In the invention recited in claim 52, the capacitors are fixed in the penetrating openings of the accommodation layer through an insulating adhesive. In this manner, the capacitors can be fixed to proper positions.

In the invention recited in claim 53, the IC chip mounted on the front surface of the printed circuit board, the external substrate mounted on the back surface of the printed circuit board (i.e. daughter board, mother board) are connected to the terminals of the capacitors through the via holes formed in the connection layer. That is, the terminals of the capacitors, the IC chip, and the external substrate are directly connected to each other. As a result, the length of electric wire can be shortened.

In the invention recited in claim 54, a wiring for connecting an IC chip and an external substrate is provided between capacitors, and a signal line does not pass through the chip capacitors. This structure eliminates the problems that the impedance becomes discontinuous by the high dielectric body to generate a reflection, and that the transmission is delayed by passing through the high dielectric body. By mounting a capacitor for power supply, large electric power can be easily supplied to the IC chip. Furthermore, by providing a capacitor for ground, noise generated when a signal is transmitted in the printed circuit board can be reduced. In addition, by providing a wiring for connection, it becomes possible to provide a wiring below the capacitors. In this manner, a wiring has an increased degree of freedom, thereby attaining high density and small size.

In the invention recited in claim 55, a capacitor is mounted on the surface of the printed circuit board on top of the capacitors accommodated in the substrate. Since the capacitors are accommodated within the printed circuit board, the distance between the IC chip and each capacitor is shortened. In addition, the loop inductance can be lowered, and electric power can be instantaneously provided. On the other hand, since a capacitor is provided on the surface of the printed circuit board as well, a capacitor having a large capacity can be mounted. In this manner, large electric power can be easily supplied to the IC chip.

In the invention recited in claim 56, the chip capacitor mounted on the surface of the printed circuit board has an electrostatic capacity same or l