JPH04356998A - Multichip module - Google Patents
Multichip moduleInfo
- Publication number
- JPH04356998A JPH04356998A JP3157738A JP15773891A JPH04356998A JP H04356998 A JPH04356998 A JP H04356998A JP 3157738 A JP3157738 A JP 3157738A JP 15773891 A JP15773891 A JP 15773891A JP H04356998 A JPH04356998 A JP H04356998A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- conductor circuit
- multilayer printed
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 32
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 abstract description 23
- 239000003990 capacitor Substances 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 6
- 239000011810 insulating material Substances 0.000 abstract description 4
- 239000012790 adhesive layer Substances 0.000 abstract description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000004806 packaging method and process Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 4
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229960004643 cupric oxide Drugs 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009421 internal insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、多層プリント配線板に
多数の電子部品を搭載実装したマルチチップモジュール
に関し、特には外部導体回路上の他にその内部導体回路
に電子部品を内蔵接続させたマルチチップモジュールに
関する。[Industrial Application Field] The present invention relates to a multi-chip module in which a large number of electronic components are mounted and mounted on a multilayer printed wiring board, and in particular, the present invention relates to a multi-chip module in which a large number of electronic components are mounted and mounted on a multilayer printed wiring board, and in particular, electronic components are built-in and connected to the internal conductor circuit in addition to the external conductor circuit. Regarding multi-chip modules.
【0002】0002
【従来の技術】従来、両面または多層プリント配線板を
使った高密度実装への取組が種々なされてきている。そ
れは、ハイブリッドテクノロジーの中で電子部品を小型
化し、そしてその電子部品を高密度に実装する技術であ
る。そして、当初はハイブリッドICといった部品レベ
ルに始まり、近年では携帯用オーディオやビデオカメラ
等の電子回路全体にこの高密度実装技術が駆使され、電
子機器の小型化が進められいるのである。2. Description of the Related Art Conventionally, various efforts have been made to achieve high-density packaging using double-sided or multilayer printed wiring boards. It is a hybrid technology that miniaturizes electronic components and mounts them in high density. Initially, this high-density packaging technology started at the level of components such as hybrid ICs, but in recent years, this high-density packaging technology has been used for entire electronic circuits such as portable audio and video cameras, and the miniaturization of electronic devices is progressing.
【0003】一方、高密度実装を行うためのプリント配
線板としては、導体回路の微細化と基板の薄型多層化に
より高密度配線を実現してきた。現在では、0.05m
mまでの微細導体回路と、0.1mm厚さの内層基板と
0.1mm厚さのプリプレグ接着層の組合せによる0.
5mm厚さ4層基板が量産されている。On the other hand, as for printed wiring boards for high-density packaging, high-density wiring has been realized by miniaturizing conductor circuits and making substrates thinner and multilayered. Currently, 0.05m
0.1mm fine conductor circuit, a combination of a 0.1mm thick inner layer substrate and a 0.1mm thick prepreg adhesive layer.
5mm thick 4-layer boards are being mass-produced.
【0004】しかしながら、近年ではさらに高密度実装
を進めることが要求されてきており、プリント配線板表
面のみに電子部品を実装するだけではなく、プリント配
線板の内部導体回路間に主に受動部品を内蔵させること
が要求されたのである。そして、内部導体回路間に印刷
によるカーボン抵抗やニッケルめっき抵抗等の抵抗体入
れることがまず検討され、さらにはコンデンサを内蔵さ
せることが試みられた。しかし、プリント配線板にカー
ボン抵抗を印刷したものは抵抗値変動が大きかったり、
ニッケル抵抗やコンデンサを形成するにはコストが多く
かかったりしたため、量産にはやはり取り入れにくいも
のであった。However, in recent years, there has been a demand for higher-density packaging, and in addition to mounting electronic components only on the surface of printed wiring boards, passive components are mainly mounted between the internal conductor circuits of printed wiring boards. It was requested that it be built-in. At first, consideration was given to inserting a resistor such as a printed carbon resistor or a nickel-plated resistor between internal conductor circuits, and attempts were also made to incorporate a capacitor. However, printed wiring boards with carbon resistors have large resistance fluctuations,
Because it was expensive to form nickel resistors and capacitors, it was difficult to incorporate it into mass production.
【0005】また、近年急速に小型化の進んだチップ部
品を内蔵させる検討も進められた。1005タイプのチ
ップ部品では、0.5mm幅の1.0mm長さで0.3
5mm厚さのチップ抵抗が製造されており、また0.5
mm幅の1.0mm長さで0.5mm厚さのチップセラ
ミックコンデンサも作られている。この小型チップ部品
をプリント配線板の層間に内蔵させるのである。[0005] Further, studies have been made to incorporate chip components, which have been rapidly miniaturized in recent years. For 1005 type chip parts, 0.5 mm width and 1.0 mm length are 0.3
Chip resistors with a thickness of 5 mm are manufactured, and also with a thickness of 0.5 mm.
Chip ceramic capacitors with a width of 1.0 mm, a length of 0.5 mm and a thickness of 0.5 mm are also made. This small chip component is embedded between the layers of the printed wiring board.
【0006】しかしながら、1005タイプのチップ部
品を内蔵させるにせよ、厚さが0.35〜0.5mmと
層間絶縁材であるプリプレグ厚さ0.1mmよりも随分
厚く、多層プリント配線板として積層一体化するために
はプリプレグを複数枚使用し厚くして用いなければなら
なかった。それでもチップ部品周辺の樹脂量が不足して
、層間接着が不十分であったり、ボイドが残ったりし、
また多層プリント配線板全体が厚いものとなり高密度実
装の考え方に逆行することになったのである。However, even if 1005 type chip components are built in, the thickness is 0.35 to 0.5 mm, which is much thicker than the 0.1 mm thickness of prepreg, which is an interlayer insulating material, and it is not necessary to laminate it as a multilayer printed wiring board. In order to achieve this, it was necessary to use multiple sheets of prepreg to make it thicker. Even so, the amount of resin around the chip components may be insufficient, resulting in insufficient interlayer adhesion or voids remaining.
Additionally, the entire multilayer printed wiring board became thicker, which went against the idea of high-density packaging.
【0007】さらに、多層プリント配線板として、内層
基板とプリプレグを積層接着させるためには、内層基板
上の内部導体回路表面を酸化第2銅化する黒化処理やそ
の酸化銅を還元した粗化面としなければならず、また、
この粗化面は高熱に弱く容易に酸化還元されやすいもの
であり、チップ部品や薄型パッケージICを半田づけす
るときの熱の影響をどうするかが大きな問題であったの
である。Furthermore, in order to bond the inner layer substrate and the prepreg together as a multilayer printed wiring board, blackening treatment of converting the surface of the internal conductor circuit on the inner layer substrate into cupric oxide or roughening treatment by reducing the copper oxide is necessary. must be a surface, and
This roughened surface is sensitive to high heat and is easily oxidized and reduced, and a major problem has been how to deal with the effects of heat when soldering chip components and thin packaged ICs.
【0008】[0008]
【発明が解決しようとする課題】本発明は、以上のよう
な問題を解決するためになされたものであり、その解決
しようとする課題は、薄型のチップ部品や薄型パッケー
ジICを内蔵させたときに多層プリント配線板全体の厚
さを極力薄く且つ層間の接着を十分なものとすることで
ある。そして、本発明の目的とするところは、多層プリ
ント配線板の外部導体回路上の他にその内部導体回路に
薄型の電子部品を内蔵接続させることにより、電子部品
の高密度実装化を実現することにある。[Problems to be Solved by the Invention] The present invention has been made to solve the above-mentioned problems, and the problem to be solved is when a thin chip component or a thin package IC is incorporated. Another objective is to make the overall thickness of the multilayer printed wiring board as thin as possible and to ensure sufficient adhesion between the layers. An object of the present invention is to realize high-density packaging of electronic components by connecting thin electronic components not only on the external conductor circuits of a multilayer printed wiring board but also to the internal conductor circuits thereof. It is in.
【0009】[0009]
【課題を解決するための手段】以上の課題を解決するた
めに本発明の採った手段は、実施例に使用する符号を付
して説明すると、「多層プリント配線板10に多数の電
子部品14、15、16を搭載実装したマルチチップモ
ジュール100であって、多層プリント配線板10の外
部導体回路11上に電子部品15を搭載実装するととも
に、多層プリント配線板10の内部絶縁層12間に薄型
の電子部品14、16を載置し且つ内部導体回路13に
電気的に接続させたマルチチップモジュール100にお
いて、内部絶縁層12に薄型の電子部品14、16を収
納するための凹部もしくは開口17を設けるとともに、
凹部もしくは開口17と薄型の電子部品14、16の隙
間を多層プリント配線板10のプリプレグ接着剤により
充填させたことを特徴とするマルチチップモジュール1
00。」である。[Means for Solving the Problems] The means taken by the present invention to solve the above-mentioned problems can be explained using the reference numerals used in the embodiments. , 15 and 16, in which an electronic component 15 is mounted and mounted on an external conductor circuit 11 of a multilayer printed wiring board 10, and a thin chip is mounted between an internal insulating layer 12 of the multilayer printed wiring board 10. In the multi-chip module 100 in which the electronic components 14 and 16 are mounted and electrically connected to the internal conductor circuit 13, a recess or opening 17 is formed in the internal insulating layer 12 to accommodate the thin electronic components 14 and 16. In addition to providing
A multi-chip module 1 characterized in that the gap between a recess or opening 17 and thin electronic components 14 and 16 is filled with a prepreg adhesive of a multilayer printed wiring board 10.
00. ”.
【0010】0010
【作用】以上のような構成のマルチチップモジュール1
00においては、内部絶縁層12に薄型の電子部品14
、16を収納するための凹部もしくは開口17が設けて
あるため、薄型の電子部品14、16の厚さが吸収でき
るようになっているのである。従って、内部絶縁層12
や内部導体回路13は薄型の電子部品14、16を内蔵
させたことによる大きな厚さの膨らみがなくなだらかな
平坦状になっているのである。また、凹部もしくは開口
17と薄型の電子部品14、16の隙間は多層プリント
配線板10のプリプレグ接着剤により充填させるのであ
るため、内部絶縁層12や内部導体回路13の周辺とく
に薄型の電子部品14、16の周辺にはボイド残りは存
在していないのである。そして、薄型の電子部品14、
16の周辺はなだらかな平坦状であるため、プリプレグ
接着剤による充填は樹脂不足とならないのである。[Operation] Multi-chip module 1 configured as above
00, a thin electronic component 14 is provided on the internal insulating layer 12.
, 16 are provided, so that the thickness of the thin electronic components 14, 16 can be absorbed. Therefore, the inner insulating layer 12
The internal conductor circuit 13 has a smooth, flat shape without a large bulge in thickness due to the built-in thin electronic components 14 and 16. Furthermore, since the gap between the recess or opening 17 and the thin electronic components 14 and 16 is filled with the prepreg adhesive of the multilayer printed wiring board 10, the thin electronic components 14 and 16 are particularly close to the inner insulating layer 12 and the internal conductor circuit 13. , 16, there are no remaining voids. And a thin electronic component 14,
Since the area around 16 is gently flat, filling with the prepreg adhesive will not result in resin shortage.
【0011】[0011]
【実施例】次に、本発明を図面に示した各実施例に従っ
て詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained in detail according to embodiments shown in the drawings.
【0012】図1には、本発明のマルチチップモジュー
ル100に係わる1実施例が示してある。多層プリント
配線板10の両面の外部導体回路11上には薄型パッケ
ージIC15が複数搭載実装してある。薄型パッケージ
IC15はこの実施例ではTAB(Tape Aut
omated Bonding)パッケージである。
TABのほかにトランスファーモールドしたTSOP(
Thin Smoll Outline Pac
kage)が高密度薄型実装に適している。そして多層
プリント配線板10の内部絶縁層12間には薄型のチッ
プコンデンサ16が載置され内部導体回路13に電気的
に接続してある。この実施例では、内部絶縁層である内
層基板12に座グリによる凹部17を形成し、そこに表
裏逆向きにしたチップコンデンサ16を載置し、内部導
体回路13に半田づけを行った。そして、0.1mm厚
みのプリプレグ接着層を2枚各々層間絶縁材として積層
プレスして、多層プリント配線板10にチップコンデン
サ16を内蔵したものを得た。ここで得た多層プリント
配線板10にチップコンデンサ16を内蔵したものは、
内部絶縁層12にボイド残りは全くなく、接着強度も充
分であった。また、この後多層プリント配線板10の外
部導体回路11上に電子部品15を搭載接続してマルチ
チップモジュール100を得た。FIG. 1 shows one embodiment of a multi-chip module 100 of the present invention. A plurality of thin package ICs 15 are mounted on external conductor circuits 11 on both sides of the multilayer printed wiring board 10. In this embodiment, the thin package IC 15 is TAB (Tape Out).
It is a bonding package. In addition to TAB, transfer molded TSOP (
Thin Small Outline Pac
cage) is suitable for high-density, thin packaging. A thin chip capacitor 16 is placed between the internal insulating layers 12 of the multilayer printed wiring board 10 and electrically connected to the internal conductor circuit 13. In this example, a recess 17 was formed by counterbore in the inner layer substrate 12, which is an internal insulating layer, and a chip capacitor 16 with the front and back turned upside down was placed therein, and the internal conductor circuit 13 was soldered to the recess 17. Then, two prepreg adhesive layers each having a thickness of 0.1 mm were laminated and pressed as interlayer insulating materials to obtain a multilayer printed wiring board 10 with a built-in chip capacitor 16. The multilayer printed wiring board 10 obtained here with a built-in chip capacitor 16 is
There were no remaining voids in the internal insulating layer 12, and the adhesive strength was sufficient. Further, after this, electronic components 15 were mounted and connected on the external conductor circuit 11 of the multilayer printed wiring board 10 to obtain a multichip module 100.
【0013】また、内部導体回路13の表面処理および
電子部品16の半田づけは、望ましくは次のようにする
とよい。まづ内部導体回路13の表面処理は、電子部品
16との接続端子部(図示しない)はニッケル及び金メ
ッキを行い、次いで黒化処理を行う。ニッケル及び金メ
ッキは接続端子部のみについて行うため、その部分を除
いてメッキレジストでマスクし、ニッケル及び金メッキ
を行うのである。そして、黒化処理を行えば、金メッキ
を行った部分は酸化を受けないので、その部分以外の内
部導体回路13上に黒化処理が施されるのである。The surface treatment of the internal conductor circuit 13 and the soldering of the electronic component 16 are preferably carried out as follows. First, as for the surface treatment of the internal conductor circuit 13, the connection terminal portion (not shown) with the electronic component 16 is plated with nickel and gold, and then blackened. Since nickel and gold plating is applied only to the connection terminals, that area is masked with a plating resist and nickel and gold plating is performed. If the blackening treatment is performed, the gold-plated portion will not be oxidized, so the blackening treatment will be performed on the internal conductor circuit 13 other than that portion.
【0014】次に、電子部品16の半田づけは、前述し
た凹部もしくは開口17に電子部品16を載置し、電子
部品16の外部接続端子(図示しない)の一部と内部導
体回路13の接続端子に半田ペーストを塗布し、半田を
リフロー溶融させて半田づけを行えばよい。ここで、注
意を要するのは黒化処理部分が熱に弱いことであり、黒
化処理部分に高熱をかけないことが重要である。そのた
めに、リフロー溶融ではヒーターブロック、パルスツー
ル、レーザー光等による部分加熱の方法もしくは低融点
半田ペーストを使った低温リフローが望ましい。低融点
半田ペーストとしてはビスマス半田やインジウム半田で
融点が130〜180℃程度のものが望ましい。Next, the electronic component 16 is soldered by placing the electronic component 16 in the recess or opening 17 described above, and connecting a part of the external connection terminal (not shown) of the electronic component 16 to the internal conductor circuit 13. Soldering can be performed by applying solder paste to the terminals and melting the solder by reflow. Here, it is important to note that the blackened part is sensitive to heat, and it is important not to apply high heat to the blackened part. For this reason, in reflow melting, it is desirable to use a heater block, a pulse tool, a method of partial heating using a laser beam, etc., or a low-temperature reflow using a low melting point solder paste. The low melting point solder paste is preferably bismuth solder or indium solder with a melting point of about 130 to 180°C.
【0015】図2には、本発明のマルチチップモジュー
ル100に係わる別の実施例が示してある。図2の実施
例の図1の実施例との違いは、内部絶縁層である内層基
板12に金型による打抜きもしくは切削加工により開口
17を形成し、そこに薄型のパッケージIC14を載置
し内部導体回路13に接続した点である。薄型のパッケ
ージIC14としては前述したTABやTSOPパッケ
ージが望ましい。また、薄型のパッケージIC14の代
わりにベアチップICをフリップチップ実装する転用も
容易である。その場合は、内部絶縁層である内層基板1
2に開口は設けず、内層基板12上にベアチップICを
フリップチップ実装し、その部分の層間絶縁材であるプ
リプレグに開口17を設けた。FIG. 2 shows another embodiment of the multichip module 100 of the present invention. The difference between the embodiment shown in FIG. 2 and the embodiment shown in FIG. This is the point connected to the conductor circuit 13. As the thin package IC 14, the above-mentioned TAB or TSOP package is preferable. Furthermore, it is easy to use flip-chip mounting of a bare chip IC instead of the thin package IC 14. In that case, the inner layer substrate 1 which is an internal insulating layer
No opening was provided in 2, a bare chip IC was flip-chip mounted on the inner layer substrate 12, and an opening 17 was provided in the prepreg which is an interlayer insulating material in that part.
【0016】図3の実施例は、チップコンデンサやチッ
プ抵抗等のチップ部品16と薄型パッケージIC14を
内部絶縁層12間に混在させて内蔵したものであり、詳
細は省略する。In the embodiment shown in FIG. 3, a chip component 16 such as a chip capacitor or a chip resistor and a thin package IC 14 are mixed and built in between the internal insulating layers 12, and the details will be omitted.
【0017】[0017]
【発明の効果】以上詳述した通り、本発明に係わるマル
チチップモジュールにあっては、薄型のチップ部品や薄
型パッケージICを内蔵させたときに多層プリント配線
板全体の厚さを極力薄く且つ層間の接着を充分なものと
することができる。従って、多層プリント配線板の外部
導体回路上の他にその内部導体回路に薄型の電子部品を
内蔵接続させることができ、電子部品の高密度実装化が
実現できるのである。Effects of the Invention As detailed above, in the multi-chip module according to the present invention, when thin chip components or thin package ICs are incorporated, the overall thickness of the multilayer printed wiring board can be made as thin as possible, and the interlayer Adhesion can be made sufficient. Therefore, thin electronic components can be built-in and connected to the internal conductor circuits of the multilayer printed wiring board in addition to the external conductor circuits, and high-density packaging of electronic components can be realized.
【図1】本発明に係わるマルチチップモジュールの1実
施例を示す断面図である。FIG. 1 is a sectional view showing one embodiment of a multi-chip module according to the present invention.
【図2】本発明に係わるマルチチップモジュールの別の
実施例を示す断面図である。FIG. 2 is a sectional view showing another embodiment of a multi-chip module according to the present invention.
【図3】本発明に係わるマルチチップモジュールの更に
別の実施例を示す断面図である。FIG. 3 is a sectional view showing still another embodiment of the multi-chip module according to the present invention.
【図4】従来のマルチチップモジュールを示す断面図で
ある。FIG. 4 is a cross-sectional view showing a conventional multi-chip module.
10 多層プリント配線板 11 外部導体回路 12 内部絶縁層 13 内部導体回路 14 薄型パッケージIC 15 電子部品 16 チップ部品 17 凹部又は開口 100 マルチチップモジュール 10 Multilayer printed wiring board 11 External conductor circuit 12 Internal insulation layer 13 Internal conductor circuit 14 Thin package IC 15 Electronic parts 16 Chip parts 17 Recess or opening 100 Multi-chip module
Claims (1)
を搭載実装したマルチチップモジュールであって、前記
多層プリント配線板の外部導体回路上に電子部品を搭載
実装するとともに、前記多層プリント配線板の内部絶縁
層間に薄型の電子部品を載置し且つ内部導体回路に電気
的に接続させたマルチチップモジュールにおいて、内部
絶縁層に前記薄型の電子部品を収納するための凹部もし
くは開口を設けるとともに、その凹部もしくは開口と前
記薄型の電子部品の隙間を前記多層プリント配線板のプ
リプレグ接着剤により充填させたことを特徴とするマル
チチップモジュール。1. A multi-chip module in which a large number of electronic components are mounted and mounted on a multilayer printed wiring board, wherein the electronic components are mounted and mounted on an external conductor circuit of the multilayer printed wiring board, and the electronic components are mounted and mounted on an external conductor circuit of the multilayer printed wiring board. In a multi-chip module in which a thin electronic component is placed between internal insulating layers and electrically connected to an internal conductor circuit, the internal insulating layer is provided with a recess or opening for accommodating the thin electronic component, and A multi-chip module characterized in that a gap between a recess or opening and the thin electronic component is filled with a prepreg adhesive of the multilayer printed wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3157738A JPH04356998A (en) | 1991-06-01 | 1991-06-01 | Multichip module |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3157738A JPH04356998A (en) | 1991-06-01 | 1991-06-01 | Multichip module |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000388403A Division JP2001217382A (en) | 2000-12-21 | 2000-12-21 | Multi-chip module |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04356998A true JPH04356998A (en) | 1992-12-10 |
Family
ID=15656279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3157738A Pending JPH04356998A (en) | 1991-06-01 | 1991-06-01 | Multichip module |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04356998A (en) |
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US6586827B2 (en) | 2000-12-27 | 2003-07-01 | Ngk Spark Plug Co., Ltd. | Wiring board and method for fabricating the same |
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US6876091B2 (en) | 2000-12-25 | 2005-04-05 | Ngk Spark Plug Co., Ltd. | Wiring board |
US6952049B1 (en) | 1999-03-30 | 2005-10-04 | Ngk Spark Plug Co., Ltd. | Capacitor-built-in type printed wiring substrate, printed wiring substrate, and capacitor |
US7855894B2 (en) | 1999-09-02 | 2010-12-21 | Ibiden Co., Ltd. | Printed circuit board |
US7864542B2 (en) | 1999-09-02 | 2011-01-04 | Ibiden Co., Ltd. | Printed circuit board |
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-
1991
- 1991-06-01 JP JP3157738A patent/JPH04356998A/en active Pending
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