JPH04304693A - Chip package and composite chip package - Google Patents

Chip package and composite chip package

Info

Publication number
JPH04304693A
JPH04304693A JP3068260A JP6826091A JPH04304693A JP H04304693 A JPH04304693 A JP H04304693A JP 3068260 A JP3068260 A JP 3068260A JP 6826091 A JP6826091 A JP 6826091A JP H04304693 A JPH04304693 A JP H04304693A
Authority
JP
Japan
Prior art keywords
chip
terminal
integrated
chip components
flexible substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3068260A
Other languages
Japanese (ja)
Inventor
Katsuhide Tsukamoto
勝秀 塚本
Seiichi Nakatani
誠一 中谷
Hisashi Nakamura
中村 恒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3068260A priority Critical patent/JPH04304693A/en
Publication of JPH04304693A publication Critical patent/JPH04304693A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PURPOSE:To make it possible to connect chip components without strain induced by a thermal cycle by laying out each terminal of a chip component in face- shape and bonding each terminal with a flexible board. CONSTITUTION:There are provide chip components 101, such as an IC, a resistor, a capacitor, and a coil. A sealing resin integrates each chip components 101, and hence forms one piece component 105 having a bump 103 attached to the terminal of each chip component 101. Each terminal of the chip components 101 is integrally laid out in face shape and bonded with a flexible board 106. This construction makes it possible to eliminate thermal strain produced by a thermal cycle and provide a reliable bonding performance and enhance a heat emission performance more satisfactorily if a further attempt is made to integrate the chip components 101, using a good conductor sheet.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はチップ部品を搭載したモ
ジュールに関係する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a module mounted with chip components.

【0002】0002

【従来の技術】最近は、電気回路で達成できる機能が随
分と多くなり、それに伴い電気回路が複雑になり、そこ
に使う電気部品の数がずいぶん増えてきた。そのために
、配線基板は複雑になり、小型化も要求されるようにな
った。このような要求を満たすために、最近マルチチッ
プモジュールと呼ばれる実装方法(パッケージ方法)が
提案されている。このものは、一つの回路基板(通常多
層基板)の上に複数個のチップ(ICやチップ部品)を
搭載し、一つのパッケージ内に納めたものであり、一つ
の機能ブロックを構成する様に設計されるのが一般的で
ある。この機能ブロックの複数個を担体ICチップやチ
ップ部品と共に一枚の回路基板(単層あるいは多層)上
に搭載し、一つのシステムとしている。
BACKGROUND OF THE INVENTION In recent years, the number of functions that can be achieved with electrical circuits has increased significantly, and as a result, electrical circuits have become more complex and the number of electrical components used in them has increased considerably. As a result, wiring boards have become more complex, and miniaturization has also been required. In order to meet such demands, a mounting method (packaging method) called a multi-chip module has recently been proposed. This device has multiple chips (ICs and chip components) mounted on one circuit board (usually a multilayer board) and housed in one package, so that they form one functional block. It is generally designed. A plurality of these functional blocks are mounted on a single circuit board (single layer or multilayer) together with a carrier IC chip and chip components to form a single system.

【0003】小型化や低価格化のために、裸のICチッ
プ(ベアーチップ)をフェイスダウンで搭載することが
多くなってきた。
[0003] In order to reduce the size and cost, bare IC chips (bare chips) are increasingly being mounted face down.

【0004】0004

【発明が解決しようとする課題】しかし、ベアーチップ
をフェイスダウン搭載した実装には熱サイクルの際に受
ける歪みによる接続不良の問題や熱伝導が悪く発熱する
ICなどは搭載できないという問題があった。
[Problems to be Solved by the Invention] However, mounting bare chips face-down has the problem of connection failure due to distortion during thermal cycling, and the inability to mount ICs that generate heat due to poor heat conduction. .

【0005】[0005]

【課題を解決するための手段】本発明においては、上記
問題を解決するために、チップ部品の各端子が面状に並
ぶように配列一体化し、各端子をフレキシブル基板で結
合するようにしている。
[Means for Solving the Problems] In order to solve the above problem, the present invention arranges and integrates the terminals of the chip components so that they are lined up in a plane, and connects the terminals with a flexible substrate. .

【0006】[0006]

【作用】そのために、熱サイクルによる熱歪みがなく信
頼性のよい接続が得られるばかりでなく、チップ部品を
良熱伝導体の板などを用いて一体化すれば放熱特性もよ
くなる。
[Operation] Therefore, not only can a reliable connection be obtained without thermal distortion due to thermal cycles, but also heat dissipation characteristics can be improved if the chip components are integrated using a plate made of a good thermal conductor.

【0007】[0007]

【実施例】以下、本発明のチップ実装体の一実施例につ
いて図面を参照しながら説明する。  (図1)は本発
明のチップ実装体の断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a chip package according to the present invention will be described below with reference to the drawings. (FIG. 1) is a sectional view of a chip mounting body of the present invention.

【0008】(図1)において、101はIC、抵抗、
コンデンサ、コイル等のチップ部品である。102は封
止樹脂であり、各チップ部品101を一体化していて、
一体化部品105を形成している。103は各チップ部
品の端子(ICの入出力パッド等)につけたバンプであ
る。のチップ部本の各端子が面状に並ぶように配列一体
化している。
In (FIG. 1), 101 is an IC, a resistor,
Chip parts such as capacitors and coils. 102 is a sealing resin that integrates each chip component 101;
An integrated component 105 is formed. Reference numeral 103 denotes bumps attached to terminals (IC input/output pads, etc.) of each chip component. The terminals of the chip section are arranged and integrated so that they are lined up in a plane.

【0009】104は半田あるいは導電性接着剤等の電
気的接合材である。106は多層のフレキシブル基板で
あって、導体配線108を絶縁シート107で支えて何
層にも構成し、各端子を結線をしている。各層の導体配
線108は導体を埋めたビアホール109で接続されて
いる。この構成のチップ実装体においては、基板がフレ
キシブルであるため一体化部品との間に熱サイクルによ
る歪みが少なく、信頼性がよい。
Reference numeral 104 represents an electrical bonding material such as solder or conductive adhesive. Reference numeral 106 is a multilayer flexible board, which is constructed of many layers with conductor wiring 108 supported by an insulating sheet 107, and each terminal is connected. The conductor wiring 108 of each layer is connected through a via hole 109 filled with a conductor. In the chip mounted body having this configuration, since the substrate is flexible, there is little distortion due to thermal cycles between the substrate and the integrated components, and the reliability is high.

【0010】この実施例では多層のフレキシブル基板の
片面にのみ一体化部品を搭載したが、両面に搭載可能な
ことは言うまでもない。また、片面搭載であっても、複
数個の一体化部品を搭載することも可能である。また、
フレキシブル基板の一部を接続端子として残して全体を
樹脂などで包むことも可能である。
[0010] In this embodiment, the integrated component was mounted only on one side of the multilayer flexible board, but it goes without saying that it can be mounted on both sides. Further, even if it is mounted on one side, it is also possible to mount a plurality of integrated parts. Also,
It is also possible to leave a part of the flexible substrate as a connection terminal and wrap the entire flexible substrate with resin or the like.

【0011】この実施例ではフレキシブル基板に多層を
用いたが、当然、単層のフレキシブル基板でも本発明の
効果は失わない。また、一体化部品105とフレキシブ
ル基板106との間に補強あるいは保護のために樹脂な
どで埋めることも可能である。
[0011] In this embodiment, a multi-layer flexible substrate is used, but of course, the effects of the present invention are not lost even with a single-layer flexible substrate. Further, it is also possible to fill the space between the integrated component 105 and the flexible substrate 106 with resin or the like for reinforcement or protection.

【0012】この樹脂は柔らかいほうが歪みの発生をお
さえ好ましい。(図2)は本発明の別の実施例である。 この実施例においては、複数個のチップ部品を樹脂中に
埋め込んで一体化し、上下二つの面に各端子を露出させ
、同一面上の各端子を上下二枚のフレキシブル基板で接
合している。(図2)において、205は一体化部品で
あり、チップ部品201、樹脂202、バンプ203か
らなる。206はフレキシブル基板で、絶縁シート20
7と導体配線208とビアホール209からなる。一体
化部品205とフレキシブル多層基板は接合剤204で
電気的に接続する。上下のフレキシブル多層基板は外側
で接続することも可能である。このようなチップ実装体
では、立体的に高密度な実装が実現できる。
[0012] It is preferable that this resin is softer to suppress the occurrence of distortion. (FIG. 2) is another embodiment of the invention. In this embodiment, a plurality of chip components are embedded in resin and integrated, each terminal is exposed on two upper and lower surfaces, and each terminal on the same surface is joined by two upper and lower flexible substrates. In (FIG. 2), 205 is an integrated component, which consists of a chip component 201, a resin 202, and a bump 203. 206 is a flexible substrate, and an insulating sheet 20
7, a conductor wiring 208, and a via hole 209. The integrated component 205 and the flexible multilayer substrate are electrically connected using a bonding agent 204. It is also possible to connect the upper and lower flexible multilayer substrates on the outside. With such a chip mounting body, high-density three-dimensional mounting can be realized.

【0013】(図3)は別の実施例を示す。大部分が(
図1)のものと同じであるがチップ部品101の背面に
金属等の良熱伝導体301を置いてあるところが違う。 パワーチップを実装するのに有効な構成である。この考
えは(図2)の構成のものにも応用できて、チップ部品
201を良熱伝導体の両面に取りつけ、(図2)の構成
を取ればよい。
FIG. 3 shows another embodiment. Most of them (
It is the same as the one in FIG. 1), except that a good heat conductor 301 made of metal or the like is placed on the back side of the chip component 101. This is an effective configuration for mounting a power chip. This idea can also be applied to the configuration shown in FIG. 2, and the chip component 201 can be attached to both sides of a good heat conductor, and the configuration shown in FIG. 2 can be adopted.

【0014】フレキシブル基板には、ポリイミドシート
に銅箔を張りつけエッチングして配線したものが一般的
である。シート材料の異なるものも知られている。その
外に、後述する実施例のように、離型性基板の上に焼結
した導体を樹脂シートに転写したようなフレキシブル基
板もある。
[0014] The flexible substrate is generally made of a polyimide sheet covered with copper foil and etched with wiring. Different sheet materials are also known. In addition, there is also a flexible substrate in which a conductor sintered on a releasable substrate is transferred to a resin sheet, as in the embodiment described later.

【0015】今まで説明したチップ実装体の複数個を結
合し、一体化したような別の複合チップ実装体を作るこ
とができる。(図4)にその構成を示す。(図4)にお
いて401は(図1)や(図3)に説明したようなチッ
プ実装体である。402はチップ実装体401の入出力
端子につけたバンプである。406は担体の個別チップ
部品である。これらの部品を樹脂404で一体化する。 405は配線基板であって、各チップ実装体や個別チッ
プ部品を電気的に結合する。403は半田のような電気
的な接合剤である。
[0015] A plurality of the chip mounts described so far can be combined to form another composite chip mount as if they were integrated. (Figure 4) shows its configuration. In (FIG. 4), 401 is a chip mounting body as described in (FIG. 1) and (FIG. 3). 402 is a bump attached to the input/output terminal of the chip mounting body 401. 406 is an individual chip component of the carrier. These parts are integrated with resin 404. Reference numeral 405 is a wiring board, which electrically connects each chip mounting body and individual chip components. 403 is an electrical bonding agent such as solder.

【0016】(実施例1)パッド間隔200μですべて
短絡させた64パッドをもつテスト用ICにワイヤボン
ドによる金バンプをつけ、更に、ディップにより半田を
つけたものを2つ用意した。2つのICを離型性の平板
の上にフェイスダウンで並べて配置し、上からエポキシ
樹脂を流し、硬化させ、基板から剥がした。このものを
削って直方体に成形した。半田バンプの面は慎重に研磨
し、2つのテスト用ICのすべてのバンプが研磨面に露
出するようにして、一体化部品を作った。サイズはおよ
そ10×10mmであった。
(Example 1) Two test ICs having 64 pads, all of which were short-circuited with a pad spacing of 200 μm, were provided with gold bumps by wire bonding, and further soldered by dipping. Two ICs were placed face down on a releasable flat plate, epoxy resin was poured over the top, cured, and peeled off from the substrate. This was cut and formed into a rectangular parallelepiped. The solder bump surfaces were carefully polished so that all bumps on the two test ICs were exposed to the polished surface, creating an integrated part. The size was approximately 10 x 10 mm.

【0017】次に、表面を平坦にした六方晶窒化硼素の
板(デンカ株式会社製TGグレード)に以下の組成の焼
結性の導体ペースト 材料組成wt% Cu          79.9 CuO          2.55 ガラス粉        2.55 ビヒクル      15.0 合計        100.00wt%を幅300μ
mのストライプ状のラインにスクリーン印刷した。この
導体ぺ−ストの作製方法は、上記の無機組成にエチルセ
ルロ−スをテルピネオ−ルで溶解させたビヒクルを3段
ロ−ルにて混練して得たものである。
Next, a sinterable conductive paste material having the following composition was applied to a flattened hexagonal boron nitride plate (TG grade manufactured by Denka Co., Ltd.) with the following composition: Cu 79.9 CuO 2.55 Glass powder 2.55 Vehicle 15.0 Total 100.00wt% Width 300μ
Screen printing was performed on striped lines of m. This conductor paste was prepared by kneading the above-mentioned inorganic composition with a vehicle in which ethyl cellulose was dissolved in terpineol using a three-stage roll.

【0018】これを120℃−10分間の乾燥の後、窒
素中の雰囲気でメッシュベルト炉で焼成した。その条件
は、900℃−10分間保持で投入から取り出しまで6
0分であった。その結果、焼結導体(焼結銅)のパタ−
ンが基板から剥がれる事が無く精度よく形成できた。焼
結導体のパタ−ン幅は約300μmで幅方向の収縮はほ
とんど無く、焼結導体の厚みは約15μmであった。
After drying this at 120° C. for 10 minutes, it was fired in a mesh belt furnace in a nitrogen atmosphere. The conditions were 900°C for 10 minutes and 6 hours from loading to unloading.
It was 0 minutes. As a result, the pattern of the sintered conductor (sintered copper)
The pattern could be formed with high accuracy without peeling off from the substrate. The pattern width of the sintered conductor was approximately 300 μm, with almost no shrinkage in the width direction, and the thickness of the sintered conductor was approximately 15 μm.

【0019】エポキシ接着剤つきのポリイミドシート(
東レ株式会社製FPC用カバーレイシート  以下、単
にポリイミドシートと呼ぶ)を上記焼結導体の上に重ね
た後、160℃に加熱可圧した。冷却後、ポリイミドシ
ートを剥がし、焼結導体はポリイミドシートに接着し、
フレキシブル基板をえた。
Polyimide sheet with epoxy adhesive (
A coverlay sheet for FPC manufactured by Toray Industries, Inc. (hereinafter simply referred to as polyimide sheet) was layered on the sintered conductor, and then heated and pressurized to 160°C. After cooling, the polyimide sheet is peeled off, and the sintered conductor is glued to the polyimide sheet.
I got a flexible board.

【0020】このフレキシブル基板の必要なところにハ
ンダペーストを印刷し、乾燥後、リフローさせた。
[0020] Solder paste was printed on the necessary parts of this flexible substrate, and after drying, it was reflowed.

【0021】前記の一体化部品のバンプ露出部とフレキ
シブル基板の半田部分とを位置合わせし、圧接加熱して
テスト用チップ実装体をえた。すべての端子は確実に接
続しており、−20℃〜100℃の500回の熱サイク
ルに耐えた。
The exposed bump portion of the integrated component and the solder portion of the flexible substrate were aligned and pressed and heated to obtain a chip mount for testing. All terminals were securely connected and withstood 500 thermal cycles from -20°C to 100°C.

【0022】[0022]

【発明の効果】本発明を用いれば、熱サイクルによる歪
みのないチップ部品の接合が得られ、信頼性がよいばか
りでなく、形状がコンパクト、堅牢で従来にない実装が
えられる。
[Effects of the Invention] By using the present invention, it is possible to bond chip components without distortion due to thermal cycles, which not only has good reliability but also has a compact shape, robustness, and unprecedented mounting.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明のチップ実装体の断面図である。FIG. 1 is a sectional view of a chip package according to the present invention.

【図2】本発明の別のチップ実装体の断面図である。FIG. 2 is a sectional view of another chip mounting body of the present invention.

【図3】本発明の別のチップ実装体の断面図である。FIG. 3 is a sectional view of another chip mounting body of the present invention.

【図4】本発明の複合チップ実装体の断面図である。FIG. 4 is a cross-sectional view of the composite chip package of the present invention.

【符号の説明】[Explanation of symbols]

101、201  チップ部品 102、202、404  樹脂 103、203、402  バンプ 104、204、403  接合剤 105、205  一体化部品 106、206  フレキシブル基板 107、207  絶縁シート 108、208  導体配線 109  ビアホール 405  配線基板 406  個別チップ部品 101, 201 Chip parts 102, 202, 404 Resin 103, 203, 402 Bump 104, 204, 403 Bonding agent 105, 205 Integrated parts 106, 206 Flexible board 107, 207 Insulation sheet 108, 208 Conductor wiring 109 Beer Hall 405 Wiring board 406 Individual chip parts

Claims (12)

【特許請求の範囲】[Claims] 【請求項1】  チップ部品の各端子が面状に並ぶよう
に配列一体化し、各端子をフレキシブル基板で結合した
ことを特徴とするチップ実装体。
1. A chip mounting body characterized in that each terminal of a chip component is arranged and integrated so as to be lined up in a plane, and each terminal is connected by a flexible substrate.
【請求項2】  チップ部品を樹脂中に埋め込んで一体
化し、一つの面に各端子を露出させ、フレキシブル基板
で結合したたことを特徴とする請求項1記載のチップ実
装体。
2. The chip mounting body according to claim 1, wherein the chip components are embedded in a resin and integrated, each terminal is exposed on one surface, and the chip components are bonded by a flexible substrate.
【請求項3】  チップ部品を樹脂中に埋め込んで一体
化し、上下二つの面に各端子を露出させ、同一面上の各
端子を上下二枚のフレキシブル基板で結合したことを特
徴とする請求項1記載のチップ実装体。
[Claim 3] A claim characterized in that the chip components are embedded in resin and integrated, each terminal is exposed on two upper and lower surfaces, and each terminal on the same surface is connected by two upper and lower flexible substrates. The chip-mounted body according to 1.
【請求項4】  チップ部品を良熱伝導板の片面上に配
列して一体化し、フレキシブル基板で結合したたことを
特徴とする請求項1記載のチップ実装体。
4. The chip mounting body according to claim 1, wherein the chip components are arranged and integrated on one side of a good heat conductive plate and are connected by a flexible substrate.
【請求項5】  チップ部品を一枚の良熱伝導板の両面
に配列して一体化し、上下に各端子を配列させ、各端子
を上下二枚のフレキシブル基板で結合したことを特徴と
する請求項1記載のチップ実装体。
[Claim 5] A claim characterized in that chip components are arranged and integrated on both sides of a single good heat conductive plate, respective terminals are arranged above and below, and each terminal is connected by two upper and lower flexible substrates. The chip-mounted body according to item 1.
【請求項6】  フレキシブル基板が樹脂基板上に焼結
導体を接着した構成であることを特徴とする請求項1か
ら5のいずれかに記載のチップ実装体。
6. The chip mounting body according to claim 1, wherein the flexible substrate has a structure in which a sintered conductor is bonded onto a resin substrate.
【請求項7】  チップ部品の各端子が面状に並ぶよう
に配列一体化し、各端子をフレキシブル基板で結合した
チップ実装体を複数個結合一体化したことを特徴とする
複合チップ実装体。
7. A composite chip mount body comprising a plurality of chip mount bodies in which each terminal of a chip component is arranged and integrated so as to be lined up in a plane, and each terminal is connected by a flexible substrate.
【請求項8】  チップ部品を樹脂中に埋め込んで一体
化し、一つの面に各端子を露出させ、フレキシブル基板
で結合したチップ実装体を複数個結合一体化したことを
特徴とする請求項7記載の複合チップ実装体。
8. The device according to claim 7, wherein a plurality of chip components are integrated by embedding them in a resin, each terminal is exposed on one surface, and a plurality of chip mounting bodies are connected by a flexible substrate. composite chip assembly.
【請求項9】  チップ部品を樹脂中に埋め込んで一体
化し、上下二つの面に各端子を露出させ、同一面上の各
端子を上下二枚のフレキシブル基板で結合したチップ実
装体を複数個結合一体化したことを特徴とする請求項7
記載の複合チップ実装体。
9. A plurality of chip mounting bodies are combined by embedding and integrating chip components in resin, exposing each terminal on two upper and lower surfaces, and connecting each terminal on the same surface with two upper and lower flexible substrates. Claim 7 characterized in that they are integrated.
The described composite chip mounting body.
【請求項10】  チップ部品を良熱伝導板の片面上に
配列して一体化し、フレキシブル基板で結合したチップ
実装体を複数個結合一体化したことを特徴とする請求項
7記載の複合チップ実装体。
10. The composite chip mounting according to claim 7, characterized in that the chip components are arranged and integrated on one side of a good thermally conductive plate, and a plurality of chip mounting bodies connected by a flexible substrate are integrated. body.
【請求項11】  チップ部品を一枚の良熱伝導板の両
面に配列して一体化し、上下に各端子を配列させ、各端
子を上下二枚のフレキシブル基板で結合したチップ実装
体を複数個結合一体化したことを特徴とする請求項7記
載の複合チップ実装体。
[Claim 11] A plurality of chip mounting bodies in which chip components are arranged and integrated on both sides of a single good heat conductive plate, each terminal is arranged above and below, and each terminal is connected by two upper and lower flexible substrates. 8. The composite chip package according to claim 7, wherein the composite chip package is integrally bonded.
【請求項12】  フレキシブル基板が樹脂基板上に焼
結導体を接着した構成であることを特徴とする請求項7
から11のいずれかに記載の複合チップ実装体。
12. Claim 7, wherein the flexible substrate has a structure in which a sintered conductor is bonded onto a resin substrate.
12. The composite chip-mounted body according to any one of 11 to 11.
JP3068260A 1991-04-01 1991-04-01 Chip package and composite chip package Pending JPH04304693A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3068260A JPH04304693A (en) 1991-04-01 1991-04-01 Chip package and composite chip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3068260A JPH04304693A (en) 1991-04-01 1991-04-01 Chip package and composite chip package

Publications (1)

Publication Number Publication Date
JPH04304693A true JPH04304693A (en) 1992-10-28

Family

ID=13368609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3068260A Pending JPH04304693A (en) 1991-04-01 1991-04-01 Chip package and composite chip package

Country Status (1)

Country Link
JP (1) JPH04304693A (en)

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* Cited by examiner, † Cited by third party
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JP2004363566A (en) * 2003-05-14 2004-12-24 Matsushita Electric Ind Co Ltd Electronic-component mounting body and method of manufacturing the same
JP2006093679A (en) * 2004-08-24 2006-04-06 Sony Corp Semiconductor package
WO2007072616A1 (en) * 2005-12-22 2007-06-28 Murata Manufacturing Co., Ltd. Module having built-in component and method for fabricating such module
US7613010B2 (en) 2004-02-02 2009-11-03 Panasonic Corporation Stereoscopic electronic circuit device, and relay board and relay frame used therein
CN105764273A (en) * 2016-04-22 2016-07-13 深圳崇达多层线路板有限公司 Manufacturing method of PCB embedded with heat dissipation block
CN106028631A (en) * 2016-07-28 2016-10-12 广东欧珀移动通信有限公司 PCB and mobile terminal with PCB
CN106413244A (en) * 2016-10-25 2017-02-15 广东欧珀移动通信有限公司 Printed-circuit board and mobile terminal
US20190035758A1 (en) * 2017-07-31 2019-01-31 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004363566A (en) * 2003-05-14 2004-12-24 Matsushita Electric Ind Co Ltd Electronic-component mounting body and method of manufacturing the same
JP4503349B2 (en) * 2003-05-14 2010-07-14 パナソニック株式会社 Electronic component mounting body and manufacturing method thereof
US7613010B2 (en) 2004-02-02 2009-11-03 Panasonic Corporation Stereoscopic electronic circuit device, and relay board and relay frame used therein
JP2006093679A (en) * 2004-08-24 2006-04-06 Sony Corp Semiconductor package
JP4626445B2 (en) * 2004-08-24 2011-02-09 ソニー株式会社 Manufacturing method of semiconductor package
WO2007072616A1 (en) * 2005-12-22 2007-06-28 Murata Manufacturing Co., Ltd. Module having built-in component and method for fabricating such module
CN105764273A (en) * 2016-04-22 2016-07-13 深圳崇达多层线路板有限公司 Manufacturing method of PCB embedded with heat dissipation block
CN106028631A (en) * 2016-07-28 2016-10-12 广东欧珀移动通信有限公司 PCB and mobile terminal with PCB
CN106413244A (en) * 2016-10-25 2017-02-15 广东欧珀移动通信有限公司 Printed-circuit board and mobile terminal
US20190035758A1 (en) * 2017-07-31 2019-01-31 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10833041B2 (en) * 2017-07-31 2020-11-10 Samsung Electronics Co., Ltd. Fan-out semiconductor package

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