JP6631212B2 - Mounting structure of multilayer capacitor - Google Patents

Description

  The present invention relates to a multilayer capacitor mounting structure.

  On a wiring board on which an integrated circuit such as an IC is mounted, a decoupling capacitor may be mounted between the power supply and the ground of the integrated circuit in order to suppress a voltage fluctuation during operation of the integrated circuit and to remove noise. is there. When a decoupling capacitor is mounted, it is desirable that the power supply impedance be as low as possible from the viewpoint of suppressing voltage fluctuation.

  By the way, a capacitor has ESL (Equivalent Series Inductance) or ESR (Equivalent Series Resistance) in addition to a capacitance component. Therefore, in the wiring board on which the decoupling capacitor is mounted, anti-resonance occurs between the capacitance of the wiring board and the integrated circuit and the inductance of the decoupling capacitor.

  Due to this anti-resonance, the power supply impedance becomes higher as the frequency becomes higher on the low frequency side and becomes lower as the frequency becomes higher on the high frequency side from the anti-resonance frequency. That is, it exhibits a mountain-shaped characteristic near the antiresonance frequency. In order to reduce the power supply impedance, it is desirable to suppress this anti-resonance. As a method of suppressing the anti-resonance, it is conceivable to increase the ESR of the decoupling capacitor. However, although the impedance at the anti-resonance frequency is kept relatively low by this method, there is a problem that the impedance on the low frequency side becomes higher than the anti-resonance frequency.

  In order to solve this problem, Patent Document 1 discloses a capacitor having an ESL of 1 nH or less and an ESR of 1.5 to 20 Ω and an ESL of 1 nH or less between a power supply and a ground of an integrated circuit mounted on a wiring board. It is disclosed that a capacitor having an ESR of 100 mΩ or less is provided in parallel. The anti-resonance is suppressed by the capacitor having the higher ESR, and the impedance on the low frequency side of the anti-resonance frequency is suppressed by the capacitor having the lower ESR. Thereby, the anti-resonance between the capacitance of the wiring board and the inductance of the capacitor can be suppressed.

JP 2012-164817 A

  However, in practice, apart from the capacitance of the wiring board, anti-resonance between the capacitance of the integrated circuit and the inductance of the capacitor may also occur. The anti-resonance between the capacitance of the integrated circuit and the inductance of the capacitor is affected by the inductance of the wiring existing between the integrated circuit and the capacitor (that is, the inductance of the wiring is added to the inductance of the capacitor). Therefore, the impedance at the anti-resonance frequency increases, and the method disclosed in Patent Document 1 cannot suppress this anti-resonance. As the impedance increases due to the anti-resonance, the voltage fluctuation increases.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a mounting structure of a multilayer capacitor capable of suppressing anti-resonance between the capacitance of an integrated circuit and the inductance of the multilayer capacitor.

  The mounting structure of the multilayer capacitor according to the present invention, a wiring board having a power supply pattern and a ground pattern, an integrated circuit mounted on the wiring board, having a power terminal and a ground terminal, and mounted inside the wiring board, the power supply pattern, A multilayer capacitor electrically connected to a ground pattern, wherein a power terminal of the integrated circuit is electrically connected to the power pattern, and a ground terminal of the integrated circuit is electrically connected to the ground pattern. And a first internal electrode provided on one end surface of a pair of opposed end surfaces of the laminate, in which first internal electrodes and second internal electrodes are alternately stacked with a dielectric layer interposed therebetween. And a second external electrode provided on the other end surface of the pair of end surfaces of the laminate and electrically connected to the second internal electrode. The first external electrode has an end surface along one end surface, a first main surface along one main surface connected to one end of the one end surface, and another main surface connected to the other end of one end surface. A second main surface portion along the other end surface, an end surface portion along the other end surface, a first main surface portion along one main surface connected to one end portion of the other end surface, A second main surface portion along the other main surface connected to the other end portion of the other end surface, and the first main surface portion of the first external electrode is connected via a first via formed inside the wiring board. The second main surface of the first external electrode is electrically connected to the power supply pattern via a second via formed inside the wiring board, and the second main surface of the first external electrode is electrically connected to the power supply pattern. The first main surface portion is electrically connected to the ground pattern via a third via formed inside the wiring board, and the second main surface of the second external electrode. The surface portion is electrically connected to a ground pattern via a fourth via formed inside the wiring board, and between the power supply and the ground of the integrated circuit, the first via, the first main surface portion of the first external electrode, A first path passing through the first main surface and the third via of the second external electrode, and a second path passing through the second via, the second main surface of the first external electrode, the second main surface of the second external electrode, and the fourth via. The two paths are formed in parallel, the first path has a higher equivalent series resistance than the second path, and the second path has a higher equivalent series inductance than the first path.

  According to the mounting structure of the multilayer capacitor according to the present invention, the first path and the second path are formed in parallel between the power supply and the ground of the integrated circuit on the wiring board. The first path passes through the first via, the first main surface of the first external electrode, the first main surface of the second external electrode, and the third via, and has low ESL and high ESR. The second path passes through the second via, the second main surface of the first external electrode, the second main surface of the second external electrode, and the fourth via, and has high ESL and low ESR. With this configuration, even when there is a wiring inductance between the integrated circuit and the multilayer capacitor on the wiring board, the high ESL of the first path reduces the high ESR of the first path and the inductance of the multilayer capacitor. Can be suppressed. As a result, the impedance at the anti-resonance frequency decreases, and voltage fluctuation can be suppressed. As described above, according to the mounting structure of the multilayer capacitor according to the present invention, it is possible to suppress the anti-resonance between the capacitance of the integrated circuit and the inductance of the multilayer capacitor even under the influence of the wiring inductance.

  In the mounting structure of the multilayer capacitor according to the present invention, the first main surface of the first external electrode and / or the first main surface of the second external electrode are connected to the second main surface of the first external electrode and the second main electrode. It is preferable that the electrode is formed of an electrode having a higher resistance value than the two main surfaces. With this configuration, the ESR of the first route can be higher than the ESR of the second route.

  In the mounting structure of the multilayer capacitor according to the present invention, it is preferable that the first via and / or the third via be formed using a material having a higher electrical resistivity than the second via and the fourth via. With this configuration, the ESR of the first route can be higher than the ESR of the second route. This material having a high electric resistivity is preferably conductive carbon or palladium.

  In the multilayer capacitor mounting structure according to the present invention, it is preferable that the total length of the first via and the third via is shorter than the total length of the second via and the fourth via. With this configuration, the ESL of the second path can be higher than the ESL of the first path.

  In the multilayer capacitor mounting structure according to the present invention, it is preferable that the first via and / or the third via have a larger diameter than the second via and the fourth via. With this configuration, the ESL of the second path can be higher than the ESL of the first path.

  In the mounting structure of the multilayer capacitor according to the present invention, it is preferable that the first via and / or the third via include a plurality of vias connected in parallel. With this configuration, the ESL of the second path can be higher than the ESL of the first path. In this configuration, it is preferable that the first via, the second via, the third via, and the fourth via all have substantially the same diameter.

  According to the present invention, it is possible to suppress the anti-resonance between the capacitance of the integrated circuit and the inductance of the multilayer capacitor.

FIG. 2 is a cross-sectional view schematically illustrating a mounting structure of the multilayer capacitor according to the first embodiment. It is a figure showing the external shape of the multilayer capacitor concerning a 1st embodiment, (a) is a top view and (b) is a side view. 3 is an equivalent circuit of a mounting structure of the multilayer capacitor according to the embodiment. It is a sectional view showing typically the mounting structure of the multilayer capacitor concerning a 2nd embodiment. 6 is a table showing an example of inductance and resistance according to the diameter of a via. It is a sectional view showing typically the mounting structure of the multilayer capacitor concerning a 3rd embodiment. It is a sectional view showing typically the mounting structure of the multilayer capacitor concerning a 4th embodiment. 6 is a table showing an example of inductance and resistance according to a material (conductivity) of a via. Inductance and resistance when the diameter of the first path-side via is larger than that of the second path-side via, and the material of the first path-side via has lower conductivity (higher electrical resistivity) than the material of the second path-side via It is a table | surface which shows the example of. When the diameter of the first path-side via is smaller than that of the second path-side via, and the material of the first path-side via has a lower conductivity (higher electrical resistivity) than the material of the second path-side via, the inductance and the resistance of the first path-side via are lower. It is a table showing an example. It is a sectional view showing typically the mounting structure of the multilayer capacitor concerning a 5th embodiment. When the first path-side via and the second path-side via have the same diameter, the first path-side via has lower conductivity than the second path-side via, and the number of parallel vias on the first path-side is changed. It is a table | surface which shows the example of an inductance and a resistance. It is explanatory drawing of an example of the manufacturing method of the via | veer with low electric conductivity (high electric resistivity). 6 is an equivalent circuit involved in anti-resonance in a conventional multilayer capacitor mounting structure. 9 is a frequency characteristic of impedance in a mounting structure of a conventional multilayer capacitor. 9 is a complex plane of admittance in a mounting structure of a conventional multilayer capacitor. 7 is a complex plane of impedance in a conventional multilayer capacitor mounting structure. 5 is an equivalent circuit involved in anti-resonance in the mounting structure of the multilayer capacitor according to the embodiment. 4 is a diagram illustrating a frequency characteristic of impedance in a mounting structure of the multilayer capacitor according to the embodiment. 4 is a complex plane of admittance in the mounting structure of the multilayer capacitor according to the embodiment. 6 is a complex plane of impedance in the mounting structure of the multilayer capacitor according to the embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts have the same reference characters allotted. In each of the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted.

  In the mounting structure of the multilayer capacitor according to the embodiment, a via is provided inside a wiring board so as to be connected between a power supply and a ground of an integrated circuit (for example, an IC) mounted on one surface (for example, an upper surface) of the wiring board. This is a structure in which a multilayer capacitor is mounted using the same. In the following description, the mounting structure of the multilayer capacitor according to the first to fifth embodiments will be described.

(1st Embodiment)
The mounting structure 1 of the multilayer capacitor according to the first embodiment will be described with reference to FIGS. FIG. 1 is a sectional view schematically showing a mounting structure 1 of the multilayer capacitor according to the first embodiment. 2A and 2B are diagrams illustrating an outer shape of the multilayer capacitor 11 according to the first embodiment, where FIG. 2A is a plan view and FIG. 2B is a side view. FIG. 3 is an equivalent circuit of the mounting structure 1 of the multilayer capacitor according to the embodiment. In the cross-sectional views of FIG. 1 and the like, hatching is omitted for the insulating layer for easy viewing.

  The mounting structure 1 includes a wiring board 10, a multilayer capacitor 11, and an IC 12 (corresponding to an integrated circuit described in the claims). The multilayer capacitor 11 is a decoupling capacitor connected between the power supply and the ground of the IC 12.

  The IC 12 is, for example, a BGA (Ball Grid Array) package IC, and is mounted on the wiring board 10 by face-down mounting using ball-shaped electrodes (bumps). The IC 12 has a power terminal 12a and a ground terminal 12b.

  The wiring board 10 is a multilayer wiring board. A multilayer capacitor 11 is mounted inside the wiring board 10. On the upper surface 10a of the wiring board 10, an IC 12 is surface-mounted. The multilayer capacitor 11 is disposed, for example, directly below the IC 12.

  On the upper surface 10a of the wiring board 10, wiring patterns such as a power supply pattern 10c and a ground pattern 10d are formed. In the wiring board 10, an insulating layer 10e, a wiring layer 10f, an insulating layer 10g, a wiring layer 10h, an insulating layer 10i, a wiring layer 10j, an insulating layer 10k, a wiring layer 10l, and an insulating layer 10m are sequentially stacked from above in FIG. ing. Vias such as vias 10s, 10t, 10u, 10v, 10w, and 10x are formed inside the wiring board 10.

  The power supply pattern 10c and the ground pattern 10d are, for example, printed wiring patterns made of copper foil or the like. The power supply pattern 10c is electrically connected to the power supply pattern 10o of the wiring layer 10h by the via 10s. The power supply terminal 10a of the IC 12 is electrically connected to the power supply pattern 10c. The ground pattern 10d is electrically connected to the ground pattern 10n of the wiring layer 10f by the via 10t. A ground terminal 12b of the IC 12 is electrically connected to the ground pattern 10d.

  Each of the insulating layers 10e, 10g, 10i, 10k, and 10m is, for example, a rectangular thin plate formed of an insulating resin, ceramics, or the like. The multilayer capacitor 11 is disposed on the insulating layer 10i. Wiring patterns made of, for example, copper foil are formed on the wiring layers 10f, 10h, 10j, and 10l. In particular, a ground pattern (for example, ground plane) 10n is formed in the wiring layer (for example, ground layer) 10f. A power supply pattern (for example, power supply plane) 10o is formed in the wiring layer (for example, power supply layer) 10h. Wiring patterns 10p and 10q are formed in the wiring layer 10j.

  The vias 10s, 10t, 10u, 10v, 10w, and 10x are interlayer through vias formed so as to penetrate an insulating layer or the like in the thickness direction of the wiring board 10. The vias 10s, 10t, 10u, 10v, 10w, and 10x are, for example, through-hole vias in which the wall surfaces of the through holes are plated with a conductor such as copper. The vias 10s, 10t, 10u, 10v, 10w, 10x all have the same diameter, for example, 30 μm.

  The via 10s is a via penetrating through the insulating layer 10e, the insulating layer 10g, and a part of the insulating layer 10i. Via 10s electrically connects one power supply terminal (first main surface portion 11j of first external electrode 11b described later) of multilayer capacitor 11 arranged in insulating layer 10i and power supply pattern 10c formed on upper surface 10a. These are vias to be connected. It is preferable that the via 10 s is disposed immediately below the power supply terminal 12 a of the IC 12. The via 10s is electrically connected to the power supply pattern 10o formed on the upper surface of the insulating layer 10i.

  The via 10t is a via that penetrates a part of the insulating layer 10e, the insulating layer 10g, and the insulating layer 10i. The via 10t electrically connects one ground terminal (the first main surface 11m of the second external electrode 11c described later) of the multilayer capacitor 11 disposed in the insulating layer 10i and the ground pattern 10d formed on the upper surface 10a. These are vias to be connected. It is preferable that the via 10t is disposed directly below the ground terminal 12b of the IC 12. The via 10t is electrically connected to a ground pattern 10n formed on the upper surface of the insulating layer 10g.

  The via 10u is a via penetrating a part of the insulating layer 10i. The via 10u connects the other power supply terminal (the second main surface portion 11k of the first external electrode 11b described later) of the multilayer capacitor 11 disposed in the insulating layer 10i and the wiring pattern 10p formed on the lower surface of the insulating layer 10i. These are vias that are electrically connected.

  The via 10v is a via penetrating the insulating layer 10i. The via 10v is a via that electrically connects the wiring pattern 10p formed on the lower surface of the insulating layer 10i and the power supply pattern 10o formed on the upper surface of the insulating layer 10i. Therefore, the via 10v is electrically connected to the via 10u via the wiring pattern 10p. The via 10v is electrically connected to the via 10s via the power supply pattern 10o.

  The via 10w is a via penetrating a part of the insulating layer 10i. The via 10w connects the other ground terminal (the second main surface 11n of the second external electrode 11c described later) of the multilayer capacitor 11 disposed in the insulating layer 10i and the wiring pattern 10q formed on the lower surface of the insulating layer 10i. These are vias that are electrically connected.

  The via 10x is a via penetrating the insulating layer 10i and the insulating layer 10g. The via 10x is a via that electrically connects the wiring pattern 10q formed on the lower surface of the insulating layer 10i and the ground pattern 10n formed on the upper surface of the insulating layer 10g. Therefore, the via 10x is electrically connected to the via 10w via the wiring pattern 10q. The via 10x is electrically connected to the via 10t via the ground pattern 10n.

  The multilayer capacitor 11 is a decoupling capacitor as described above, and has a function of suppressing voltage fluctuation of the power supply during the operation of the IC 12 and a noise (for example, a noise between the power supply and the ground, a noise generated by the operation of the IC 12). It has a function of removing. Further, the multilayer capacitor 11 has a function of suppressing anti-resonance with the IC 12.

  The multilayer capacitor 11 is a chip-type multilayer ceramic capacitor and has a substantially rectangular parallelepiped shape. The multilayer capacitor 11 includes a multilayer body 11a, a first external electrode 11b, and a second external electrode 11c. The multilayer capacitor 11 is a two-terminal capacitor including the multilayer body 11a, a first external electrode 11b serving as a power terminal, and a second external electrode 11c serving as a ground terminal.

  The first external electrode 11b is provided on one end face 11e of a pair of opposed end faces 11e and 11f of the stacked body 11a, and a part of the upper main face 11g and an end face 11e connected to the upper end of the end face 11e. Is provided up to a part of the lower main surface 11h connected to the lower end of the main surface. A portion along the end face 11e of the first external electrode 11b is referred to as an end face part 11i. A portion along the upper main surface 11g of the first external electrode 11b is referred to as a first main surface portion 11j. A portion along the lower main surface 11h of the first external electrode 11b is referred to as a second main surface portion 11k. The first external electrode 11b is provided up to a part of the opposing side surface that is connected to the end surface 11e and the main surfaces 11g and 11h.

  The second external electrode 11c is provided on the other end face 11f of the pair of opposed end faces 11e and 11f of the multilayer body 11a, and a part of the upper main surface 11g and the end face 11f connected to the upper end of the end face 11f. Is provided up to a part of the lower main surface 11h connected to the lower end of the main surface. A portion along the end face 11f of the second external electrode 11c is referred to as an end face part 111. A portion along the upper main surface 11g of the second external electrode 11c is referred to as a first main surface portion 11m. A portion along the lower main surface 11h of the second external electrode 11c is referred to as a second main surface portion 11n. The second external electrode 11c is provided up to a part of the opposing side surface connected to the end surface 11f and the main surfaces 11g and 11h.

  The laminated body 11a has a plurality of dielectric layers 11p, a plurality of first internal electrodes 11q, and a plurality of second internal electrodes 11r. The first internal electrode 11q and the second internal electrodes 11r sandwich the dielectric layer 11p. Are alternately stacked. The laminate 11a has a rectangular parallelepiped shape.

The dielectric layer 11p is formed in a rectangular film shape. The dielectric layer 11p is made of, for example, a dielectric ceramic mainly containing BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO _{3 and the} like. In addition, an auxiliary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, and a Ni compound may be added to these main components.

  The first and second internal electrodes 11q and 11r are formed in a thin film shape. The first and second internal electrodes 11q and 11r are made of, for example, Ni, Cu, Ag, Pd, an Ag-Pd alloy, Au, or the like. The first internal electrodes 11q and the second internal electrodes 11r are alternately stacked so as to face each other via the dielectric layer 11p. The first internal electrode 11q is electrically connected to the end face 11i of the first external electrode 11b. The second internal electrode 11r is electrically connected to the end surface 11l of the second external electrode 11c.

  The end face 11i of the first external electrode 11b is electrically connected to the plurality of first internal electrodes 11q. The first main surface 11j of the first external electrode 11b is electrically connected to the via 10s. The second main surface 11k of the first external electrode 11b is electrically connected to the via 10u. The first external electrode 11b is a terminal for a power supply (for a signal), and has two connection portions of the first main surface portion 11j and the second main surface portion 11k. The first and second main surface portions 11j and 11k have a width sufficient to arrange the vias 10s and 10u.

  The end face 11l of the second external electrode 11c is electrically connected to the plurality of second internal electrodes 11r. The first main surface 11m of the second external electrode 11c is electrically connected to the via 10t. The second main surface 11n of the second external electrode 11c is electrically connected to the via 10w. The second external electrode 11c is a terminal for ground, and has two connecting portions of the first main surface 11m and the second main surface 11n. The first and second main surface portions 11m and 11n have a width sufficient to arrange the vias 10t and 10w.

  The end surfaces 11i and 11l and the second main surfaces 11k and 11n of the first and second external electrodes 11b and 11c are formed of, for example, a metal electrode (for example, a Cu electrode). In addition, the first main surface portions 11j and 11m of the first and second external electrodes 11b and 11c are formed of, for example, resin electrodes so as to have higher resistance than the second main surface portions 11k and 11n. The resin electrode is conductive and has a higher resistance value than the metal electrode. Since the resin electrode is a well-known electrode, a detailed description is omitted.

  The first main surface portions 11j and 11m on the upper side of the first and second external electrodes 11b and 11c have a higher resistance value (ESR) than the second main surface portions 11k and 11n on the lower side. The ESR of the multilayer capacitor 11 on the first main surface portions 11j and 11m side can be adjusted by the resin electrodes used for the first main surface portions 11i and 11m.

  An example of the dimensions of each part of the multilayer capacitor 11 is shown. Here, the direction connecting the opposed end surface 11e and the end surface 11f is defined as the width direction, the direction connecting the opposed main surface 11g and the main surface 1h is defined as the thickness direction, and the directions other than the end surfaces 11e and 11f and the main surfaces 11g and 11h are defined. The direction connecting the opposing side surfaces is the longitudinal direction. As shown in FIG. 2, the external dimensions of the multilayer capacitor 11 are such that the dimension L in the longitudinal direction is 1.0 mm, the dimension W in the width direction is 0.6 mm, and the dimension T in the thickness direction is 0.22 mm. . The minimum value of the dimension e in the width direction of the first and second external electrodes 11b and 11c (the first main surface portions 11j and 11m and the second main surface portions 11k and 11n) is 0.2 mm. The dimension g between the first external electrode 11b (first main surface 11j, second main surface k) and the second external electrode 11c (first main surface 11m, second main surface 11n) is W-2 × e. It is. The thickness t of the first and second external electrodes 11b and 11c is 10 μm. The internal structure of the multilayer capacitor 1 has a dielectric thickness of 1 μm, an outer layer thickness of 20 μm, a thickness of the internal electrodes 11q and 11r of 0.5 μm, and a gap in the longitudinal and width directions of 50 μm.

  In the mounting structure 1, the first main surface portion 11j of the first external electrode 11b of the multilayer capacitor 11 is connected to the power supply pattern 10c to which the power supply terminal 12a of the IC 12 is connected by a via 10s, and the ground to which the ground terminal 12b of the IC 12 is connected. The first main surface 11m of the second external electrode 11c of the multilayer capacitor 11 is connected to the pattern 10d by a via 10t. In the mounting structure 1, the second main surface 11k of the first external electrode 11b of the multilayer capacitor 11 is connected to the power supply pattern 10c to which the power supply terminal 12a of the IC 12 is connected by the vias 10u, 10v, and a part of the via 10s (the insulating layer). 10e, 10g), and the second main surface 11n of the second external electrode 11c of the multilayer capacitor 11 is connected to the ground pattern 10d to which the ground terminal 12b of the IC 12 is connected by the vias 10w, 10x, and 10t. They are connected by a part (a part penetrating the insulating layer 10e).

  With this configuration, in the mounting structure 1, the via 10s, the first main surface 11j of the first external electrode 11b, the stacked body 11a, and the first main surface of the second external electrode 11c are provided between the power supply and the ground of the IC 12. 11m, a first path A1 passing through the via 10t, a portion of the via 10s, a second main surface 11k of the via 10v, the via 10u, the second main surface 11k of the first external electrode 11b, a second main surface of the stacked body 11a, and the second main surface of the second external electrode 11c 11n, a via 10w, a via 10x, and a second path A2 passing through a part of the via 10t are formed in parallel. In the first embodiment, the via 10s corresponds to the first via described in the claims, and the vias 10u, 10v, and a part of the vias 10s correspond to the second via described in the claims. , Via 10t corresponds to a third via described in the claims, and a part of via 10w, via 10x and via 10t corresponds to a fourth via described in the claims.

  The length of the via (a portion of the via 10u, the via 10v and the via 10s, a portion of the via 10w, the via 10x and the via 10t) on the second path A2 side (that is, the second main surface 11k of the first external electrode 11b). (The length of the via connected in series between the power supply pattern 10c and the second main surface 11n of the second external electrode 11c and the length of the via connected in series between the ground pattern 10d) The length of the via (vias 10s, 10t) on the one path A1 side (that is, the length of the via between the first main surface portion 11j of the first external electrode 11b and the power supply pattern 10c, the first length of the second external electrode 11c) (The length of the via between the main surface 11m and the ground pattern 10d). The length of the via on the first path A1 side and the length of the via on the second path A2 side depend on the thickness of the insulating layers 10e, 10g, 10k, 10i, and 10m. For example, when the thickness of the insulating layers 10e, 10g, 10k, and 10m is 50 μm and the thickness of the insulating layer 10i is 300 μm, the length of the via on the first path A1 side is approximately 100 μm, and the length of the via on the second path A2 side is approximately 100 μm. The length of the via is approximately 400 μm.

  As described above, by changing the length of the via, the inductance (ESL) at the via can be adjusted. If the length of the via is long, the inductance at the via increases. Therefore, in the mounting structure 1, the length of the via on the second path A2 side is longer than the length of the via on the first path A1 side, and the difference in the length of the via causes the second path A2 to be longer than the first path A1. Also, the inductance (ESL) increases.

  FIG. 3 shows an equivalent circuit of the mounting structure 1 showing the first path A1 and the second path A2. The impedance of the first path A1 includes the inductance L11 and the resistance R11 of the first external electrode 11b on the first main surface 11j side, the capacitance C, and the inductance L12 and the resistance R12 of the second external electrode 11c on the first main surface 11m side. Consists of On the other hand, the impedance of the second path A2 includes the inductance L21 and the resistance R21 of the first external electrode 11b on the second main surface 11k side, the capacitance C, and the inductance L22 and the inductance L22 of the second external electrode 11c on the second main surface 11n side. And a resistor R22. The inductance L11 and the resistance R11 of the first path A1 and the inductance L21 and the resistance R21 of the second path A2 are in parallel. Further, the inductance L12 and the resistance R12 of the first path A1 and the inductance L22 and the resistance R22 of the second path A2 are in parallel. The capacitance C is common to the first path A1 and the second path A2.

  Since the first path A1 passes through the first main surface portions 11j and 11m of the first and second external electrodes 11b and 11c formed of a resin electrode having a higher resistance value than the metal electrode, the resistance is higher than that of the second path A2. High (R11> R21, R12> R22). Thus, the first route A1 has a higher ESR than the second route A2. On the other hand, the second path A2 passes through a via (a via 10u, a part of the via 10v and a part of the via 10s, a via 10w, a part of the via 10x and a part of the via 10t) longer than the via (10s, 10t) of the first path A1. Therefore, the inductance is higher than the first path A1 (L21> L11, L22> L12). Thus, the second route A2 has a higher ESL than the first route A1.

  Although the example of the length of the via on the first path A1 side and the length of the via on the second path A2 side has been described above, the length of the via on the first path A1 side and the via length on the second path A2 side are described above. May be appropriately adjusted according to the size of the ESL of the first route A1 and the ESL of the second route A2.

  As described above, the multilayer capacitor 11 is mounted between the power supply and the ground of the IC 12 of the wiring board 10 by using the vias 10s, 10t, 10u, 10v, 10w, and 10x, so that the first path A1 is provided between the power supply and the ground of the IC 12. And the second path A2 are inserted in parallel. Since the IC 12 has a capacitance, anti-resonance occurs between the capacitance of the IC 12 and the inductance of the multilayer capacitor 11. However, since the first path A1 has a high ESR, anti-resonance can be suppressed by the high ESR of the first path A1. Further, since the second path A2 has a low ESR, the impedance on the low frequency side of the anti-resonance frequency can be suppressed by the low ESR of the second path A2.

  However, wiring other than vias 10s, 10t, 10u, 10v, 10w, and 10x (for example, a part of power supply pattern 10o, a part of ground pattern 10n, and a wiring pattern 10p, between the multilayer capacitor 11 and the IC 12). 10q) is present. This wiring also has inductance. If the inductance of the wiring is added to the inductance of the multilayer capacitor 11 (if affected by the inductance of the wiring), the high ESR of the first path A1 described above cannot contribute to the suppression of the anti-resonance, so that The impedance will be high.

  Therefore, the second path A2 is made high in ESL. Due to the high ESL of the second path A2, the high ESR of the first path A1 can contribute to the suppression of anti-resonance even if wiring inductance exists between the multilayer capacitor 11 and the IC 12. As a result, anti-resonance with the capacitance of the IC 12 can be suppressed, and impedance at the anti-resonance frequency decreases. As a result, voltage fluctuation is suppressed, and stable power can be supplied to the IC 12.

  In the mounting structure 1 of the multilayer capacitor according to the first embodiment, the multilayer capacitor 11 is mounted in parallel between the power supply and the ground of the IC 12 on the wiring board 10 by using vias 10s, 10t, 10u, 10v, 10w, and 10x. Thus, the first path A1 and the second path A2 are formed in parallel. Since the first path A1 has a low ESL and a high ESR and the second path A2 has a high ESL and a low ESR, even if there is a wiring inductance between the IC 12 and the multilayer capacitor 11 on the wiring board 10, By increasing the ESL of the second path A2 having a low ESR, the high ESR of the first path A1 can contribute to suppression of anti-resonance between the capacitance of the IC 12 and the inductance of the multilayer capacitor 11. As a result, the impedance at the anti-resonance frequency is reduced, so that the power supply impedance is reduced and voltage fluctuation can be suppressed. As described above, according to the mounting structure 1 of the multilayer capacitor according to the first embodiment, the anti-resonance between the capacitance of the IC 12 and the inductance of the multilayer capacitor 11 can be suppressed even under the influence of the wiring inductance.

  According to the mounting structure 1 of the multilayer capacitor according to the first embodiment, the first main surface portions 11j and 11m on the first path A1 side of the multilayer capacitor 11 are formed of the resin electrodes. The ESR of the first path A1 can be adjusted, and the ESR of the first path A1 can be higher than the ESR of the second path A2.

  Further, according to the multilayer capacitor mounting structure 1 according to the first embodiment, the length of the via on the second path A2 side is made longer than the length of the via on the first path A1 side, so that the first path A1 The ESL of the second path A2 can be adjusted, and the ESL of the second path A2 can be higher than the ESL of the first path A1.

(2nd Embodiment)
The mounting structure 2 of the multilayer capacitor according to the second embodiment will be described with reference to FIGS. FIG. 4 is a sectional view schematically showing a mounting structure 2 of the multilayer capacitor according to the second embodiment. FIG. 5 is a table showing examples of inductance and resistance according to the diameter of the via.

  The mounting structure 2 is different from the mounting structure 1 according to the first embodiment in that the ESL is adjusted even with the diameter of the via. In the mounting structure 2, the ESR is adjusted by the external electrodes of the multilayer capacitor 21 as in the first embodiment.

  The mounting structure 2 includes a wiring board 20, a multilayer capacitor 21, and an IC 22 (corresponding to an integrated circuit described in the claims). The multilayer capacitor 21 is a decoupling capacitor connected between the power supply and the ground of the IC 22.

  The wiring board 20 is a multilayer wiring board. Similarly to the wiring board 10 according to the first embodiment, the wiring board 20 has a multilayer capacitor 21 mounted inside and an IC 22 mounted on the upper surface 20a. Similarly to the wiring board 10, the wiring board 20 has a wiring pattern such as a power supply pattern 20c and a ground pattern 20d formed on an upper surface 20a, and includes an insulating layer 20e, a wiring layer 20f, an insulating layer 20g, a wiring layer 20h, and an insulating layer. 20i, a wiring layer 20j, an insulating layer 20k, a wiring layer 201, and an insulating layer 20m are sequentially stacked. Vias such as vias 20s, 20t, 20u, 20v, 20w, and 20x are formed inside the wiring board 20.

  The power supply pattern 20c is electrically connected to the power supply pattern 20o of the wiring layer 20f via 20s, and the power supply terminal 22a of the IC 22 is electrically connected. The ground pattern 20d is electrically connected to the ground pattern 20n of the wiring layer 20f by the via 20t, and is also electrically connected to the ground terminal 22b of the IC 22.

  The multilayer capacitor 21 is disposed on the insulating layer 20i. Wiring patterns are respectively formed on the wiring layers 20f, 20h, 20j, and 201. In particular, a ground pattern 20n and a power supply pattern 20o are formed on the wiring layer 20f, and the wiring patterns 20p, 20q are formed on the wiring layer 20j. Is formed.

  The vias 20s, 20t, 20u, 20v, 20w, and 20x are different from the vias 10s, 10t, 10u, 10v, 10w, and 10x according to the first embodiment in that only the vias 20s and 20v are connected to the vias 10s and 10v. Are different. Like the via 10s, the via 20s penetrates the insulating layer 20e, the insulating layer 20g, and a part of the insulating layer 20i. The via 20s has one power terminal of the multilayer capacitor 21 and the power pattern 20c formed on the upper surface 20a. Are electrically connected to each other. In particular, the via 20s is electrically connected to the power supply pattern 20o formed on the upper surface of the insulating layer 20g. The via 20v is a via penetrating the insulating layer 20g and the insulating layer 10i. The via 20v is a via that electrically connects the wiring pattern 20p formed on the lower surface of the insulating layer 20i and the power supply pattern 20o formed on the upper surface of the insulating layer 20g. Therefore, the via 20v is electrically connected to the via 20u via the wiring pattern 20p. The via 20v is electrically connected to the via 20s via the power supply pattern 20o.

  The vias 20s, 20t, 20u, 20v, 20w, and 20x have different diameters of some vias as compared with the vias 10s, 10t, 10u, 10v, 10w, and 10x according to the first embodiment. The vias 20s, 20t and the vias 20u, 20v, 20w, 20x have different diameters, and the vias 20s, 20t have a larger diameter. The vias 20s and 20t are, for example, 50 μm. The vias 20u, 20v, 20w, 20x are, for example, 30 μm.

  The multilayer capacitor 21 is a decoupling capacitor as described above. The multilayer capacitor 21 is a chip-type multilayer ceramic capacitor and has a substantially rectangular parallelepiped shape. The multilayer capacitor 21 is a multilayer capacitor similar to the multilayer capacitor 11 according to the first embodiment, and includes a multilayer body 21a, a first external electrode 21b, and a second external electrode 21c. Similarly to the first external electrode 11b according to the first embodiment, the first external electrode 21b includes an end surface 21i along one end surface 21e of the multilayer body 21a, and a first main surface 21j along an upper main surface 21g. , And a second main surface portion 21k along the lower main surface 21h. Similarly to the second external electrode 11c according to the first embodiment, the second external electrode 21c has an end surface portion 211 along the other end surface 21f of the multilayer body 21a and a first main surface portion 21m along the upper main surface 21g. , And a second main surface portion 21n along the lower main surface 21h. Note that the first and second external electrodes 21b and 21c are provided up to a part of opposing side surfaces connected to the end surfaces 21e and 21f and the main surfaces 21g and 21h.

  The multilayer body 21a has the same configuration as the multilayer body 11a of the multilayer capacitor 11 according to the first embodiment, and includes a plurality of dielectric layers 21p, a plurality of first internal electrodes 21q, and a plurality of second internal electrodes 21r. I have. The first external electrode 21b has the same configuration as the first external electrode 11b of the multilayer capacitor 11 according to the first embodiment. Therefore, the first main surface portion 21j of the first external electrode 21b is formed of a resin electrode having a higher resistance than the metal electrode. The second external electrode 21c has the same configuration as the second external electrode 11c of the multilayer capacitor 11 according to the first embodiment. Therefore, the first main surface 21m of the second external electrode 21c is formed of a resin electrode having a higher resistance than the metal electrode.

  In the mounting structure 2, the first main surface 21j of the first external electrode 21b of the multilayer capacitor 21 is connected to the power supply pattern 20c to which the power supply terminal 22a of the IC 22 is connected by the via 20s, and the ground to which the ground terminal 22b of the IC 22 is connected. The first main surface 21m of the second external electrode 21c of the multilayer capacitor 21 is connected to the pattern 20d by the via 20t. In the mounting structure 2, the second main surface portion 21k of the first external electrode 21b of the multilayer capacitor 21 is connected to the power supply pattern 20c to which the power supply terminal 22a of the IC 22 is connected by the via 20u, the via 20v, and a part of the via 20s (the insulating layer). 20e) and the ground pattern 20d to which the ground terminal 22b of the IC 22 is connected, the second main surface 21n of the second external electrode 21c of the multilayer capacitor 21 is part of the via 20w, the via 20x, and the via 20t. (The portion penetrating the insulating layer 20e).

  With this configuration, in the mounting structure 2, similarly to the mounting structure 1 according to the first embodiment, the via 20s, the first main surface portion 21j of the first external electrode 21b, and the stacked structure are provided between the power supply and the ground of the IC 22. The body 21a, the first path A1 passing through the first main surface 21m of the second external electrode 21c and the via 20t, a part of the via 20s, the via 20v, the via 20u, the second main surface 21k of the first external electrode 21b, and the stack The body 21a, the second main surface 21n of the second external electrode 21c, the via 20w, the via 20x, and the second path A2 passing through a part of the via 20t are formed in parallel. In the second embodiment, the via 20s corresponds to the first via described in the claims, and the vias 20u, 20v, and a part of the vias 20s correspond to the second via described in the claims. , Via 20t corresponds to a third via described in the claims, and a part of via 20w, via 20x and via 20t corresponds to a fourth via described in the claims.

  The length of the via on the second path A2 side is longer than the length of the via on the first path A1 side, similarly to the mounting structure 1 according to the first embodiment. As described above, also in the mounting structure 2, the length of the via on the second path A2 side is longer than the length of the via on the first path A1 side. The inductance (ESL) is higher than A1.

  Further, in the mounting structure 2, the diameters of the vias 20s and 20t serving as vias on the first path A1 side are larger than the diameters of the vias 20u, 20v, 20w and 20x serving as vias on the second path A2 side. As described above, by changing the diameter of the via (cross-sectional area of the via), the inductance (ESL) of the via can be adjusted. Specifically, when the diameter of the via is small (when the cross-sectional area of the via is small), the inductance at the via increases. The via on the second path A2 side includes a part of the vias 20s and 20t having a large diameter, whereas the via on the first path A1 side includes all the vias 20s and 20t having the large diameter. In addition, most of the vias on the second path A2 side are constituted by vias 20u, 20v, 20w, and 20x having small diameters. Therefore, since the diameter of the via on the second path A2 side is smaller than the diameter of the via on the first path A1 side, the inductance (ESL) of the second path A2 is higher than that of the first path A1 even if the diameter of the via is different. .

  FIG. 5 shows an example of the inductance and the resistance according to the diameter of the via. In this example, the via is a through-hole via plated with copper. The conductivity (= 1 / electrical resistivity) of copper is 58000000 S / m. The length of the via was 40 μm. The thickness of the copper plating was 10 μm. The diameters of the vias to be compared were 30 μm, 50 μm, and 100 μm. Thus, for a 30 μm via, the outer diameter is 30 μm and the inner diameter is 20 μm. For a 50 μm via, the outer diameter is 50 μm and the inner diameter is 40 μm. For a 100 μm via, the outer diameter is 100 μm and the inner diameter is 90 μm. Using these numerical values, the inductance and resistance of the via of each diameter were calculated. The inductance was calculated at 100 MHz.

  For a 30 μm via, the inductance was 10 pH and the resistance was 0.4390 mΩ. For a 50 μm via, the inductance was 7.3 pH and the resistance was 0.2439 mΩ. For a 100 μm via, the inductance was 6 pH and the resistance was 0.1155 mΩ. As can be seen from this example, the smaller the diameter of the via, the higher the inductance at the via (the larger the diameter of the via, the lower the inductance at the via).

  The equivalent circuit of the mounting structure 2 in which the first path A1 and the second path A2 are formed is also the one shown in FIG. 3, as in the first embodiment. The first path A1 passes through the first main surface portions 21j and 21m of the first and second external electrodes 21b and 21c formed of a resin electrode having a higher resistance than the metal electrode, and therefore has a higher resistance than the second path A2. High (R11> R21, R12> R22). Thus, the first route A1 has a higher ESR than the second route A2. Further, the second path A2 passes through vias (via 20u, via 20v, via 20w, via 20x) longer and smaller in diameter than the vias (20s, 20t) of the first path A1. High inductance (L21> L11, L22> L12). Thus, the second route A2 has a higher ESL than the first route A1.

  Although the example of the diameters of the vias 20s, 20t, 20u, 20v, 20w, and 20x has been described above, the diameters of the vias 20s, 20t, 20u, 20v, 20w, and 20x are the same as the ESL of the first path A1 and the second path. What is necessary is just to adjust suitably according to what magnitude | size ESL of A2 is made.

  As described above, also in the mounting structure 2, similarly to the mounting structure 1 according to the first embodiment, the first path A1 has a high ESR and the second path A2 has a high ESL. Due to the high ESL of the second path A2, similarly to the mounting structure 1 according to the first embodiment, even if there is a wiring inductance between the multilayer capacitor 21 and the IC 22, the high ESR of the first path A1 is reduced to the IC22. Of the multilayer capacitor 21 and the inductance of the multilayer capacitor 21 can be suppressed.

  The mounting structure 2 of the multilayer capacitor according to the second embodiment has the same effects as the mounting structure 1 according to the first embodiment, and also has the following effects. According to the mounting structure 2 of the multilayer capacitor according to the second embodiment, the diameter of the via on the second path A2 side is made smaller than the diameter of the via on the first path A1 side. And the ESL of the second path A2 can be adjusted, and the ESL of the second path A2 can be made higher than the ESL of the first path A1.

(Third embodiment)
A mounting structure 3 of the multilayer capacitor according to the third embodiment will be described with reference to FIG. FIG. 6 is a sectional view schematically showing a mounting structure 3 of the multilayer capacitor according to the third embodiment.

  The mounting structure 3 is different from the mounting structure 1 according to the first embodiment in that the ESL is adjusted even with the number of vias connected in parallel. In the mounting structure 3, the ESR is adjusted by the external electrodes of the multilayer capacitor 31 as in the first embodiment.

  The mounting structure 3 includes a wiring board 30, a multilayer capacitor 31, and an IC 32 (corresponding to an integrated circuit described in the claims). The multilayer capacitor 31 is a decoupling capacitor connected between the power supply and the ground of the IC 32.

  The wiring board 30 is a multilayer wiring board. Similar to the wiring board 10 according to the first embodiment, the wiring board 30 has a multilayer capacitor 31 mounted inside and an IC 32 mounted on the upper surface 30a. Similarly to the wiring substrate 10, the wiring substrate 30 has a wiring pattern such as a power supply pattern 30c and a ground pattern 30d formed on the upper surface 30a, and includes an insulating layer 30e, a wiring layer 30f, an insulating layer 30g, a wiring layer 30h, and an insulating layer. 30i, a wiring layer 30j, an insulating layer 30k, a wiring layer 30l, and an insulating layer 30m are sequentially stacked. Vias such as vias 30 s, 30 t, 30 u, 30 v, 30 w, 30 x, 30 y, and 30 z are formed inside the wiring board 30.

  The power supply pattern 30c is electrically connected to the power supply pattern 30o of the wiring layer 30f by the via 30s, and is electrically connected to the power supply terminal 32a of the IC 32. The ground pattern 30d is electrically connected to the ground pattern 30n of the wiring layer 30f by the via 30u, and is also electrically connected to the ground terminal 32b of the IC 32.

  The multilayer capacitor 31 is disposed on the insulating layer 30i. Wiring patterns are respectively formed on the wiring layers 30f, 30h, 30j and 30l. In particular, a ground pattern 30n and a power supply pattern 30o are formed on the wiring layer 30f, and wiring patterns 30p and 30q are formed on the wiring layer 30k. Is formed.

  The vias 30w, 30x, 30y, 30z are vias having the same configuration as the vias 20u, 20v, 20w, 20x according to the second embodiment. The vias 30s, 30t, 30u, 30v, 30w, 30x, 30y, and 30z all have the same diameter, for example, 30 μm.

  The via 30s is a via penetrating through the insulating layer 30e, the insulating layer 30g, and a part of the insulating layer 30i. The via 30s electrically connects one power supply terminal (a first main surface portion 31j of a first external electrode 31b described later) of the multilayer capacitor 31 disposed on the insulating layer 30i and a power supply pattern 30c formed on the upper surface 30a. Beer. The via 30s is electrically connected to a power supply pattern 30o formed on the upper surface of the insulating layer 30g.

  The via 30t is a via that penetrates a part of the insulating layer 30g and the insulating layer 30i. The via 30t is a via for electrically connecting one power supply terminal of the multilayer capacitor 31 arranged on the insulating layer 30i and a power supply pattern 30o formed on the upper surface of the insulating layer 30g. Therefore, a part of the via 30s and the via 30t are connected in parallel between one power supply terminal of the multilayer capacitor 31 and the power supply pattern 30o.

  The via 30u is a via penetrating through a part of the insulating layer 30e, the insulating layer 30g, and the insulating layer 30i. Via 30u electrically connects one ground terminal (first main surface portion 31m of second external electrode 31c described later) of multilayer capacitor 31 arranged in insulating layer 30i and ground pattern 30d formed on upper surface 30a. Beer. The via 30u is electrically connected to a ground pattern 30n formed on the upper surface of the insulating layer 30g.

  The via 30v is a via penetrating through a part of the insulating layer 30g and the insulating layer 30i. The via 30v is a via that electrically connects one ground terminal of the multilayer capacitor 31 arranged on the insulating layer 30i and a ground pattern 30n formed on the upper surface of the insulating layer 30g. Therefore, a portion of the via 30u and the via 30v are connected in parallel between one ground terminal of the multilayer capacitor 31 and the ground pattern 30n.

  The multilayer capacitor 31 is a decoupling capacitor as described above. The multilayer capacitor 31 is a chip-type multilayer ceramic capacitor and has a substantially rectangular parallelepiped shape. The multilayer capacitor 31 is a multilayer capacitor similar to the multilayer capacitor 11 according to the first embodiment, and includes a multilayer body 31a, a first external electrode 31b, and a second external electrode 31c. Like the first external electrode 11b according to the first embodiment, the first external electrode 31b includes an end surface 31i along one end surface 31e of the multilayer body 31a, and a first main surface 31j along an upper main surface 31g. , And a second main surface portion 31k along the lower main surface 31h. Similarly to the second external electrode 11c according to the first embodiment, the second external electrode 31c has an end surface portion 31l along the other end surface 31f of the multilayer body 31a and a first main surface portion 31m along the upper main surface 31g. , And a second main surface portion 31n along the lower main surface 31h. The first and second external electrodes 31b and 31c are provided up to a part of the opposing side surfaces connected to the end surfaces 31e and 31f and the main surfaces 31g and 31h.

  The multilayer body 31a has the same configuration as the multilayer body 11a of the multilayer capacitor 11 according to the first embodiment, and includes a plurality of dielectric layers 31p, a plurality of first internal electrodes 31q, and a plurality of second internal electrodes 31r. I have. The first external electrode 31b has the same configuration as the first external electrode 11b of the multilayer capacitor 11 according to the first embodiment. Therefore, the first main surface portion 31j of the first external electrode 31b is formed of a resin electrode having a higher resistance than the metal electrode. The second external electrode 31c has the same configuration as the second external electrode 11c of the multilayer capacitor 11 according to the first embodiment. Therefore, the first main surface portion 31m of the second external electrode 31c is formed of a resin electrode having a higher resistance value than the metal electrode.

  In the mounting structure 3, the first main surface 31j of the first external electrode 31b of the multilayer capacitor 31 is connected to the power supply pattern 30c to which the power supply terminal 32a of the IC 32 is connected by the via 30s, and the first main surface 31j is connected to the via 30t. The first main surface portion 31m of the second external electrode 31c of the multilayer capacitor 31 is connected to the ground pattern 30d to which the ground terminal 32b of the IC 32 is connected by the via 30u and the first main surface portion 31m. Are connected to the ground pattern 30n by vias 30v. In the mounting structure 3, the second main surface portion 31k of the first external electrode 31b of the multilayer capacitor 31 is connected to the power supply pattern 30c to which the power supply terminal 32a of the IC 32 is connected by the via 30w, the via 30x, and a part of the via 30s (the insulating layer). 30e) and the ground pattern 30d to which the ground terminal 32b of the IC 32 is connected, the second main surface portion 31n of the second external electrode 31c of the multilayer capacitor 31 is part of the via 30y, the via 30z, and the via 30u. (A portion penetrating through the insulating layer 30e).

  With this configuration, in the mounting structure 3, between the power supply and the ground of the IC 32, the vias 30s and 30t, the first main surface portion 31j of the first external electrode 31b, the stacked body 31a, and the second external electrode 31c A first path A1 passing through the first main surface 31m and the vias 30u and 30v, a part of the via 30s, the via 30x, the via 30w, the second main surface 31k of the first external electrode 31b, the laminate 31a, and the second external electrode 31c. The second path A2 passing through a part of the second main surface portion 31n, the via 30y, the via 30z, and the via 30u is formed in parallel. In the third embodiment, the vias 30s and 30t correspond to the first vias described in the claims, and the vias 30w, 30x, and a part of the vias 30s correspond to the second vias described in the claims. Correspondingly, the vias 30u and 30v correspond to the third via described in the claims, and the vias 30y, 30z, and a part of the vias 30u correspond to the fourth via described in the claims.

  The via on the second path A2 side is longer than the via on the first path A1 side, similarly to the mounting structure 1 according to the first embodiment. As described above, also in the mounting structure 3, since the length of the via on the second path A2 side is longer than the length of the via on the first path A1 side, the second path A2 is different from the first path A1 due to the difference in the via length. The inductance (ESL) becomes higher than that.

  Further, in the mounting structure 3, a part of the via 30s and the via 30t are connected in parallel, and a part of the via 30u and the via 30v are connected in parallel. Thus, the first path A1 side is configured by connecting two vias in parallel. On the other hand, the second path A2 side is configured only with vias connected in series, and the vias are not connected in parallel. By changing the number of vias connected in parallel on the first path A1 side, the cross-sectional area of the via changes in the same manner as changing the diameter of the via, so that the inductance (ESL) of the via can be adjusted. In particular, if the diameters of the vias are all the same, it is easy to adjust the inductance by the number of parallel vias. Specifically, as the number of vias connected in parallel increases, the inductance increases. Therefore, since only the first path A1 is formed of vias connected in parallel, the second path A2 has a higher inductance (ESL) than the first path A1.

  The equivalent circuit of the mounting structure 3 in which the first path A1 and the second path A2 are formed is the same as that of the first embodiment shown in FIG. Since the first path A1 passes through the first main surface portions 31j and 31m of the first and second external electrodes 31b and 31c formed of a resin electrode having a higher resistance value than the metal electrode, the resistance is lower than that of the second path A2. High (R11> R21, R12> R22). Thus, the first route A1 has a higher ESR than the second route A2. The second path A2 is longer than the vias of the first path A1 (parallel 30s and 30t, parallel 30u and 30v) and not parallel (parts of the series via 30w, the via 30x and the via 30s, the series). (Part of the via 30y, the via 30z, and the via 30u), the inductance is higher than the first path A1 (L21> L11, L22> L12). Thus, the second route A2 has a higher ESL than the first route A1.

  Although the example in which the number of the parallel vias on the first path A1 side is two has been described, the number of the parallel vias on the first path A1 side is the same as the ESL of the first path A1 and the second path A2. What is necessary is just to adjust suitably according to what magnitude | size ESL is made. However, the number of vias that can be arranged in the first main surface portions 31j and 31m depends on the area of the first main surface portions 31j and 31m of the first and second external electrodes 31b and 31c of the multilayer capacitor 31 and the diameter (cross-sectional area) of the vias. Since there is an upper limit, the number is within the upper limit.

  As described above, also in the mounting structure 3, similarly to the mounting structure 1 according to the first embodiment, the first path A1 has a high ESR and the second path A2 has a high ESL. Due to the high ESL of the second path A2, similarly to the mounting structure 1 according to the first embodiment, even if there is a wiring inductance between the multilayer capacitor 31 and the IC 32, the high ESR of the first path A1 is reduced to the IC 32. And the inductance of the multilayer capacitor 31 can contribute to the suppression of anti-resonance.

  The multilayer capacitor mounting structure 3 according to the third embodiment has the same effects as the mounting structure 1 according to the first embodiment, and also has the following effects. According to the mounting structure 3 of the multilayer capacitor according to the third embodiment, the first path A1 side is constituted by a plurality of vias connected in parallel, so that the number of the parallel vias is the same as that of the first path A1 and the second path. The ESL of the path A2 can be adjusted, and the ESL of the second path A2 can be higher than the ESL of the first path A1.

(Fourth embodiment)
The mounting structure 4 of the multilayer capacitor according to the fourth embodiment will be described with reference to FIGS. FIG. 7 is a sectional view schematically showing a mounting structure 4 of the multilayer capacitor according to the fourth embodiment. FIG. 8 is a table showing an example of inductance and resistance according to the material (conductivity) of the via. FIG. 9 shows a case where the first path-side via has a larger diameter than the second path-side via, and the material of the first path-side via has lower conductivity (higher electrical resistivity) than the material of the second path-side via. 5 is a table showing examples of inductance and resistance of the present invention. FIG. 10 shows the inductance and resistance when the first path-side via has a smaller diameter than the second path-side via and the first path-side via has a lower conductivity (higher electrical resistivity) than the second path-side via. It is a table showing an example.

  The mounting structure 4 is different from the mounting structure 2 according to the second embodiment in that the ESR is adjusted by the material of the via (electrical resistivity = 1 / conductivity). In the mounting structure 4, as in the second embodiment, the ESL is adjusted by the length and diameter of the via.

  The mounting structure 4 includes a wiring board 40, a multilayer capacitor 41, and an IC 42 (corresponding to an integrated circuit described in the claims). The multilayer capacitor 41 is a decoupling capacitor connected between the power supply and the ground of the IC 42.

  The wiring board 40 is a multilayer wiring board. Similar to the wiring board 20 according to the second embodiment, the wiring board 40 has a multilayer capacitor 41 mounted inside and an IC 42 mounted on the upper surface 40a. Similarly to the wiring board 20, the wiring board 40 has a wiring pattern such as a power supply pattern 40c and a ground pattern 40d formed on an upper surface 40a, and includes an insulating layer 40e, a wiring layer 40f, an insulating layer 40g, a wiring layer 40h, and an insulating layer. 40i, a wiring layer 40j, an insulating layer 40k, a wiring layer 40l, and an insulating layer 40m are sequentially stacked. Vias such as vias 40s, 40t, 40u, 40v, 40w, and 40x are formed inside the wiring board 40.

  The vias 40s, 40t, 40u, 40v, 40w, and 40x differ from the vias 20s, 20t, 20u, 20v, 20w, and 20x according to the second embodiment in the material of some vias. Like the vias 20s, 20t, 20u, 20v, 20w, and 20x according to the second embodiment, the vias 40u, 40v, 40w, and 40x are plated with a material such as copper having low electrical resistivity (high conductivity). This is a through-hole via. On the other hand, the vias 40s, 40t are through-hole vias plated with a material having a higher electrical resistivity (lower conductivity) than the vias 40u, 40v, 40w, 40x. Examples of the material having a high electric resistivity (low electric conductivity) include conductive carbon and palladium whose electric conductivity is sufficiently lower than that of copper. Therefore, the resistance at the vias 40s, 40t is higher than the resistance at the vias 40u, 40v, 40w, 40x.

  FIG. 8 shows an example of inductance and resistance according to the material (conductivity) of the via. In this example, the length of the via was 40 μm. The diameter of the via was 30 μm. The plating thickness of each material was 10 μm. Therefore, the via has an outer diameter of 30 μm and an inner diameter of 20 μm. The materials of the vias to be compared were copper (conductivity = 5800000 S / m), palladium (conductivity = 9200000 S / m), and conductive carbon (conductivity = 1,000,000 S / m). Using these numerical values, the inductance and resistance of the via of each diameter were calculated. The inductance was calculated at 100 MHz.

  For the copper via, the inductance was 10 pH and the resistance was 0.44 mΩ. In the case of a palladium via, the inductance was 10 pH and the resistance was 2.77 mΩ. In the case of a conductive carbon via, the inductance is 10 pH and the resistance is 25.46 mΩ. As can be seen from this example, the lower the conductivity (the higher the electrical resistivity), the higher the via resistance.

  When the resistances of the vias 40s and 40t are higher than the resistances of the vias 40u, 40v, 40w and 40x, all of the vias 40s and 40t may be formed of a material having low conductivity, or Some of the vias 40s and 40t may be formed of a material having a low conductivity, and the other portion may be formed of a material having a high conductivity such as copper.

  The multilayer capacitor 41 is a decoupling capacitor as described above. The multilayer capacitor 41 is a chip-type multilayer ceramic capacitor, and has a substantially rectangular parallelepiped shape. The multilayer capacitor 41 includes a multilayer body 41a, a first external electrode 41b, and a second external electrode 41c. Like the first external electrode 21b according to the second embodiment, the first external electrode 41b includes an end surface 41i along one end surface 41e of the multilayer body 41a, and a first main surface 41j along the upper main surface 41g. , And a second main surface portion 41k along the lower main surface 41h. Similarly to the second external electrode 21c according to the second embodiment, the second external electrode 41c includes an end surface portion 41l along the other end surface 41f of the multilayer body 41a and a first main surface portion 41m along the upper main surface 41g. , And a second main surface portion 41n along the lower main surface 41h. The first and second external electrodes 41b and 41c are provided up to a part of opposing side surfaces connected to the end surfaces 41e and 41f and the main surfaces 41g and 41h.

  The multilayer body 41a has the same configuration as the multilayer body 21a of the multilayer capacitor 21 according to the second embodiment, and includes a plurality of dielectric layers 41p, a plurality of first internal electrodes 41q, and a second internal electrode 41r. I have.

  The first external electrode 41b is different from the first external electrode 21b of the multilayer capacitor 21 according to the second embodiment in that the first main surface portion 41j is also formed of a metal electrode. Therefore, in the first external electrode 41b, the end face 41i, the first main face 41j, and the second main face 41k are all formed of metal electrodes, and the first main face 41j and the second main face 41k are substantially the same. It is a resistance value. Further, the second external electrode 41c is different from the second external electrode 21c of the multilayer capacitor 21 according to the second embodiment in that the first main surface portion 42m is also formed of a metal electrode. Therefore, in the second external electrode 41c, the end surface portion 41l, the first main surface portion 41m, and the second main surface portion 41n are all formed of metal electrodes, and the first main surface portion 41m and the second main surface portion 41n are substantially the same. It is a resistance value.

  In the mounting structure 4, the first main surface portion 41j of the first external electrode 41b of the multilayer capacitor 41 is connected to the power supply pattern 40c to which the power supply terminal 42a of the IC 42 is connected via the via 40s, and the ground terminal 42b of the IC 42 is connected. The first main surface 41m of the second external electrode 41c of the multilayer capacitor 41 is connected to the ground pattern 40d via a via 40t. In the mounting structure 4, the second main surface portion 41k of the first external electrode 41b of the multilayer capacitor 41 is connected to the power supply pattern 40c to which the power supply terminal 42a of the IC 42 is connected by the vias 40u, 40v, and a part of the vias 40s (insulating layer). 40e), and the second main surface portion 41n of the second external electrode 41c of the multilayer capacitor 41 is connected to the ground pattern 40d to which the ground terminal 42b of the IC 42 is connected via the vias 40w, 40x, and 40t. They are connected via a part (a part penetrating the insulating layer 40e).

  With this configuration, in the mounting structure 4, similarly to the mounting structure 2 according to the second embodiment, the via 40s, the first main surface portion 41j of the first external electrode 41b, and the stacked The first path A1 passing through the body 41a, the first main surface 41m of the second external electrode 41c, and the via 40t, a part of the via 40s, the via 40v, the via 40u, the second main surface 41k of the first external electrode 41b, and the lamination The body 41a, the second main surface 41n of the second external electrode 41c, the via 40w, the second path A2 passing through a part of the via 40x and a part of the via 40t are formed in parallel. In the fourth embodiment, the vias 40s correspond to the first vias described in the claims, and the vias 40u, 40v, and some of the vias 40s correspond to the second vias described in the claims. , Via 40t corresponds to a third via described in the claims, and a part of via 40w, via 40x and via 40t corresponds to a fourth via described in the claims.

  The length of the via on the second path A2 side is longer than the length of the via on the first path A1 side, similarly to the mounting structure 2 according to the second embodiment. The diameter of the via on the second path A2 side is smaller than the diameter of the via on the first path A1 side, similarly to the mounting structure 2 according to the second embodiment. Therefore, the second path A2 has a higher inductance (ESL) than the first path A1.

  In particular, in the mounting structure 4, the vias 40s and 40t serving as vias on the first path A1 side are mainly formed of a material having lower conductivity than the vias 40u, 40v, 40w, and 40x serving as vias on the second path A2 side. ing. Thus, by changing the material (conductivity) for forming the via, the resistance (ESR) can be adjusted by the via. Specifically, when a via is formed of a material having low conductivity (high electrical resistivity), the resistance at the via increases. The via on the second path A2 side includes a part of the vias 40s and 40t with low conductivity, while the via on the first path A1 side includes all the vias 40s and 40t with low conductivity. Most of the vias on the second path A2 side are formed of vias 40u, 40v, 40w, and 40x having high conductivity. Therefore, the first path A1 has a higher resistance (ESR) than the second path A2.

  Note that as the via length increases, the via resistance increases. Also, as the cross-sectional area of the via decreases, the resistance of the via increases. In the mounting structure 4, the via on the first path A1 side has a shorter length and a larger diameter (larger cross-sectional area) than the via on the second path A2 side. Therefore, in order to increase the resistance of the first path A1 of the via having the shorter length and the larger cross-sectional area than that of the second path A2, the vias 40u of the second path A2 are added to the vias 40s and 40t of the first path A1. , 40v, 40w, and 40x.

  FIG. 9 shows that the via on the first path A1 has a larger diameter than the via on the second path A2, and the material of the via on the first path A1 has a higher conductivity than the material of the via on the second path A2. An example of the inductance and the resistance when the electric resistance is low (the electric resistivity is high) is shown. In this example, the diameter of the via on the first path A1 side is 50 μm, and the material is conductive carbon (conductivity = 1,000,000 S / m). The diameter of the via on the second path A2 side is 30 μm, and the material is copper (conductivity = 58000000 S / m). The length of the via was 40 μm, which is the same length on the first path A1 side and the second path A2 side. The plating thickness of each material was 10 μm, which is the same thickness on the first path A1 side and the second path A2 side. Using these numerical values, the inductance and resistance of the via on the first path A1 side and the via on the second path A2 side were calculated. The inductance was calculated at 100 MHz.

  When the number of vias is one, the inductance of the via on the first path A1 side is 7.3 pH, the resistance is 14.15 mΩ, the inductance of the via on the second path A2 side is 10.0 pH, and the resistance is Was 0.4 mΩ. As can be seen from this example, the vias on the first path A1 having a lower conductivity have higher resistance than the vias on the second path A2 having a higher conductivity. In addition, the via on the second path A2 having a smaller diameter has a higher inductance than the via on the first path A1 having a larger diameter.

  FIG. 9 also shows, as a reference example, the inductance and the resistance when the number of vias connected in parallel is changed. When the number of vias on the first path A1 side is one, the inductance is 7.3 pH and the resistance is 14.15 mΩ, and when the number of vias is two, the inductance is 3.65 pH and the resistance is 7. 08 mΩ, three wires have an inductance of 2.43 pH and a resistance of 4.72 mΩ, and four wires have an inductance of 1.83 pH, a resistance of 3.54 mΩ and five wires In this case, the inductance was 1.46 pH and the resistance was 2.83 mΩ. When the number of vias on the second path A2 side is one, the inductance is 10.0 pH and the resistance is 0.4 mΩ. When the number of vias is two, the inductance is 5.0 pH and the resistance is m0. 2 ohms, 3 wires have an inductance of 3.33 pH and a resistance of 0.15 mΩ, and 4 wires have an inductance of 2.50 pH and a resistance of 0.11 mΩ and 5 wires In the case of the above, the inductance was 2.00 pH and the resistance was 0.09 mΩ. As can be seen from this example, as the number of parallel vias increases, the inductance decreases and the resistance decreases. From this example, it can be seen that the ESL can be adjusted by the number of parallel vias in the third embodiment described above.

  FIG. 10 shows an example of inductance and resistance when the via on the first path A1 side is smaller in diameter than the via on the second path A2 side as a comparative example with respect to FIG. In this example, the diameter of the via on the first path A1 side is 30 μm, and the material is conductive carbon. The via on the second path A2 side has a diameter of 50 μm and is made of copper. The length of the via was 40 μm, which is the same length on the first path A1 side and the second path A2 side. The plating thickness of each material was 10 μm, which is the same thickness on the first path A1 side and the second path A2 side. Using these numerical values, the inductance and resistance of the via on the first path A1 side and the via on the second path A2 side were calculated. The inductance was calculated at 100 MHz.

  When the number of vias is one, the inductance of the via on the first path A1 side is 10.0 pH, the resistance is 25.46 mΩ, the inductance of the via on the second path A2 side is 7.30 pH, and the resistance is Was 0.24 mΩ. Comparing the inductance shown in FIG. 10 and the inductance shown in FIG. 9 in the case where the number of vias is one, it is found that the inductance decreases as the diameter of the via increases. From this comparison result, it is understood that the ESL can be adjusted by the diameter of the via in the fourth embodiment and the above-described second embodiment.

  FIG. 10 also shows, as a reference example, the inductance and the resistance when the number of vias connected in parallel on the first path side is changed. When the number of vias is one, the inductance is 10.00 pH and the resistance is 25.46 mΩ, and when the number of vias is two, the inductance is 5.00 pH and the resistance is 12.73 mΩ and the number of vias is three. In the case of the above, the inductance is 3.33 pH and the resistance is 8.49 mΩ. In the case of four, the inductance is 1.83 pH, the resistance is 3.54 mΩ, and in the case of five, the inductance is The pH was 0.91 and the resistance was 1.77 mΩ. This example also shows that the ESL can be adjusted by the number of parallel vias in the third embodiment described above.

  An equivalent circuit of the mounting structure 3 in which the first path A1 and the second path A2 are formed is the same as that of the first embodiment shown in FIG. Since the first path A1 passes through the vias 40s and 40t formed of a material having low conductivity (high electric resistivity), the first path A1 has higher resistance than the second path A2 (R11> R21, R12> R22). Thus, the first route A1 has a higher ESR than the second route A2. The second path A2 is one of the vias (the vias 40u, 40v, a part of the vias 40v, and the vias 40s, the vias 40w, the vias 40x, and the vias 40t) longer and smaller in diameter than the vias (40s, 40t) of the first path A1. Part), the inductance is higher than the first path A1 (L21> L11, L22> L12). Thus, the second route A2 has a higher ESL than the first route A1.

  As described above, also in the mounting structure 4, similarly to the mounting structure 1 according to the first embodiment, the first path A1 has a high ESR and the second path A2 has a high ESL. Due to the high ESL of the second path A2, similarly to the mounting structure 1 according to the first embodiment, even if the wiring inductance exists between the multilayer capacitor 41 and the IC 42, the high ESR of the first path A1 is , And the inductance of the multilayer capacitor 41 can be suppressed.

  The mounting structure 4 of the multilayer capacitor according to the fourth embodiment has the same effects as the mounting structure 2 according to the second embodiment, and also has the following effects. According to the mounting structure 4 of the multilayer capacitor according to the fourth embodiment, the vias 40s, 40t on the first path A1 side have lower conductivity (electrical resistance) than the vias 40u, 40v, 40w, 40x on the second path A2 side. By using a material having a high rate, the ESR of the first path A1 and the second path A2 can be adjusted, and the ESR of the first path A1 can be higher than the ESR of the second path A2.

(Fifth embodiment)
The mounting structure 5 of the multilayer capacitor according to the fifth embodiment will be described with reference to FIGS. FIG. 11 is a cross-sectional view schematically showing the mounting structure 5 of the multilayer capacitor according to the fifth embodiment. FIG. 12 shows that the first path side via and the second path side via have the same diameter, the first path side via has lower conductivity than the second path side via, and the number of parallel vias on the first path side is smaller. It is a table | surface which shows the example of the inductance and resistance at the time of changing.

  The mounting structure 5 is different from the mounting structure 3 according to the third embodiment in that the ESR is adjusted by the material of the via (electrical resistivity = 1 / conductivity). In the mounting structure 5, similarly to the third embodiment, the ESL is adjusted by the number of vias in parallel with the length of the via.

  The mounting structure 5 includes a wiring board 50, a multilayer capacitor 51, and an IC 52 (corresponding to an integrated circuit described in the claims). The multilayer capacitor 51 is a decoupling capacitor connected between the power supply and the ground of the IC 52.

  The wiring board 50 is a multilayer wiring board. Similarly to the wiring board 30 according to the third embodiment, the wiring board 50 has a multilayer capacitor 51 mounted inside and an IC 52 mounted on the upper surface 50a. Similarly to the wiring substrate 30, the wiring substrate 50 has a wiring pattern such as a power supply pattern 50c and a ground pattern 50d formed on the upper surface 50a, and includes an insulating layer 50e, a wiring layer 50f, an insulating layer 50g, a wiring layer 50h, 50i, a wiring layer 50j, an insulating layer 50k, a wiring layer 501, and an insulating layer 50m are sequentially stacked. Vias such as vias 50s, 50t, 50u, 50v, 50w, 50x, 50y, and 50z are formed inside the wiring board 50.

  The vias 50 s, 50 t, 50 u, 50 v, 50 w, 50 x, 50 y, and 50 z are different from the vias 30 s, 30 t, 30 u, 30 v, 30 w, 30 x, 30 y, and 30 z according to the third embodiment. Are different. The vias 50w, 50x, 50y, and 50z are made of copper having a low electric resistivity (high conductivity), like the vias 30s, 30t, 30u, 30v, 30w, 30x, 30y, and 30z according to the third embodiment. This is a through-hole via plated with a material. On the other hand, the vias 50s, 50t, 50u, and 50v are through-hole vias plated with a material having a higher electrical resistivity (lower conductivity) than the vias 50w, 50x, 50y, and 50z. Therefore, the resistance in the vias 50s, 50t, 50u, and 50v is higher than the resistance in the vias 50w, 50x, 50y, and 50z. Note that only one of the via 50s and the via 50t may be formed of a material having a high electrical resistivity, or only one of the via 50u and the via 50v may be formed of a material having a high electrical resistivity. May be formed.

  The multilayer capacitor 51 is a decoupling capacitor as described above. The multilayer capacitor 51 is a chip-type multilayer ceramic capacitor, and has a substantially rectangular parallelepiped shape. The multilayer capacitor 51 includes a multilayer body 51a, a first external electrode 51b, and a second external electrode 51c. Similarly to the first external electrode 31b according to the third embodiment, the first external electrode 51b includes an end surface 51i along one end surface 51e of the multilayer body 51a and a first main surface 51j along the upper main surface 51g. , And a second main surface portion 51k along the lower main surface 51h. Similarly to the third external electrode 31c according to the third embodiment, the second external electrode 51c includes an end surface portion 51l along the other end surface 51f of the multilayer body 51a and a first main surface portion 51m along the upper main surface 51g. , And a second main surface portion 51n along the lower main surface 21h. The first and second external electrodes 51b and 51c are provided up to a part of the opposing side surfaces connected to the end surfaces 51e and 51f and the main surfaces 51g and 51h.

  The multilayer body 51a has the same configuration as the multilayer body 31a of the multilayer capacitor 31 according to the third embodiment, and includes a plurality of dielectric layers 51p, a plurality of first internal electrodes 51q, and a plurality of second internal electrodes 51r. I have. The first external electrode 51b has the same configuration as the first external electrode 41b of the multilayer capacitor 41 according to the fourth embodiment. The second external electrode 51c has the same configuration as the second external electrode 41c of the multilayer capacitor 41 according to the fourth embodiment.

  In the mounting structure 5, the first main surface 51j of the first external electrode 51b of the multilayer capacitor 51 is connected to the power supply pattern 50c to which the power supply terminal 52a of the IC 52 is connected via the via 50s, and the first main surface 51j is connected to the power supply pattern 50c. The first main surface 51m of the second external electrode 51c of the multilayer capacitor 51 is connected to the ground pattern 50d connected to the power supply pattern 50o via the via 50t and to the ground terminal 52b of the IC 52 via the via 50u. The first main surface 51m is connected to the ground pattern 50n via the via 50v. In the mounting structure 5, the second main surface 51k of the first external electrode 51b of the multilayer capacitor 51 is connected to the power supply pattern 50c to which the power supply terminal 52a of the IC 52 is connected by the via 50w, the via 50x, and a part of the via 50s (the insulating layer). 50e), the second main surface 51n of the second external electrode 51c of the multilayer capacitor 51 is connected to the ground pattern 50d connected to the ground terminal 52b of the IC 52 via the vias 50y, 50Z and 50u. They are connected via a part (a part penetrating the insulating layer 50e).

  With this configuration, in the mounting structure 5, similarly to the mounting structure 3 according to the third embodiment, the vias 50s and 50t, the first main surface 51j of the first external electrode 51b are provided between the power supply and the ground of the IC 52. A first path A1 passing through the stacked body 51a, the first main surface portion 51m of the second external electrode 51c and the vias 50u and 50v, and a part of the via 50s, the via 50x, the via 50w, and the second main electrode of the first external electrode 51b. The surface portion 51k, the stacked body 51a, the second main surface portion 51n of the second external electrode 51c, the second path A2 passing through a part of the via 50y, the via 50z, and the via 50u are formed in parallel. In the fifth embodiment, the vias 50s and 50t correspond to the first vias described in the claims, and the vias 50w, 50x, and a part of the vias 50s correspond to the second vias described in the claims. Correspondingly, the vias 50u and 50v correspond to the third vias described in the claims, and the vias 50y, 50z, and a part of the vias 50u correspond to the fourth vias described in the claims.

  The length of the via on the second path A2 side is longer than the length of the via on the first path A1 side, similarly to the mounting structure 3 according to the third embodiment. Further, the first path A1 side is configured by a plurality of vias connected in parallel, similarly to the mounting structure 3 according to the third embodiment. Therefore, the second path A2 has a higher inductance (ESL) than the first path A1.

  The via on the first path A1 side is formed of a material having a lower conductivity (higher electrical resistivity) than the via on the second path A2 side, similarly to the mounting structure 4 according to the fourth embodiment. . Therefore, the first path A1 has a higher resistance (ESR) than the second path A2.

  In FIG. 12, the diameter of the via on the first path A1 side and the diameter of the via on the second path A2 side are the same, and the material of the via on the first path A1 side has a higher conductivity than the material of the via on the second path A2 side. 9 shows an example of the inductance and the resistance when the number of parallel vias on the first path A1 side is changed. In this example, the diameter of the via on the first path A1 side is 50 μm, and the material is conductive carbon (conductivity = 1,000,000 S / m). The diameter of the via on the second path A2 side is 50 μm, and the material is copper (conductivity = 58000000 S / m). The length of the via was 40 μm, which is the same length on the first path A1 side and the second path A2 side. The plating thickness of each material was 10 μm, which is the same thickness on the first path A1 side and the second path A2 side. The number of parallel vias on the first path A1 side was changed from one to five. The number of vias on the second path A2 side is only one. Using these numerical values, the inductance and resistance of the via on the first path A1 side and the via on the second path A2 side were calculated. The inductance was calculated at 100 MHz.

  When the number of vias on the second path A2 side was one, the inductance was 7.30 pH and the resistance was 0.24 mΩ. When the number of vias on the first path A1 side is one, the inductance is 7.30 pH and the resistance is 14.15 mΩ. When the number of vias is two, the inductance is 3.65 pH and the resistance is 7. 08 mΩ, three wires have an inductance of 2.43 pH and a resistance of 4.72 mΩ, and four wires have an inductance of 1.83 pH, a resistance of 3.54 mΩ and five wires In this case, the inductance was 1.46 pH and the resistance was 2.83 mΩ. As can be seen from this example, as the number of parallel vias on the first path A1 increases, the inductance of the via on the first path A1 becomes lower than that of the via on the second path A2 (the via on the side of the second path A2). The via has a higher inductance than the via on the first path A1 side). Also, as the number of parallel vias on the first path A1 increases, the resistance of the via on the first path A1 decreases. However, since the via on the first path A1 side is formed of a material having sufficiently lower conductivity than the via on the second path A2 side, even if the number of parallel vias is increased, the via on the first path A1 side is increased. The via has a higher resistance than the via on the second path A2 side.

  The equivalent circuit of the mounting structure 5 in which the first path A1 and the second path A2 are formed is the same as that of the first embodiment shown in FIG. The first path A1 passes through the vias 50s, 50t, 50u, and 50v formed of a material having low conductivity (high electric resistivity), and thus has a higher resistance than the second path A2 (R11> R21, R12>). R22). Thus, the first route A1 has a higher ESR than the second route A2. The second path A2 is longer than the vias of the first path A1 (parallel 50s and 50t, parallel 50u and 50v) and not parallel (parts of the series via 50w, the via 50x and the via 50s, the series). Of the vias 50y, 50z and 50u), the inductance is higher than the first path A1 (L21> L11, L22> L12). Thus, the second route A2 has a higher ESL than the first route A1.

  Thus, also in the mounting structure 5, similarly to the mounting structure 1 according to the first embodiment, the first path A1 has a high ESR and the second path A2 has a high ESL. Due to the high ESL of the second path A2, similarly to the mounting structure 1 according to the first embodiment, even if the wiring inductance exists between the multilayer capacitor 51 and the IC 52, the high ESR of the first path A1 is reduced to the IC 52. And the inductance of the multilayer capacitor 51 can contribute to suppression of anti-resonance.

  The mounting structure 5 of the multilayer capacitor according to the fifth embodiment has the same effects as the mounting structure 3 according to the third embodiment, and also has the following effects. According to the mounting structure 5 of the multilayer capacitor according to the fifth embodiment, the vias 50s, 50t, 50u, and 50v on the first path A1 side have a higher conductivity than the vias 50w, 50x, 50y, and 50z on the second path A2 side. The ESR of the first path A1 and the second path A2 can be adjusted by forming the first path A1 and the second path A2 with a material having a low (high electric resistivity), and the ESR of the first path A1 can be higher than the ESR of the second path A2.

  According to the multilayer capacitor mounting structures 4 and 5 according to the fourth and fifth embodiments, the existing low ESR and low ESL multilayer capacitors 41 and 51 can be used without using a special multilayer capacitor. Thus, the suppression of the anti-resonance described above can be realized. Therefore, cost can be reduced.

  With reference to FIG. 13, an example of a method for manufacturing a via made of a material having low conductivity according to the fourth and fifth embodiments will be described. FIG. 13 is an explanatory diagram of an example of a method for manufacturing a via with low conductivity (high electrical resistivity). FIG. 13 shows a part of the wiring board 60 including the multilayer capacitor 61.

  In this example, the wiring board 60 has an insulating layer 60e, a wiring layer 60f, an insulating layer 60g, a wiring layer 60h, an insulating layer 60i, and the like stacked in this order from the upper side in FIG. Vias such as vias 60 s and 60 t are formed inside the wiring board 60.

  First, vias forming a part of the vias 60s and 60t are formed in the respective layers 60e, 60f, 60g, 60h, and 60i. Specifically, vias 60se and 60te are formed in the insulating layer 60e, vias 60sf and 60tf are formed in the wiring layer 60f, vias 60sg and 60tg are formed in the insulating layer 60g, and vias 60sh are formed in the wiring layer 60h. Then, a via 60th is formed, and a via 60si and a via 60ti are formed in the insulating layer 60i. At this time, the vias of some layers are formed using a material having a low conductivity and the vias of the other layers are formed using a material having a high conductivity, or the vias of all the layers are formed using a material having a low conductivity. It is formed using a low material. For example, only the vias 60sg and 60tg of the insulating layer 60g are formed using conductive carbon, and the vias of the other layers are formed using copper.

  Then, by stacking the layers 60e, 60f, 60g, 60h, and 60i, the via 60s including the via 60se, the via 60sf, the via 60sg, the via 60sh and the via 60si, and the via 60te, the via 60tf, the via 60tg, the via 60th, and the via 60th. And a via 60t composed of 60ti. By forming the vias 60s and 60t in this manner, the resistance (ESR) of the vias 60s and 60t can be easily adjusted. In particular, the resistance of the vias 60s and 60t can be adjusted by replacing an arbitrary layer.

  The reason why the anti-resonance can be suppressed by using the mounting structures 1 to 5 of the multilayer capacitor according to the first to fifth embodiments described above will be described by using impedance (Z) on a complex plane and admittance (Y) on a complex plane. This will be described in detail. Hereinafter, first, the reason why the effect of suppressing the anti-resonance is reduced due to the presence of the wiring inductance in the conventional mounting structure of the multilayer capacitor will be described. Next, the mounting of the multilayer capacitor according to the first to fifth embodiments will be described. The reason why the anti-resonance can be suppressed when the structures 1 to 5 are used even if the wiring inductance exists will be described. The conventional multilayer capacitor mounting structure is such that a low ESL and high ESR first multilayer capacitor and a low ESL and low ESR second multilayer capacitor are connected in parallel between the power supply and the ground of the IC on the wiring board. And

  A case of a conventional mounting structure of a multilayer capacitor will be described with reference to FIGS. FIG. 14 is an equivalent circuit involved in anti-resonance in a mounting structure of a conventional multilayer capacitor. FIG. 15 shows frequency characteristics of impedance in a conventional mounting structure of a multilayer capacitor. FIG. 16 is a complex plane of admittance in a conventional multilayer capacitor mounting structure. FIG. 17 is a complex plane of impedance in a conventional multilayer capacitor mounting structure.

  FIG. 14 shows a simple equivalent circuit showing only those involved in anti-resonance, and omits the capacitances of the first and second multilayer capacitors not involved in anti-resonance. Symbol C1 'is the capacity of the IC, which was set to 30 nF. The impedance consisting of the capacitance C1 'of this IC is Z2', and its admittance is Y2 '. Symbol L1 'is the inductance (low ESL) of the first multilayer capacitor, which was set to 50 pH. Symbol R1 'is the resistance (high ESR) of the first multilayer capacitor, which was set to 100 mΩ. The impedance consisting of the inductance L1 'and the resistance R1' of this first multilayer capacitor is Z3 ', and its admittance is Y3'. Symbol L2 'is the inductance (low ESL) of the second multilayer capacitor, which was set to 50 pH. Symbol R2 'is the resistance (low ESR) of the second multilayer capacitor, which was set to 10 mΩ. The impedance formed by the inductance L2 'and the resistance R2' of this second multilayer capacitor is Z4 ', and its admittance is Y4'. Symbol L3 'is the inductance of the wiring between the IC and the multilayer capacitor, which was set to 100 pH. The impedance consisting of the inductance L3 'of this wiring is Z5', and its admittance is Y5 '. The impedance consisting of the impedance Z3 'of the first parallel multilayer capacitor and the impedance Z4' of the second multilayer capacitor is Z6 ', and its admittance is Y6'. The impedance consisting of the series impedance Z6 'and the impedance Z5' is defined as Z7 ', and its admittance is defined as Y7'. The impedance (power supply impedance) of the entire circuit including the parallel impedance Z2 'and the impedance Z7' is defined as Z1 ', and its admittance is defined as Y1'.

  In the frequency characteristics of the impedance shown in FIG. 15, the horizontal axis represents frequency [Hz] and the vertical axis represents impedance [Ω]. The frequency ranges from 0.01 GHz to 1.00 GHz. The solid line indicated by the symbol ZF1 'is the frequency characteristic of the impedance Z1' of the entire circuit. The dashed line indicated by the symbol ZF2 'is a frequency characteristic of the impedance Z2' of the IC. An alternate long and short dash line indicated by reference symbol ZF3 'is a frequency characteristic of the impedance Z3' of the first multilayer capacitor. A two-dot chain line indicated by a symbol ZF4 'is a frequency characteristic of the impedance Z4' of the second multilayer capacitor. A dashed line indicated by a symbol ZF7 'is a frequency characteristic of the impedance Z7'. The symbol AF 'on the frequency characteristic ZF1' of the impedance Z1 'indicates the anti-resonance frequency at which the impedance becomes highest.

  In the complex plane of admittance shown in FIG. 16, the horizontal axis is the conductance G (real part) and the vertical axis is the susceptance B (imaginary part). The solid line indicated by the reference sign YP1 'indicates the admittance Y1' on a complex plane. The dashed line indicated by the symbol YP2 'indicates the admittance Y2' on a complex plane. An alternate long and short dash line YP3 'indicates admittance Y3' on a complex plane. The two-dot chain line indicated by the symbol YP4 'indicates the admittance Y4' on a complex plane. The dashed line indicated by the symbol YP6 'indicates the admittance Y6' on a complex plane. The dashed line indicated by the symbol YP7 'indicates the admittance Y7' on a complex plane. The vector indicated by the symbol YV1 'indicates the admittance Y1' at the anti-resonance frequency AF 'on a complex plane. The vector indicated by the symbol YV2 'indicates the admittance Y2' at the anti-resonance frequency AF 'on a complex plane. The vector indicated by the symbol YV3 'indicates the admittance Y3' at the anti-resonance frequency AF 'on a complex plane. The vector indicated by the symbol YV4 'indicates the admittance Y4' at the anti-resonance frequency AF 'on a complex plane. The vector indicated by the symbol YV6 'indicates the admittance Y6' at the anti-resonance frequency AF 'on a complex plane. The vector indicated by the symbol YV7 'indicates the admittance Y7' at the anti-resonance frequency AF 'on a complex plane.

  In the complex plane of the impedance shown in FIG. 17, the horizontal axis is the resistance R (real part), and the vertical axis is the reactance X (imaginary part). The solid line indicated by the symbol ZP1 'indicates the impedance Z1' on a complex plane. An alternate long and short dash line indicated by reference sign ZP5 'indicates the impedance Z5' on a complex plane. A two-dot chain line indicated by a symbol ZP6 'indicates the impedance Z6' on a complex plane. The broken line indicated by the symbol ZP7 'indicates the impedance Z7' on a complex plane. The vector indicated by the symbol ZV1 'indicates the impedance Z1' at the anti-resonance frequency AF 'on a complex plane. The vector indicated by the symbol ZV5 'indicates the impedance Z5' at the anti-resonance frequency AF 'on a complex plane. The vector indicated by the symbol ZV6 'indicates the impedance Z6' at the anti-resonance frequency AF 'on a complex plane. The vector indicated by the symbol ZV7 'indicates the impedance Z7' at the anti-resonance frequency AF 'on a complex plane.

  Note that the impedance consisting of only the resistor is only the real part. The impedance consisting only of the capacitance is only the imaginary part. The impedance consisting of only the inductance is only the imaginary part. The impedance composed of the series resistance and inductance has a real part and an imaginary part.

  The reason why the anti-resonance suppression effect is reduced when a conventional multilayer capacitor mounting structure is used will be described with reference to FIGS. In the following description, a part connected in parallel in the equivalent circuit shown in FIG. 14 is considered by admittance on a complex plane shown in FIG. 16, and a part connected in series is represented by an impedance on a complex plane shown in FIG. Think.

  Since the resistance R1 'and inductance L1' (impedance Z3 ') of the first multilayer capacitor and the resistance R2' and inductance L2 '(impedance Z4') of the second multilayer capacitor are connected in parallel, the complex plane of FIG. The above admittance YP3 ′ and admittance YP4 ′ are combined to form an admittance YP6 ′, and a vector YV3 ′ indicating the admittance Y3 ′ at the anti-resonance frequency AF ′ and a vector YV4 ′ indicating the admittance Y4 ′ are combined to form the admittance Y6. 'Vector YV6'. The admittance YP6 'becomes an impedance ZP6' on the complex plane in FIG. 17, and the vector YV6 'indicating the admittance Y6' at the anti-resonance frequency AF 'becomes a vector ZV6' indicating the impedance Z6 'on the complex plane in FIG. .

  Since the wiring inductance L3 ′ (impedance Z5 ′) and the parallel portion (impedance Z6 ′) of the first and second multilayer capacitors are connected in series, the impedance ZP5 ′ and the impedance ZP6 ′ on the complex plane of FIG. Are combined into an impedance ZP7 ', and a vector ZV5' indicating the impedance Z5 'at the anti-resonance frequency AF' and a vector ZV6 'indicating the impedance Z6' are combined to form a vector ZV7 'indicating the impedance Z7'. Thus, the presence of the wiring inductance L3 'causes the impedance ZP7' to approach the X-axis. The impedance ZP7 'is admittance YP7' on the complex plane in FIG. 16, and the vector ZV7 'indicating the impedance Z7' at the anti-resonance frequency AF 'is a vector YV7' indicating admittance Y7 'on the complex plane in FIG. .

  Since the capacitance C1 'of the IC (impedance Z2') and the inductance L3 'of the wiring and the series part (impedance Z7') of the first and second multilayer capacitors are connected in parallel, the capacitance C1 'on the complex plane of FIG. The admittance YP2 ′ and the admittance YP7 ′ are combined to form the admittance YP1 ′, and the vector YV2 ′ representing the admittance Y2 ′ at the anti-resonance frequency AF ′ and the vector YV7 ′ representing the admittance Y7 ′ are combined to form the admittance Y1 ′. A vector YV1 ′ shown in FIG. The admittance YP1 'becomes an impedance ZP1' on the complex plane in FIG. 17, and the vector YV1 'indicating the admittance Y1' at the anti-resonance frequency AF 'becomes a vector ZV1' indicating the impedance Z1 'on the complex plane in FIG. .

  As the impedance ZP7 'approaches the X axis on the complex plane in FIG. 17, the admittance YP7' approaches the B axis on the complex plane in FIG. Thus, the vector YV7 'indicating the admittance Y7' at the anti-resonance frequency AF 'approaches the B axis, and the vector YV1' indicating the admittance Y1 'at the anti-resonance frequency AF' approaches the origin of the complex plane in FIG. Accordingly, the vector ZV1 'indicating the impedance Z1' at the anti-resonance frequency AF 'moves away from the origin of the complex plane in FIG. That is, the level of the impedance Z1 'increases at the anti-resonance frequency AF'. As a result, as shown in FIG. 15, in the frequency characteristic ZF1 'of the impedance Z1', the level of the impedance is increased at the anti-resonance frequency AF ', and a sharp angle-shaped characteristic is obtained. That is, anti-resonance is not suppressed.

  With reference to FIGS. 18 to 21, a description will be given of the case where the multilayer capacitor mounting structures 1 to 5 according to the first to fifth embodiments are used. FIG. 18 is an equivalent circuit related to anti-resonance in the mounting structure of the multilayer capacitor according to the embodiment. FIG. 19 shows frequency characteristics of impedance in the mounting structure of the multilayer capacitor according to the embodiment. FIG. 20 is a complex plane of admittance in the mounting structure of the multilayer capacitor according to the embodiment. FIG. 21 is a complex plane of impedance in the mounting structure of the multilayer capacitor according to the embodiment.

  FIG. 18 shows a simple equivalent circuit showing only those involved in anti-resonance, and the capacitances of the multilayer capacitors 11, 21, 31, 41, 51 not involved in anti-resonance are omitted. The reference numeral C1 denotes the capacitance of the ICs 12, 22, 32, 42, and 52, which is the same as the capacitance C1 'of the IC shown in FIG. The impedance composed of the capacitance C1 of the ICs 12, 22, 32, 42, and 52 is Z2, and the admittance is Y2.

  Reference symbol L1 denotes the inductance (low ESL) of the first path A1, which was set to the same 50 pH as the inductance L1 'of the first multilayer capacitor shown in FIG. This inductance L1 corresponds to the sum of the inductance L11 and the inductance 12 of the equivalent circuit shown in FIG. Reference symbol R1 denotes the resistance (high ESR) of the first path A1, which is 100 mΩ, which is the same as the resistance R1 'of the first multilayer capacitor shown in FIG. This resistance R1 corresponds to the sum of the resistance R11 and the resistance 12 of the equivalent circuit shown in FIG. The impedance formed by the inductance L1 and the resistance R1 of the first path A1 is represented by Z3, and its admittance is represented by Y3.

  Symbol L2 is the inductance (high ESL) of the second path A2, which was set to 200 pH. This inductance L2 corresponds to the sum of the inductance L21 and the inductance L22 of the equivalent circuit shown in FIG. Reference symbol R2 denotes a resistance (low ESR) of the second path A2, which is set to 10 mΩ which is the same as the resistance R2 'of the second multilayer capacitor shown in FIG. This resistor R2 corresponds to the sum of the resistors R21 and R22 of the equivalent circuit shown in FIG. The impedance formed by the inductance L2 and the resistance R2 of the second path A2 is defined as Z4, and its admittance is defined as Y4.

  Reference symbol L3 is the inductance of the wiring between the ICs 12, 22, 32, 42, 52 and the multilayer capacitors 11, 21, 31, 41, 51, and is 100 pH, which is the same as the inductance L3 'of the wiring shown in FIG. The impedance consisting of the inductance L3 of this wiring is Z5, and its admittance is Y5.

  The impedance composed of the impedance Z3 of the parallel first path A1 and the impedance Z4 of the second path A2 is Z6, and the admittance thereof is Y6. The impedance consisting of the series impedance Z6 and the impedance Z5 is defined as Z7, and the admittance is defined as Y7. The impedance (power supply impedance) of the entire circuit including the parallel impedance Z2 and the impedance Z7 is defined as Z1, and its admittance is defined as Y1.

  In the frequency characteristics of the impedance shown in FIG. 19, the horizontal axis represents frequency [Hz], and the vertical axis represents impedance [Ω]. The frequency ranges from 0.01 GHz to 1.00 GHz. The solid line indicated by the symbol ZF1 is the frequency characteristic of the impedance Z1 of the entire circuit. The broken line indicated by the symbol ZF2 is the frequency characteristic of the impedance Z2 of the IC. An alternate long and short dash line indicated by reference sign ZF3 is a frequency characteristic of the impedance Z3 of the first path A1. A two-dot chain line indicated by a symbol ZF4 is a frequency characteristic of the impedance Z4 of the second path A2. The broken line indicated by the symbol ZF7 is the frequency characteristic of the impedance Z7 '. The symbol AF on the frequency characteristic ZF1 of the impedance Z1 indicates the anti-resonance frequency at which the impedance becomes highest.

  In the complex plane of admittance shown in FIG. 20, the horizontal axis is the conductance G (real part), and the vertical axis is the susceptance B (imaginary part). The solid line indicated by the symbol YP1 shows the admittance Y1 on a complex plane. The dashed line indicated by the symbol YP2 indicates the admittance Y2 on a complex plane. An alternate long and short dash line indicated by a symbol YP3 indicates the admittance Y3 on a complex plane. A two-dot chain line indicated by a symbol YP4 indicates the admittance Y4 on a complex plane. The dashed line indicated by the symbol YP6 indicates the admittance Y6 on a complex plane. A dashed line indicated by a symbol YP7 indicates the admittance Y7 on a complex plane. The vector indicated by the symbol YV1 indicates the admittance Y1 at the anti-resonance frequency AF on a complex plane. The vector indicated by the symbol YV2 indicates the admittance Y2 at the anti-resonance frequency AF on a complex plane. The vector indicated by the symbol YV3 indicates the admittance Y3 at the anti-resonance frequency AF on a complex plane. The vector indicated by the symbol YV4 indicates the admittance Y4 at the anti-resonance frequency AF on a complex plane. The vector indicated by the symbol YV6 indicates the admittance Y6 at the anti-resonance frequency AF on a complex plane. The vector indicated by the symbol YV7 indicates the admittance Y7 at the anti-resonance frequency AF on a complex plane.

  In the complex plane of the impedance shown in FIG. 21, the horizontal axis is the resistance R (real part), and the vertical axis is the reactance X (imaginary part). The solid line indicated by the symbol ZP1 indicates the impedance Z1 on a complex plane. The dashed line indicated by the symbol ZP5 indicates the impedance Z5 on a complex plane. The two-dot chain line indicated by the symbol ZP6 indicates the impedance Z6 on a complex plane. The dashed line indicated by the symbol ZP7 indicates the impedance Z7 on a complex plane. The vector indicated by the symbol ZV1 indicates the impedance Z1 at the anti-resonance frequency AF on a complex plane. The vector indicated by the symbol ZV5 indicates the impedance Z5 at the anti-resonance frequency AF on a complex plane. A vector indicated by a symbol ZV6 indicates an impedance Z6 at the anti-resonance frequency AF on a complex plane. The vector indicated by the symbol ZV7 indicates the impedance Z7 at the anti-resonance frequency AF on a complex plane.

  20 and 21, the reason why anti-resonance can be suppressed when the mounting structures 1, 2, 3, 4, and 5 of the multilayer capacitor are used will be described. In the following description, in the equivalent circuit shown in FIG. 18, a portion connected in parallel is considered by admittance on a complex plane shown in FIG. 20, and a portion connected in series is represented by an impedance on a complex plane shown in FIG. Think.

  Since the resistance R1 and the inductance L1 (impedance Z3) of the first path A1 and the resistance R2 and the inductance L2 (impedance Z4) of the second path A2 are connected in parallel, the admittance YP3 and the admittance on the complex plane of FIG. YP4 is combined with admittance YP6, and vector YV3 indicating admittance Y3 at anti-resonance frequency AF and vector YV4 indicating admittance Y4 are combined to form vector YV6 indicating admittance Y6. The admittance YP6 becomes an impedance ZP6 on the complex plane of FIG. 21, and the vector YV6 indicating the admittance Y6 at the anti-resonance frequency AF becomes a vector ZV6 indicating the impedance Z6 on the complex plane of FIG. Since the inductance L2 of the second path A2 is higher than the inductance L2 'of the second multilayer capacitor of FIG. 14, the admittance YP4 on the complex plane of FIG. 20 is different from the curve of the admittance YP4' on the complex plane of FIG. Become. As a result, the admittance YP6 on the complex plane in FIG. 20 is farther from the B axis than the admittance YP6 ′ on the complex plane in FIG. 16, and the impedance ZP6 on the complex plane in FIG. Is farther from the X-axis than the impedance ZP6 'of.

  Since the wiring inductance L3 (impedance Z5) and the parallel portions (impedance Z6) of the first and second paths A1 and A2 are connected in series, the impedance ZP5 and the impedance ZP6 on the complex plane in FIG. The vector ZV7 indicating the impedance Z5 at the anti-resonance frequency AF and the vector ZV6 indicating the impedance Z6 are synthesized to become the vector ZV7 indicating the impedance Z7. As described above, since the impedance ZP6 is away from the X-axis, even when the wiring inductance L3 exists, the impedance ZP7 on the complex plane in FIG. 21 is closer to the X-axis than the impedance ZP7 ′ on the complex plane in FIG. Leave. The impedance ZP7 is admittance YP7 on the complex plane in FIG. 20, and the vector ZV7 indicating the impedance Z7 at the anti-resonance frequency AF is a vector YV7 indicating admittance Y7 on the complex plane in FIG.

  Since the capacitance C1 (impedance Z2) of the IC3, the inductance L3 of the wiring, and the series portion (impedance Z7) of the first and second paths A1 and A2 are connected in parallel, the admittance YP2 and the admittance YP2 on the complex plane of FIG. The admittance YP7 is combined with the admittance YP1, and the vector YV2 indicating the admittance Y2 and the vector YV7 indicating the admittance Y7 at the anti-resonance frequency AF are combined into the vector YV1 indicating the admittance Y1. This admittance YP1 becomes impedance ZP1 on the complex plane of FIG. 21, and vector YV1 indicating admittance Y1 at the anti-resonance frequency AF becomes vector ZV1 indicating impedance Z1 on the complex plane of FIG.

  As described above, the admittance YP7 is further away from the B-axis than the admittance YV7 'in FIG. 16 because the impedance ZP7 is away from the X-axis. Thus, the vector YV7 indicating the admittance Y7 at the anti-resonance frequency AF is farther away from the B axis than the vector YV7 'in FIG. As a result, the vector YV1 indicating the admittance Y1 at the anti-resonance frequency AF in FIG. 20 is further away from the origin of the admittance complex plane than the vector YV1 'in FIG. Accordingly, vector ZV1 indicating impedance Z1 at anti-resonance frequency AF in FIG. 21 is closer to the origin of the complex plane of impedance than vector ZV1 'in FIG. That is, at the anti-resonance frequency AF, the level of the impedance Z1 decreases. As a result, as shown in FIG. 19, in the frequency characteristic ZF1 of the impedance Z1, the level of the impedance is reduced at the anti-resonance frequency AF, and the angle-shaped characteristic is reduced. That is, anti-resonance is suppressed. As described above, by adopting the multilayer capacitor mounting structures 1 to 5 according to the first to fifth embodiments, the capacitance of the ICs 12, 22, 32, 42, and 52 and the multilayer capacitor , 21, 31, 41, and 51 can be suppressed from anti-resonance.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications are possible. For example, the ICs 12, 22, 32, 42, 52 are mounted on the upper surfaces 10a, 20a, 30a, 40a, 50a of the wiring boards 10, 20, 30, 40, 50. 52 may be mounted on the lower surface of the wiring boards 10, 20, 30, 40, 50 and the like.

  In the first embodiment, the first and second external electrodes 11b and 11c of the multilayer capacitor 11 are configured such that the first main surface portions 11j and 11m are formed of resin electrodes to increase the resistance. However, the first main surface portion 11j is used. , 11m side may be made higher than the resistance of the second main surface portions 11k, 11n, the first main surface portions 11j, 11m may be formed by electrodes other than the resin electrodes. In the first embodiment, the resistance of both the first main surface 11j of the first external electrode 11b of the multilayer capacitor 11 and the first main surface 11m of the second external electrode 11c is increased. The resistance of one of the first main surface 11j and the first main surface 11m of the second external electrode 11c may be increased.

  In the first embodiment, the first via (via 10s) and the third via (via 10t) on the first path A1 side have the same short length, and the second via (via 10u, via 10v and via 10v) on the second path A2 side are used. The length of the fourth via (a part of the via 10w, the via 10x, and a part of the via 10t) is the same long length, and the first via and the third via on the first path A1 side are added together. Is made shorter than the total length of the second via and the fourth via on the second path A2 side to make the inductance of the second path A2 higher than the inductance of the first path A1. If the total length of the first via and the third via on the A1 side is shorter than the total length of the second via and the fourth via on the second path A2 side, the first via on the first path A1 side is determined. The via and the third via may have different lengths, or the second path A And a second via and a fourth via side may be different lengths.

  In the second to fifth embodiments, in order to make the second path A2 higher in ESL than the first path A1, in addition to the diameter of the via or the number of parallel vias, the length of the via on the second path A2 side is set to the first. Although the length of the via on the route A1 side is set to be longer than the length of the via on the first route A1 side (first via, third via), the via on the second route A2 side (second via, fourth via) ) May be substantially the same length, and the ESL of the second path A2 may be higher than the first path A1 only by the diameter of the via or the number of parallel vias.

  In the second embodiment, the diameters of the vias 20s and 20t on both sides of the first path A1 on the first main surface 21j side of the first external electrode 21b and the second external electrode 21c on the first main surface 21m side are determined by the second path A2. Although the diameter of the via is larger than the diameter of the via, the diameter of the via on one of the vias 20s and 20t may be increased.

  In the third embodiment, the number of parallel first vias (30s, 30t) on the first path A1 side (for example, two) and the number of parallel third vias (30u, 30v) are the same. The number of parallel first vias on the first path A1 side may be different from the number of parallel third vias, or only one of the first and third vias may be a parallel via. You may comprise. For example, the first via may be configured with three parallel vias, and the third via may be without parallel vias.

  In the fourth embodiment, both the vias 40s and the vias 40t on the first path A1 side are made of a material having a low conductivity (high electric resistivity) to increase the resistance on the first path A1 side. However, the resistance of the first path A1 side may be increased by forming one of the vias 40s and the via 40t on the first path A1 side with a material having low conductivity. In the fourth embodiment, conductive carbon and palladium are shown as materials having low conductivity. However, other materials may be used as long as the material has sufficiently lower conductivity than a material having high conductivity such as copper. Is also good.

1, 2, 3, 4, 5 Mounting structure of multilayer capacitor 10, 20, 30, 40, 50 Wiring board 10s, 10t, 10u, 10v, 10w, 10x via 20s, 20t, 20u, 20v, 20w, 20x via 30s , 30t, 30u, 30v, 30w, 30x, 30y, 30z vias 40s, 40t, 40u, 40v, 40w, 40x vias 50s, 50t, 50u, 50v, 50w, 50x, 50y, 50z vias 11, 21, 31, 41 , 51 multilayer capacitor 11a, 21a, 31a, 41a, 51a multilayer body 11b, 21b, 31b, 41b, 51b first external electrode 11c, 21c, 31c, 41c, 51c second external electrode 11j, 21j, 31j, 41j, 51j 1st main surface part 11k, 21k, 31k, 41k, 51k 2nd main surface part 11m 21m, 31m, 41m, 51m first main surface 11n, 21n, 31n, 41n, 51n second major surface portions 12,22,32,42,52 IC (Integrated Circuit)

Claims (8)

A wiring board having a power supply pattern and a ground pattern,
An integrated circuit mounted on the wiring board and having a power terminal and a ground terminal;
A multilayer capacitor mounted inside the wiring board and electrically connected to the power supply pattern and the ground pattern;
With
The power supply terminal of the integrated circuit is electrically connected to the power supply pattern,
The ground terminal of the integrated circuit is electrically connected to the ground pattern,
The multilayer capacitor is provided on a laminated body in which first internal electrodes and second internal electrodes are alternately laminated with a dielectric layer interposed therebetween, and provided on one end face of a pair of opposed end faces of the laminated body, A first external electrode electrically connected to the first internal electrode; and a second external electrode provided on the other of the pair of end surfaces of the laminate and electrically connected to the second internal electrode. And an external electrode,
The first external electrode is connected to an end surface along the one end surface, a first main surface along one main surface connected to one end of the one end surface, and connected to the other end of the one end surface. A second main surface portion along the other main surface,
The second external electrode has an end surface portion along the other end surface, a first main surface portion along the one main surface connected to one end portion of the other end surface, and another end portion of the other end surface. A second main surface portion along the other main surface to be connected,
The first main surface portion of the first external electrode is electrically connected to the power supply pattern via a first via formed inside the wiring board;
The second main surface portion of the first external electrode is electrically connected to the power supply pattern via a second via formed inside the wiring board;
The first main surface portion of the second external electrode is electrically connected to the ground pattern via a third via formed inside the wiring board;
The second main surface portion of the second external electrode is electrically connected to the ground pattern via a fourth via formed inside the wiring board,
A first path passing through the first via, the first main surface of the first external electrode, the first main surface of the second external electrode, and the third via between a power supply and a ground of the integrated circuit; A second path passing through the second via, the second main surface of the first external electrode, the second main surface of the second external electrode, and the fourth via is formed in parallel;
The mounting structure of a multilayer capacitor, wherein the first path has a higher equivalent series resistance than the second path, and the second path has a higher equivalent series inductance than the first path.   The first main surface portion of the first external electrode and / or the first main surface portion of the second external electrode are the second main surface portion of the first external electrode and the second main surface portion of the second external electrode. The mounting structure of the multilayer capacitor according to claim 1, wherein the mounting structure is formed of an electrode having a higher resistance value.   2. The multilayer capacitor according to claim 1, wherein the first via and / or the third via is formed using a material having a higher electrical resistivity than the second via and the fourth via. 3. Mounting structure.   The mounting structure according to claim 3, wherein the material having a high electric resistivity is conductive carbon or palladium.   The length of the first via and the third via added together is shorter than the length of the second via and the fourth via added together. 13. The mounting structure of the multilayer capacitor according to claim 1.   6. The multilayer capacitor according to claim 1, wherein the first via and / or the third via have a larger diameter than the second via and the fourth via. 7. Mounting structure.   6. The multilayer capacitor according to claim 1, wherein the first via and / or the third via includes a plurality of vias connected in parallel. 7. Construction. A plurality of vias that form the first via, and said second via, and a plurality of vias that constitute the third via, claim 7 and the fourth via is characterized in that all of substantially the same diameter 4. The mounting structure of the multilayer capacitor described in 1.

Images