TW200411874A - Method of manufacturing BGA substrate with high performance of heat dissipating structure - Google Patents

Abstract

A method for fabricating BGA substrate with high performance heat dissipating structure is provided. The BGA substrate includes a heat spreader having an upper surface and a lower surface, and each surface is defined with a central region and a peripheral region surrounding the central region. By means of electrical deposition, an upper protruding part and a lower protruding part are respectively formed on the central region, and the thickness of the heat spreader of the central region is larger than that of the peripheral region. Then, at least a first unit circuit board and second unit circuit board are respectively compressed on the upper surface and lower surface of the heat spreader, allowing openings formed on the first and second unit circuit boards to receive the upper and lower protruding parts. Thereafter, conductive layers are laminated to the first and second unit circuit boards, following by forming a plurality of blind holes through the conductive layers, allowing the heat generated by a semiconductor chip adhered to the substrate to be dissipated to the ambient via the heat spreader.

Description

200411874 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method of inserting & ^, especially two methods: to the heat sinking semiconductor package substrate structure and the core of the board with high dispersion and multiple sounds 2 (Heat Spreader) as the basis of the prior art] substrate structure and manufacturing method thereof. The booming development of the sub-industry industry ’electronic products are also gradually moving into multi-tasking. Ask, this is the direction of research and development. In order to meet the high accumulation of semiconductor packages (egrati〇η) and miniaturization (Miniaturization) packages, the number of active and passive components and printed circuit boards (Printed Circuit Boards) on which the lines are connected are gradually changing from single-layer boards. Evolved into a multi-dwelling board (Mu 11 i-1 ayer Board), confined in a limited space, using the Interlayer Connection technology to expand the available circuit area on the printed circuit & Body Circuit (Integrated Circuit) requirements. However, with the number of circuit layers and component density of printed circuit boards, the heat generated by the operation of Westgate ’s highly integrated semiconductor wafers will also increase significantly. If this heat cannot be removed in time, it will cause semi- and conductor package overheating. And seriously threaten the life of the chip. However, although the addition of a heat sink on the substrate can effectively improve the heat dissipation efficiency of the chip, the addition of a heat sink will obviously increase the volume and weight of the finished package component. Therefore, the concept of the “22,” ,,, and “0” structure is added inside the substrate. The 4th figure shows a conventional semiconductor package using a thermal conductive pin as a heat dissipation structure. As shown in the figure, the substrate 3 used in the semiconductor package mainly includes a heat sink 30 having an upper surface 300 and Lower surface 301, Aren 200411874 V. Description of the invention (2) Resin layer 3 on top of 4 heat sink 3 0 on top surface 3 0 0, a circuit layer 33 laminated on top of Xi Shiyue layer 31, a Laminated on the heat sink plate 30 to capture the tree layer 3 2. A laminated circuit on the lower resin layer 32 2 and a plurality of conductive pins 3 5 and 36 3. The political heat plate 30 is located in the middle layer of the substrate 3 structure, and is used as a heat sink for the US plate 3. The heat generated by the operation of the wafer 3 60 can be sent to the outside through the heat plate 3, and the heat plate 30 is connected to the chip. Shaped moon around the installation area ― several insulation holes 30 through the heat sink 30 3a; after the insulating resin of the lower resin layer 32 of the upper resin layer is pressed to the heat sink plate 30, two insulation holes 303a of the heat sink plate 30 are filled. The upper circuit layer 33 It is provided on the surface of the upper resin layer 3, and a plurality of wire bonding pads are provided on the upper life layer 3, so that after the upper circuit layer 3 3 is outside 1 and 37, the wire bonding pads expose the openings of the solder resist layer 37. Anti-freshness layer :: The circuit layer 34 is provided on the surface of the lower resin layer 32, and there are a plurality of solder balls on the lower circuit edge. Similarly, the lower circuit layer M is covered; Each solder ball pad is exposed to the outside for the solder ball 39 to be planted. The edge hole penetrates the upper resin I 31 and the heat sink 30, and the lower resin layer 32 makes the upper and lower circuit layers ⑽ and 3 Conduction, wherein the hole diameter of the conductive pin 35 is ^ channel + Q tr t 1 The small edge hole 3 0 3 a of the township is small, and a short circuit occurs between each conductive pin 35 and the insulating hole 3 0 3_ gap. ,, rim resin resin isolation to avoid

The plurality of thermally conductive bolts 3 6 are also penetrated through L nr ^ £ 〇〇α ^ ^ ^ L ngi resin layer 3 b heat dissipation plate 30 and the lower layer of the tree layer 3 2, and each thermally conductive bolt 3 6 is Jiqiu, Therefore, H H 丹 π, 泰, 风 # is connected to the bottom 360 of the wafer P. Therefore, the heat of the Japanese and Japanese film 360 can pass through the heat conduction 柃 q & Μ through the heat sink 30.

200411874 V. Description of the invention (3) Passed to solder ball 39. When the package is implemented, at least one semiconductor wafer 360 is first adhered to the upper circuit layer 31 with an insulating thermal conductive adhesive (not shown), so that the heat generated by the operation of the wafer 360 can be passed through the wafer 36. The thermal conductive adhesive (not shown) at the bottom of 0 is transmitted to the thermal pin 36 and then passes through the heat sink 30. The wiring pad of the upper circuit layer 31 and the chip electrode (Die E 1 ectr 〇) are borrowed. Coupling by a plurality of gold wires 38, in order to protect the wafer 360 from external electrical interference, the wafer 360 and the gold wires 38 are covered with a packaging gel, and then most of the solder balls are planted on the substrate 3 solder ball pads at the bottom to complete a semiconductor package with a heat dissipation structure on the substrate. However, the heat dissipation effect of the above-mentioned semiconductor packages that transfer heat by thermally conductive plugs is not as good as expected. The reason is that the heat dissipation method of the chip is to transfer the heat generated during the operation of the chip to the heat dissipation plate through the thermal conductive pins, and then to the outside. However, because the number of thermally conductive bolts is limited, and the thermal cross-section of each thermally conductive bolt is positively small, the heat of the chip cannot be quickly transmitted through the thermally conductive bolt under the encapsulation of the gel and the upper resin layer with little thermal conductivity To the heat sink, which causes serious heat accumulation problems and affects the performance of the chip. On the other hand, when setting the thermal plug, it is necessary to go through procedures such as drilling (Dr i 1 1 ing), copper plating, and plug holes of insulating resin, which is not only time consuming and increases the manufacturing cost. Furthermore, if the thermal plug and the insulation hole gap When the plug hole is incomplete and there are some gaps remaining, problems such as air holes (Void) and even popcorns often occur in subsequent processes. [Summary of the Invention]

17101.ptd Page 10 200411874 V. Description of the invention (4) The main purpose of the present invention is to provide a structure of a semiconductor package substrate with high heat dissipation, which can improve the heat dissipation efficiency of the chip and enable the substrate to have both electrical conduction and heat dissipation functions. method. Another object of the present invention is to provide a structure of a semiconductor package substrate with high heat dissipation and a manufacturing method thereof by reducing the steps of forming an interlayer circuit in the core area of the substrate to greatly reduce the manufacturing cost of the substrate. In order to achieve the disclosure and other purposes, the method for manufacturing a semiconductor package substrate with high heat dissipation according to the present invention is implemented according to the following steps: First, a heat sink is provided, so that the heat sink has a core area and a peripheral area defined in advance, and the periphery A plurality of first hole portions penetrating the heat sink are formed in the region, which are insulation holes for subsequent circuit insulation; a protrusion (such as an upper protrusion and / or a lower protrusion) is formed on at least one side of the core region of the heat sink. (Outer part), so that the thickness of the core region of the heat sink is greater than the thickness of the peripheral part; a first and second unit circuit board are respectively pressed on the lower surface of the heat sink, and the first and second unit circuit boards are provided with an insulating layer A patterned circuit is formed on both sides of the surface, and an opening for accommodating a protrusion is provided at a portion corresponding to the core area of the heat dissipation plate; a first, Two metal layers, the first and second metal layers are formed with a plurality of blind holes (Via) exposing the protruding portion of the heat sink; a surface of the first and second metal layers and the blind holes is covered with a metal conductive , The circuit pattern of a metal layer is formed with a circuit layer.

17101.ptd Page 11 200411874 V. Description of the invention (5) The heat sink is manufactured according to the above, and the protrusions on the two sides of the fan are respectively protruding; the plurality of boards and the second unit heat sink plate are the core circuit unit layer and the second metal level. A portion of the surface protruding portion of the circuit board covers the first, semiconductor wafer to the outside. The invention lies in that the conventional substrate is guided to the heat sink and the heat plug can provide the heat dissipation performance. Design, and the heat-conducting glue of the face-to-face thermal adhesive is passed through the problem of insufficient heat dissipation plate. [Embodiment] The hot plate is formed by a method of forming a laminated circuit board with two surface layers, a surface, and an upper surface. The high heat dissipation semiconductor for forming the second gold amount has a core region and a peripheral region for the wafer carrier package substrate junction. The structure includes a protrusion above the core region and / or a lower surface of the heat dissipation plate. First, the openings of the first and second unit circuit board sections are circuitized; an interval and an insulating layer are formed on the first and the convex surfaces, and a unit circuit corresponding to the first and second sections is formed. A metal and a second metal layer correspond to the majority of the blind holes of the heat sink; and a metal conductive layer is a cloth layer and the surface of the blind hole. The substrate structure can be connected to the protruding portion of the heat dissipation plate, and the high heat dissipation semiconductor package is quickly transferred. After using a plurality of conductors and circuit boards, the thermal cross-sectional area is limited. The operation of the wafer is transferred to the large heat dissipation area of the metal conductive layer to further strengthen the place where the heat dissipation mounting substrate is superior to the traditional substrate. The heat plug transfers the heat of the semiconductor wafer and transfers the heat to the outside. Due to the conduction, the heat generated by the projections on the substrate and the structure without the thermally conductive plug on the substrate and the bonding wafer can be transferred to the outside through the wafer back and the heat sink to improve the traditional thermally conductive plug. Heat transfer cross-sectional area effect.

ill

17101.ptd Page 12 200411874

200411874 V. Description of the invention (7) 1 0 0, so that the protruding portion 10 4 above the heat sink 10 is accommodated in the opening 11 0 of the first unit circuit board 11; similarly, the second The unit circuit board 12 is also provided at the center with an opening 1 2 0 having a shape similar to that of the core region 1 0 2 of the heat sink plate 10 to press the second unit circuit board 12 to the insulating layer 1 2 1 a. The lower surface 10 of the heat dissipation plate 10 can make the protruding portion 105 under the heat dissipation plate 10 completely accommodated in the opening 120 of the second unit circuit board 12. The aforementioned first unit circuit board 11 and the first-stage circuit board 12 may be selected from a copper-based substrate (Copper

Coated Laminate (CCL), Resin Coated Copper (RCC), or FR-4 resin, FR ~ 5 resin, Epoxy, Silicon, Polyesters, The surface of insulating materials such as glass fiber is coated with a copper foil resin layer (Copper Foi 1). At the same time, the copper foil layers located on both sides of the insulating core layer of the first unit circuit board and the second unit circuit board are subjected to processes such as lithography (Etching) and etching (Etching) to form a pattern circuit (Pattern Circuit). The circuit layers 151 and 15 are separated by an insulating layer 1 1 1 b and 1 2 1 b on the outside of the first and second unit circuit boards 1 and 12 respectively, and a plurality of the heat dissipation plates 10 protrude. The exposed holes 1 0 4 and 1 0 5 are covered with a metal conductive layer 15 'and a solder mask 17 (Solder Mask) covering the outer side of the circuit layer 1 5 1 and 1 5 2 The circuit layer 15b 152 with a plurality of exposed openings, that is, the blind holes 13o, 140 that are connected with the metal-plated conductive layer described above are connected. Wherein, the metal conductive layer 5 may be a copper-plated layer or a nickel-plated layer, but any other material having good electrical conductivity and thermal conductivity is included in the implementation range of the conductive layer of the high-heat-dissipation package substrate of the present invention.

17101.ptd Page 14 200411874 V. Description of the invention (8) To use the substrate of the present invention to win silver (Chuan ve "je; ί i: l; when sealing clothes, borrow-such as: == 9 road layer 152 (that is, Fresh ball 塾 " a " is available for ^ Since the protruding portion i 〇4 on the heat sink 1 〇 is used for semiconductor wafer i 6 〇 loading, when the semiconductor wafer i60 is bonded by the thermal conductive adhesive i6i When the circuit layer 151 of the core region 102 is reached, the heat generated by the operation of the wafer 160 can be transferred to the circuit layer 1 5 1 of the substrate 1 through the wafer, and then pass through the circuit layer 1 5 1 and the hot plate. 1 〇 and passed to the outside world, so that the substrate 1 can also achieve dispersion when electrical conduction, ^ effect, at the same time, the larger heat dissipation cross-sectional area of the heat sink 10 can further improve the heat dissipation efficiency of the substrate 1, so compared with The traditional substrate that conducts heat with conductive plugs' The high-heat-dissipation semiconductor package substrate of the present invention does have better heat-dissipating performance. Then, please refer to FIGS. 3A to 3H to describe the overall manufacturing process of the high-heat-sink multilayer printed circuit board of the present invention in detail. The high-heat-dissipation multilayer printed circuit board is used as a packaging substrate for a semiconductor wafer. The steps of the process are as follows: First, as shown in FIG. 3A, a metal plate is provided as the heat sink 10. The heat sink 10 is preferably copper, which has an upper surface of 100 and below. A surface 101 is defined by a core region 102 and a peripheral region 103 on the upper and lower surfaces 100 and 10 respectively. Secondly, as shown in FIG. 3B, the heat sink 10 is defined as a peripheral region.

17101.ptd Page 15 200411874 V. Description of the invention (9) A plurality of first hole portions 10 3a penetrating the metal plate 10 are opened in the area of 103, which are insulating holes formed to be insulated from the circuit. The part defined as the core region 102 is plated to a predetermined thickness by means of electroplating or electrodeposition, or a thicker metal plate is used as the heat sink 10 'to its peripheral region H) 3 etch, so that the thickness of the core region 10 is larger than the thickness of the peripheral region 103, so that the upper and lower surfaces of the core region i 〇2 are formed with an upper protruding portion 104 and a lower protruding portion 1 〇5. Then, as shown in FIG. 3C, a plurality of Copper Coated Lanunate (CCL) and Resin Coated

Copper (RCC) or resin copper layer is used as the material of the first unit circuit board and the second early circuit board 12. In this embodiment, a double-layer copper foil substrate is used as the material of the first unit circuit board η and the second unit circuit board 12, that is, a copper junction layer 113, 123 can be attached to the upper and lower surfaces of the -insulating resin layers η2 and 122, respectively. 'For forming a two-layer circuit pattern. , Connect, taxi: as shown in Figure 3D, on the copper layer 1 1 3, 1 2 3 of the double-layer copper box substrate, thin * to form a circuit pattern and form the first unit of electricity. ;: ': Make a complicated circuit and place it on the open, and have the same shape as the upper protruding part 104, and place it on the top of the pattern of another-double-layer copper drop substrate ΐ H: f 1 2 6 Hai copper foil substrate The upper position corresponding to the core region 102 is an opening 120 having a shape similar to that of the lower protruding portion 105. First, as shown in FIG. 3E, the first and second circuit boards U, ^ having openings u0, 120 are pressed against the upper surface 100 and lower surface 101 of the heat sink with insulating layers 11U, 121a, so that the upper surface The protrusion 104 is received

17101.ptd Page 16 200411874 V. Description of the invention GO) The first unit circuit board 1 1 is in the opening Π 0, and the lower protruding part 1 0 5 is accommodated in the opening of the second unit circuit board 1 2 1 2 0; an insulating layer 111 b, 1 2 1 b is formed on the outer side of the first and second unit circuit boards, and a first and second metal layer 1 3, 1 4 are formed. In this embodiment, the insulating layer 1 1 1 b, 1 2 1 b and the first and one metal layers 13, 1 4 may be a single-sided adhesive-backed copper foil formed of a copper pig layer and a resin layer, and bonded to the first, A conductive metal layer is formed on the two unit circuit boards U, 12 or on the surface of the insulating layer by the Bui Id up method. This is a technology familiar to the industry and need not be described here. Furthermore, as shown in FIG. 3F, the package substrate 1 is combined with the first metal layer 1 3, the insulating layer 1 1 1 b, the first unit circuit board U, the insulating layer 1 1 1 a, and the heat sink from top to bottom. 1 〇, insulation layer 1 2 1 a, second unit circuit board 1 2, insulation layer 1 2 1 b, and second metal layer 14, the packaging substrate 1 is positioned relative to the first hole portion 103a of the heat sink plate. Drill holes (Dr i 1 1 i ng) to form through holes 103b having a smaller diameter than the first hole portion 103a, and the first and second metal layers 13, 1 4 and the insulating layers 1 1 1 b, 1 2 1 b A plurality of second hole portions 130 and 140 that expose the protruding portion of the heat dissipation plate are formed. The second hole portion can be completed by mechanical drilling or laser drilling to form a blind via. Continuing, as shown in FIG. 3G, an outer surface of the first and second metal layers 1 3, 1 4 and the second hole portions 1 3 0, 1 4 0 and the through hole 1 0 3 b of the package substrate 1 is formed. Such as nickel-plated layer or copper-plated layer, etc. 1 5 and filled with insulating materials such as epoxy (Epoxy) 16 or conductive materials such as solder paste (So 1 der Paste) (not shown) 1 0 3 b. Finally, as shown in 3H, the metal conductive layer 15 on the surface of the package substrate is circuit-patterned to form circuit layers 1 5 1 and 1 5 2 and a majority is applied.

17101.ptd Page 17 200411874 V. Description of the invention (11) Opening solder resist 17 to protect the substrate. Where the circuit layer 15 exposed on the solder resist 17 is connected to the second hole portion 1 3 0, 1 4 0, it can be used as the heat sink plate protruding portion 1 4 4 and 1 5 Adhesive parts while providing high heat dissipation. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of patent applications described below, and any technology completed by others. Entities or methods that are completely the same as those defined in the patent application scope described below, or an equivalent change, will be considered to be covered by this patent application scope.

17101.ptd Page 18 200411874 Brief description of the drawings [Simplified description of the drawings] FIG. 1 is a schematic cross-sectional view of the first embodiment of the semiconductor package substrate structure with high heat dissipation of the present invention; FIG. Sectional schematic diagram of a high-heat-dissipation semiconductor package substrate package; Figures 3A to 3H are schematic diagrams of the overall manufacturing process of a high-heat-dissipation semiconductor package substrate of the present invention; and Figure 4 is a schematic diagram of a multi-layer semiconductor package substrate with thermally conductive plugs . 3 Package substrate 1 0 > 30 Upper surface of heat sink 100, 300 1 0 Lower surface 102, 202 Core area 103 Peripheral area 103a, 303a Insulation hole 103b Through hole 104 Upper protrusion 105 Lower protrusion 1 1 > 31 first unit circuit board 110 > 120 opening 111a, 121a, 111b, 121b insulating layer 112, 122 insulating resin layer 113, 123 copper foil layer 12, 32 second unit circuit board 130 ^ 140 blind hole 15 metal conductive layer 160 ^ 360 Semiconductor wafer 161 Thermal conductive adhesive 17, 37 Solder resist 18, 38 Gold wire 19, 39 Fresh ball 35 Conductive plug

17101.ptd Page 19

Claims (1)

200411874 VI. Scope of patent application 1. A method for manufacturing a semiconductor package substrate with high heat dissipation, comprising the following steps: A heat sink is provided, the heat sink has an upper surface and a lower surface, and at least one core area and an upper surface are respectively predetermined. A peripheral area, wherein the core area of the heat sink plate forms at least one protruding portion, and a plurality of first hole portions penetrating the heat sink plate are formed on the peripheral area; and at least one first unit circuit board and the second unit are laminated. The circuit board is on the upper and lower surfaces of the heat sink. The first and second unit circuit boards have openings corresponding to the core area. After the first and second unit circuit boards are joined to the heat sink, the opening The protruding portion of the heat sink is accommodated in the opening of each unit circuit board; at least one metal layer is formed on the first unit circuit board and the second unit circuit board by an insulation layer, and corresponds to the metal layer. Drilling a plurality of second hole portions outside the core region of the heat sink to expose the protruding portion; and forming a metal conductive layer on the outside of the metal layer and on the surface of the second hole portion Patterning to form a circuit layer. 2 · If the method of manufacturing a semiconductor package substrate according to item 1 of the scope of patent application, wherein the semiconductor package substrate is a multilayer printed circuit board (Mu 11 i 1 ayer Printed Circuit Board) ° 3-as described in item 1 of the scope of patent application The method for manufacturing a semiconductor package substrate, wherein the heat sink is a copper plate. 4 · The method for manufacturing a semiconductor package substrate according to item 1 of the scope of patent application, wherein a position on the package substrate corresponding to the protrusion is provided for a semiconductor crystal. 17101.ptd Page 20 200411874 VI. Scope of Patent Application Film loading. 5. The method for manufacturing a semiconductor package substrate according to item 1 of the application, wherein the thickness of the core region of the heat sink is greater than the thickness of the peripheral region. 6. The method of manufacturing a semiconductor package substrate according to item 1 of the application, wherein the first hole portion is an insulating hole. 7. The method for manufacturing a semiconductor package substrate according to claim 1, wherein the second hole portion is a blind hole (B 1 i n d V i a). 8 · If the method of manufacturing a semiconductor package substrate according to item 1 of the patent application, wherein the first and second unit circuit boards are a copper foil substrate (Copper Coated Laminate, CCL) 〇 9 · If the semiconductor of the patent application item 8 A method for manufacturing a package substrate, wherein the δ 玄 铜 # substrate is a double-layer copper foil substrate with front and back sides that have been patterned to form a circuit layer. 10 · According to the method for manufacturing a semiconductor package substrate according to item 1 of the patent application scope, wherein the first and second unit circuit boards are a Resin Coated Copper (RCC), which has an insulating resin layer and at least A copper layer laminated with the insulating resin. 1 1 · If the method of manufacturing a semiconductor package substrate according to item i of the patent application, the first and second unit circuit boards are selected from the "-4 tree", 1 grease, epoxy resin, silicon (SiHcOn) Copper foil resin layer of copper foil layer of insulating material such as Polyesters, glass fiber, etc. Among them, FR-5 Juku tree surface plating 1710] .ptd 1 page 21 200411874 6. The scope of patent application is similar. 13. The method for manufacturing a semiconductor package substrate according to item 1 of the scope of patent application, wherein the metal conductive layer is a copper plating layer. 1 4. The method for manufacturing a semiconductor package substrate according to item 1 of the scope of patent application, wherein the metal conductive layer is a nickel-plated layer. 1 5. According to the method for manufacturing a semiconductor package substrate according to item 1 of the scope of patent application, wherein the circuit layer is provided with a solder mask with a large number of openings. 1 6. A type of high heat dissipation semiconductor package substrate, including: A heat sink has an upper surface and a lower surface. At least one core region and a peripheral region are respectively scheduled on the upper and lower surfaces. At least one protrusion is formed on the core region of the heat sink, and a plurality of peripheral regions are provided on the peripheral region. A first hole portion penetrating the heat sink; at least one first and second unit circuit boards pressed on the heat sink, the first and second unit circuit boards corresponding to the core area of the heat sink An opening is provided at the position. After the first and second unit circuit boards are joined with the heat sink, the protrusions of the heat sink are accommodated in the openings of the unit circuit boards. At least one metal layer is separated by an insulation stack. Connected to the first and second unit circuit boards, the metal layer corresponding to the core area of the heat sink plate is drilled with a plurality of second hole portions to expose the protruding portion; and a portion formed on the metal The metal conductive layer outside the layer and the surface of the second hole portion is patterned to form a circuit layer. 17. The semiconductor package substrate according to item 16 of the patent application scope, wherein the 17101.ptd p. 22 200411874 6. Scope of patent application The semiconductor package substrate is a multilayer printed board. Circuit board Multi layer 1 8 · Semiconductor heat sink as copper plate. The mounting substrate 'wherein' the π. The semiconductor package substrate according to item 16 of the patent application scope, wherein the thickness of the core region of the heat sink is greater than the thickness of the peripheral region. 20 弋 Applicable to the 16th semiconductor package substrate of Shiliqiaowei: Among them, the first and second unit circuit boards are a copper junction substrate (c0ppa coated laminated) (CCL) ° 2 1 The semiconductor package substrate of Item 20, wherein the copper foil substrate is a double-layer copper foil substrate that has been patterned to form a circuit layer on both sides. 2 2. The semiconductor package substrate according to item 21 of the patent application scope, wherein the first and second unit circuit boards are a Resin Coated Copper (RCC), which has an insulating resin layer and at least A copper foil layer laminated with the insulating resin. 23. The semiconductor package substrate according to item 22 of the application, wherein the unit circuit board is a resin selected from the group consisting of FR-4 resin, FR-5 resin, epoxy, silicon, and polyester resin. (Polyesters), glass fiber, and other insulating materials such as copper foil, copper foil resin layer. 24. The semiconductor package substrate according to item 23 of the application, wherein the adhesive sheet is a Resiri Coated Copper (RCC). 17101.ptd Page 23 200411874 VI. Patent application scope 25. For the semiconductor package substrate of the 16th patent application scope, the second hole portion is a blind hole (B 1 ind V i a). 26. The semiconductor package substrate according to item 16 of the patent application scope, wherein the metal conductive layer is a copper plating layer. 27. The semiconductor package substrate according to item 16 of the patent application scope, wherein the metal conductive layer is a mineral recording layer. 28. The semiconductor package substrate according to item 16 of the patent application scope, wherein the circuit layer is provided with a solder mask (Solder Mask) with a plurality of openings. 17101.ptd Page 24