JPH033324A - Manufacture of semiconductor connector - Google Patents

Abstract

PURPOSE: To enable effectively reducing the size of a conductive material layer of a lower part on which a contact hole is to be formed, so that high level integration of a semiconductor device is enabled, by forming a contact hole by using a photoetching technique and forming an insulating film spacer on the side wall of the contact hole. CONSTITUTION: After MOSFET's 20A, 20B which are adjacent to each other interposing a source electrode 4 are formed, an insulating film 5 is formed on the whole surface and is flatened, and an etching stopper layer 6 is formed. The etching stopper layer 6 on the source electrode 4 and a part of the insulating film 5 are etched. After a contact hole 13 having a side wall 13A is formed, an insulating film 7 is formed on the whole surface, the insulating film 7 is anisotropically etched by using the etching stopper layer 6, and a spacer 7A of an insulating film is formed on the side wall 13A of the contact hole 13. After the etching stopper layer 6 is eliminated, a conductive material layer 8 for a bit line is formed on the whole surface, and a bit line 8A is electrically connected to the respective source electrodes 4 of the MOSFET's 20A, 20B by using the conducive material layer 8 for the bit line.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming a connection device for highly integrated semiconductor devices, and in particular, relates to a method for forming a connection device for highly integrated semiconductor devices, and in particular, it relates to a method for forming a connection device for highly integrated semiconductor devices. When selectively connecting the layers, a contact hole is formed by etching a part of the insulating layer formed on the top of the conductive material layer located below, and different electrodes are attached to the sidewalls of the contact hole. An insulating film spacer is formed for insulation, and then a conductive material layer to be connected is formed on the entire surface to electrically connect the respective conductive material layers to each other, thereby reducing the area of the cell. The present invention relates to a method for forming a semiconductor connection device obtained.

[Prior Art] Generally, when manufacturing a semiconductor IC, in order to connect one conductive material layer to the underlying conductive material layer, a layer is formed between the conductive material layers to insulate each of the conductive material layers. The structure is such that one upper conductive material layer is connected to a lower conductive material layer through a contact hole formed by etching a portion of the formed insulating layer.

Generally, in the area where such a contact hole is formed, for example, a diffusion region formed in a silicon substrate,
There are conductive material layers for gate electrodes, internal connection lines, etc.

At this time, in order to form a contact hole in such a part, it is necessary to use a mask for patterning the conductive material layer to be connected, a contact mask for the contact hole, and a conductive material layer formed on top of the conductive material layer to be connected. A mask patterning process using a patterning mask layer should be performed, and the arrangement of such masks is performed according to certain design rules.

In a conventional contact hole forming method, a certain portion of an insulating layer formed on a conductive material layer to be contacted is removed by photo-etching.

When manufacturing a semiconductor connection device using such a conventional contact hole forming method, each mask arrangement must be designed as described above.

For example, when manufacturing a semiconductor connection device by contacting the bit line (8A) to MOSFET (2OA and 20B) as shown in FIG. 1(A) and FIG. 1(B), MOSFET (20A and 20B) source electrode (
4) When forming the contact hole (12) in the upper part, in order to insulate the bit line (8A) and the gate electrodes (3A and 3B) from each other, place the source electrode (4) between adjacent gate electrodes. The distance a between (3A and 3B) and the contact mask C takes into account the thickness of the insulating layer (5), the minimum misalignment correction distance that may occur during the mask process, and the loss of critical value that occurs during the photoetching process. You need about the same length.

Bit like that! A leakage current may flow between the bit line (8A) and the gate electrodes (3A and 3B), or they may be short-circuited to each other, and the semiconductor device may not operate. Since the thickness of the insulating layer (5) is small, there may be a problem that the insulating layer (5) may be destroyed during operation of the device.

Further, as shown in FIG. 4(A) and FIG. 4(B), a contact hole (14) is formed in the upper part of the internal connection (9A) that connects the elements to each other to manufacture the semiconductor connection device. In this case, the line width g of the internal connection line (9A) must be larger than the contact mask dimension Cx and the length that takes into account the misalignment correction distance and critical value loss that may occur during the process, that is, Cx+2a. .

In this way, a contact hole (1
4), the width Ω of the internal connection line (9A) below the position where the contact hole (14) is formed must be larger than the width Cx of the contact hole (14). Therefore, there is a problem that the degree of integration of the device is reduced.

[Problem to be solved by the invention]

Therefore, an object of the present invention is to solve the above-mentioned problems by forming a contact hole in a part of an insulating layer formed between a lower conductive material layer and a later-formed conductive material layer to be connected. It is an object of the present invention to provide a method for forming a semiconductor connection device, in which a spacer of an insulating film between other electrodes is formed in the contact, and a conductive material layer to be connected is formed on the top of the whole.

[Means to solve the problem]

According to one feature of the method for manufacturing a semiconductor connection device according to the present invention, a step of sequentially forming a gate oxide film and a conductive material layer for a gate electrode on a silicon substrate, and a step of forming a gate oxide film and a conductive material layer for a gate electrode on a silicon substrate; Each of the electrode masks is arranged at a predetermined arrangement interval in consideration of the width of the contact mask arranged between these masks, the misalignment correction distance that may occur during the contact mask patterning process, and the critical value loss distance. forming respective gate electrodes by a gate mask patterning process of the gate oxide film and a conductive material layer for gate electrodes; forming a source electrode and forming a respective drain electrode in the silicon substrate on the other side of each of the gate electrodes, thereby forming respective MOSFETs adjacent to each other with the source electrodes interposed therebetween; A step of forming an insulating film on the surface of the entire structure and planarizing the same, a step of etching the upper part of the insulating layer, and a contact mask on the upper part of the source electrode between the gate electrodes of each of the MOSFETs. and etching a portion of the etching stop layer and the insulating layer above the source electrode using a contact mask pattern process to form a contact hole with sidewalls, thereby exposing the surface of the source electrode. forming an insulating film on the surface of the entire structure and anisotropically etching the insulating film using the etching stop layer;
forming an insulating film spacer on the sidewall of the contact hole; forming a conductive material layer for a bit line on the entire surface including the exposed source electrode after removing the etching stop layer; connect the bit lines to each of the above MOS
The method is characterized by the step of electrically connecting to the common source electrode of the FET.

According to other features of the method for manufacturing a semiconductor connection device according to the present invention, the step of forming a first insulating layer on the silicon substrate; and the step of forming a first conductive material layer for an internal connection line on the top of the first insulating layer. and arranging internal connection line masks on top of the first conductive material layer with a predetermined spacing that corresponds to the width of the contact mask that will be used later in forming the contact hole. forming an internal connection line through a mask pattern process of the first conductive material layer; forming a second insulating layer on the entire surface; and forming a part of the second insulating layer above the internal connection line. forming a contact hole with a sidewall by etching through a contact pattern process, thereby exposing the surface of the internal connection line; forming an insulating film on the entire surface; forming an insulating film spacer on the sidewall of the contact hole by anisotropic etching, and forming a second conductive material layer on the entire surface including the exposed interconnect line, thereby electrically connecting the second conductive material layer to the upper internal connection line.

According to this invention, when manufacturing a semiconductor connection device by a bit line contact process, for example, FIGS. 2 and 3 (E
) As shown in the figure, the distance between adjacent gate electrodes with respect to the lower source electrode is determined by the width Cx of the contact mask C and the misalignment correction distance (Mlsal).
igtvent tolerance) and the critical value loss, which is twice the length a', that is, the length 2a' on both sides.
An insulating film spacer is formed on the side wall of the contact hole to insulate between the bit line and the gate electrode.

This has the great effect of reducing the thickness of the insulating layer for insulating between the bit line and the gate electrode, compared to conventional methods.

In still another example, when manufacturing a semiconductor connection device by a contact process on the upper part of an internal connection line connecting elements, for example, as shown in FIGS. 5(A) and 5CB), the internal connection is When the line width g' of the line and the width Cx of the contact mask C are made approximately equal, the contact holes are connected internally by a length that takes into account the misalignment correction distance and critical value loss required during the contact mask patterning process. Even if the silicon substrate is exposed by etching the first insulating layer at the lower end of the side surface of the internal connection line outside the line, the insulating film spacer formed on the side wall of the contact hole prevents the silicon substrate and other layers formed later. The two conductive material layers are insulated from each other. And undesirable electrical connections between them can be prevented.

[Effect]

In the semiconductor connection device of the present invention, when selectively connecting one conductive material layer to other conductive material layers located above and below each other, one of the insulating layers formed on the upper part of the lower conductive material layer is A contact hole is formed by etching the contact hole, and an insulating film spacer is formed on the side wall of the contact hole for insulation from different electrodes. Then, a conductive material layer to be connected is formed on the entire surface to electrically connect the respective conductive material layers to each other.

Therefore, in a semiconductor device using this device, the electrodes can be brought closer to each other, and as a result, the area of the cell can be reduced.

〔Example〕

Hereinafter, the manufacturing process of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1A is a layout diagram of a mask layer when a bit line contact process is performed using a conventional technique.

By arranging the active mask A1, the gate electrode masks B and B', and the contact mask C according to the design regulations, a (insulating layer thickness + misalignment correction distance + critical value) is set between each mask as described in the header. A distance of loss distance M) and b (loss distance of misalignment correction distance measurer critical value) can be set.

FIG. 1(B) is a cross-sectional view taken along line y-y' in FIG. 1(A).

The structure shown in FIG. 1A is formed by each mask arrangement, and a gate oxide film (2) and a conductive material for a gate electrode (3) are formed on a silicon substrate (1), Gate oxide film (2A and 2B) and gate electrode (3A and 3B) are formed in the gate electrode mask pattern process.
form.

Then, the gate electrode (3A
and 3B) within the silicon substrate (1).
4), and in the silicon substrate (1) on the opposite side thereof, drain electrodes (4A and 4B) are formed and an insulating layer (5) is formed entirely, and MO8FETs (2OA and 20B) are formed. form.

Next, a contact hole (12) for bit line contact is formed on the upper part of the source electrode (4) by a contact mask patterning process, and a conductive material layer (B) for bit line is formed on the entire surface of the substrate. , the bit line (8A) formed by this is MOSFET (2OA and 20B) (
+) connected to the source electrode (4).

As can be seen from the above, according to the conventional technology, bit lines (8
A) MOSFET (2OA and 20
The area of the source electrode (4) of B) is equal to the distance required to align the respective masks according to the design rules as shown in FIG. 1A and the associated description, e.g. Due to this, the product must be widely demanded.

FIG. 2 is a layout diagram of a mask layer when performing a bit line contact process according to the present invention.

That is, when active mask A', gate electrode masks B and B', and contact C are arranged according to the design rules, contact mask C and gate electrode masks B and B' are arranged in the mask pattern process as shown in FIG. By only considering the resulting distance #a' (misalignment correction distance + critical value loss), it is possible to arrange the active mask A' and the contact mask C so that they substantially match each other, and the active mask A' and the contact mask C can be arranged at a distance b' that is hardly separated from each other.

Figures 3(A) to 3(E) represent the line y-y' in Figure 2.
2 is a cross-sectional view taken along the line 1, showing the manufacturing process of a semiconductor connection device in order to reduce the cell area according to the present invention.

FIG. 3(A) shows that a gate oxide film (2) and a conductive material layer (3) for a gate electrode are sequentially formed on a silicon substrate (1), and then as shown in FIG. Width C of the contact mask C for the contact hole to be formed
Gate electrode masks B and B' are arranged with a distance a' (misalignment correction distance + critical value loss) that may occur in the contact mask patterning process from x, and the gate oxide film (2) is and conductive material for gate electrode (3
) Gate oxide film (2A and 2B) and gate electrode (3A and 3B)
form.

Next, by an ion implantation process, a source electrode (4) is formed in the silicon substrate between the gate electrodes (3A and 3B), and a drain electrode (4) is formed in the silicon substrate on the other side of these electrodes.
4A and 4B), and then an insulating layer (5) is formed on the entire surface of the substrate, and this is planarized.

Thereafter, a contact hole (13) is formed by etching a part of the insulating layer (5) above the source electrode (4) in a contact mask patterning process. Then, a third (C) is formed on the side wall (13A) of this contact hole (13).
As shown in FIG. 3 and FIG. 3(D), an insulating film spacer (7A) such as an oxide film is formed, and a nitride film is deposited on the entire surface to serve as an etching stop layer for the oxide film. FIG.

Here, the insulating layer (5) is PSG (Phospho
-8ilicate-C;1ass) or B P S
G (Boro-Phospho-3ilinate
-Glass) etc.

FIG. 3(B) shows that a certain area above the source electrode (4) is etched by patterning a contact mask etching stop layer using a contact mask C as shown in FIG. 2 to form a contact hole for a bit line. The etching stop layer and the insulating layer (5) are sequentially etched to form a contact hole (1) so that the source electrode (4) is exposed.
3) is a cross-sectional view of the state in which 3) is formed.

FIG. 3(C) shows the side wall (1) of the contact hole (13).
FIG. 3A) is a cross-sectional view of the entire insulating film, for example, an oxide film is deposited to form the insulating film spacer in FIG. 3A).

FIG. 3(D) shows that the side wall (1) of the contact hole (13) is etched by an anisotropic etching process.
3A), an insulating film spacer (7A) for insulation purposes was formed.

At this time, when etching the oxide film of the insulating film, the nitride film used as the etching stop layer (6) of the oxide film is used to form an insulating film spacer (7A), and then this nitride film is used as the etching stop layer. (6) is removed.

FIG. 3(E) shows that, following FIG. 3(D), a conductive material layer (8) used for the bit line is formed on the entire surface, so that the bit line (8A) is connected to MOSFET (2OA and 20B). ) is a cross-sectional view showing a state in which the source electrodes (4) are electrically connected.

As described above, according to the present invention, the bit line (8A) M
The area at the source electrode of the OSFETs (20a and 20B) is determined by the spacing between the gate electrode masks B and B' and the contact mask C arranged to form the respective gate electrodes (3A and 3B). It can be arranged as shown in Figure 2, and can be more compact than the conventional structure.

That is, in the conventional structure shown in FIG. 1(B), the bit line (
Since the insulating layer (5) for insulating 8A) from the gate electrode (3A and 3B) must have a certain thickness, it is necessary to make the area of the source electrode large. be.

On the other hand, in the structure according to the present invention shown in FIG. 3E, the thickness of the insulating layer (5) for insulating between the bit line (8A) and the gate electrodes (3A and 3B) is omitted, and and a contact hole (13) for insulation between them.
An insulating film spacer (7A) is formed on the inner surface (13A) of the insulating film spacer (7A). Therefore, the area of the source electrode can be reduced to that extent.

In the case of a semiconductor connection device having a bit line contact process as described above, the area of the source electrode required in the conventional method and the method according to the present invention is compared as follows.

That is, looking at FIG. 1A, which shows the layout of the mask layer manufactured during the contact process using the conventional technique, the distance a between the contact mask C and the gate electrode masks B and 8 is as follows: a-bit line and gate The thickness of the insulating layer (5) for insulation between the electrodes (0.3 μm), the critical loss (0.1 μm) of the error alignment correction distance (0.2 μm), and the mask C and The distance between active mask A is: b - misalignment correction distance (0,2 μm) + critical value loss (0,2 μm)
1 μm)=0.3 μm.

On the other hand, looking at FIG. 2, which shows the layout of the mask layer produced when contact is stopped according to the present invention, the distance a' between the contact mask C and the gate electrode masks B and B' is: a' - Misalignment correction distance ( 0.2 μm) + critical value loss (0
, 1 μm) = 0.3 μm, and the distance b between contact mask C and active mask A'
' becomes zero.

Therefore, the size of the bit line contact mask C is
For example, when 0.8 μrn
0.3μm×2)−2.8μm2, and the area S of the source electrode required by this invention is S' = (0.8μm+0.3μmX2)
8 .mu.m)=1.12 .mu.m2, so according to the present invention, the area is only about 40% that of the conventional method.

Next, a description will be given of an example in which the technique according to the present invention is applied when manufacturing a semiconductor connection device by forming a contact hole above an internal connection line that connects elements to each other.

FIG. 4A is a layout diagram of a mask layer when a contact mask patterning process is performed on a first conductive material layer for internal connection, according to an embodiment of the prior art.

In order to arrange the contact mask C on the internal connection line mask D, the conduction for internal connection is determined by the length a, which is the sum of the minimum misalignment correction distance and the length that takes into account the loss of critical value that occurs during the process. The width g of the material layer (18) must be larger than the width Cx of the contact mask C. Therefore, as a result, the area of the mask D for internal connection must be made larger than that of the contact mask C.

FIG. 4(B) is a sectional view taken along line y-y' in FIG. 4(A).

A first insulating layer (15) is formed on the silicon substrate (10), and a first conductive material layer (9) for an internal connection line is formed on the first insulating layer (15).
is formed to form an internal connection line mask (
D), an internal connection line (9A) having a length g is formed by the above-described mask patterning process of the first conductive material layer.

Next, a second insulating layer (16) is formed on the entire surface, and then a contact mask pattern process is performed using a contact mask C so that a part of the surface of the internal connection line (9A) is exposed. A contact hole (14) is formed by etching a portion of the second insulating layer (16) above the internal connection line (9A). Then, as shown by the dotted line on the entire surface, the second conductive material layer (1
9).

As can be seen in FIG. 4(A) and FIG. 4(B), according to the prior art, the first conductive material layer (9A) for the internal connection line
Since the width g of the contact hole (14) must be larger than necessary, the degree of integration of the device is reduced.

FIG. 5A shows the width g' of the interconnected mask D' and the width Cx of the contact mask C by applying the technique according to the present invention to reduce the area of the device according to the prior art shown in FIG. 4A.
FIG. 3 is a layout diagram showing a state in which masks are arranged so as to match each other.

FIG. 5(B) is a cross-sectional view taken along line y-y' in FIG. 5(A).

A first insulating layer (15) is formed on the silicon substrate (10), and a first conductive material layer (18) for an internal connection line is formed thereon. Next, as shown in FIG. 5A, the first
The conductive material layer (18) is formed with an internal connection line (18A) having a length of about g' through a mask pattern process.

Then, a second insulating layer (16) is formed on the entire surface, and the internal connection line (16) is formed by a contact mask pattern process.
A contact hole (14) is formed by etching the second insulating layer (16) above the internal connection line (18A) so as to expose a part of the surface of the internal connection line (18A).

Furthermore, after forming an insulating film (17) such as an oxide film on the entire surface, the side wall (14A) of the contact hole (14) is
The above insulating film (
17) is anisotropically etched. Thereafter, a second conductive material layer (19) to be connected is formed on the entire surface as indicated by dotted lines.

At this time, during the contact mask patterning process, the contact hole (14) itself has an internal connection line (
It is more desirable if the contact hole (18A) is formed to match the width g' of the contact hole (18A).
14) Even if the first insulating layer (15) at the lower end of the -side surface of the internal connection line (18A) is etched and the silicon substrate (10) is exposed due to a mistake in the contact mask arrangement during formation, the present invention , the interconnection line and the second conductive material layer (18A and 19) are insulated from the silicon substrate (10) by an insulating film spacer (<17A).

〔Effect of the invention〕

As described above, according to the present invention, after a contact hole is formed using photoetching technology, an insulating film spacer is formed on the side wall of the contact hole, thereby increasing the size of the lower conductive material layer where a contact is to be formed. The size can be effectively reduced, and as a result, high integration of semiconductor devices becomes possible.

[Brief explanation of the drawing]

Figure 1 (A) is a layout diagram of a mask layer when performing a bit line contact process according to the prior art;
) is a cross-sectional view taken along the line y-y' in FIG. Figures 3(A) to 3(E) are respectively
A sectional view taken along the line y-y' in the figure to show the manufacturing process of an embodiment according to the present invention, FIG. FIG. 4(B) is a cross-sectional view taken along the line y-y' of FIG. 4(A), and FIG. 5(A) is a layout diagram of the mask layer according to the present invention. As an example, FIG. 5(B) is a layout diagram of a mask layer when performing a contact process on the upper part of an internal connection line, and FIG. 5(B) shows a state cut along line y-y' in FIG. FIG. A A'...Active mask, B, B'...
・Gate electrode mask, C...contact mask, DI
D'... Internal connection line mask, 1.10... Silicon substrate, 2A, 2B... Gate oxide film, 3A, 3B...
・Gate electrode, 4...Source electrode, 4A, 4B...
Drain electrode, 5.15.16... Insulating layer, first and second insulating layer, 6... Etching stop layer, 7.17...
・Oxide film, 7A, 17A... Insulating film spacer, 8...
・Bit line conductive material layer, 8A...Bit line, 9,1
8... Conductive material layer for internal connection, 19... Second conductive material layer, 9A, 18A... Internal connection line.

Claims (1)

[Scope of Claims] 1. Each gate oxide film and gate electrode formed on a silicon substrate, a source electrode formed in the silicon substrate between the respective gate electrodes, and other than the respective gate electrodes. each MOSFET has respective drain electrodes formed in a silicon substrate on a side surface, the source electrodes are arranged adjacent to each other with the source electrodes interposed therebetween, and the entire structure is covered with an insulating layer. In the method of manufacturing a semiconductor connection device for electrically connecting a bit line to the source electrode of the MOSFET through a contact hole by etching a part of the insulating layer above the source electrode of the MOSFET, a process of sequentially forming a gate oxide film and a conductive material layer for a gate electrode, and forming gate electrode masks on top of the conductive material layer for a gate electrode, and forming a width of a contact mask arranged between these masks and a contact mask. The gate oxide film and the conductive material layer for the gate electrode are arranged at a predetermined arrangement interval in consideration of misalignment correction distances and critical value loss distances that may occur during the mask patterning process, and the gate oxide film and the conductive material layer for the gate electrode are each formed by the gate mask patterning process. forming gate electrodes in the silicon substrate between the respective gate electrodes formed at predetermined spacing, and forming source electrodes in the silicon substrate on the other side of the respective gate electrodes; forming respective drain electrodes thereby forming respective adjacent MOSFETs with the source electrode therebetween; forming an insulating film on the entire structure surface;
a step of planarizing the insulating layer; a step of etching the upper part of the insulating layer; arranging a contact mask above the source electrode between the gate electrodes of each of the MOSFETs, and etching an etching stop layer above the source electrode. and etching a part of the insulating layer by a contact mask patterning process to form a contact hole with sidewalls, thereby exposing the surface of the source electrode, and forming an insulating film on the surface of the entire structure. and anisotropically etching the insulating film using the etching stop layer,
forming an insulating spacer on the sidewall of the contact hole; and forming a conductive material layer for a bit line on the entire surface including the exposed source electrode after removing the etch stop layer; The bit lines are connected to the respective MOS
1. A method for manufacturing a semiconductor connection device, comprising the step of electrically connecting to a source electrode of an FET. 2. The insulating layer is made of PSG (Phospho-Silic).
ate-Glass) or BPSG (Borp-Pho
2. The method of manufacturing a semiconductor connection device according to claim 1, wherein the semiconductor connection device is made of spho-Silicate-G1ass). 3. The method of manufacturing a semiconductor connection device according to claim 1, wherein the insulating film for the insulating film spacer is an oxide film. 4. The method of manufacturing a semiconductor connection device according to claim 1, wherein the etching stop layer is a nitride film. 5. A first insulating layer formed on an upper part of the silicon substrate, an internal connecting line formed in a part of the upper part of the first insulating layer, and a second insulating layer formed on the silicon substrate and the internal connecting line. etching a part of the second insulating layer on the internal connection line to expose a part of the internal connection line to form a contact hole, and forming a second insulating layer on the internal connection line through the contact hole. A method of manufacturing a semiconductor connection device for connecting conductive material layers includes the steps of: forming a first insulating layer on top of a silicon substrate; and forming a first conductive material layer for an internal connection line on top of the first insulating layer. forming an internal connection line mask on the first conductive material layer at a predetermined spacing that corresponds to a width of a contact mask that will later be used when forming a contact hole;
forming an internal connection line through a mask patterning process of the first conductive material layer; forming a second insulating layer on the entire surface; and contacting a part of the second insulating layer above the internal connection line. etching through a patterning process to form a contact hole with a sidewall, thereby exposing the surface of the internal connection line; forming an insulating film on the entire surface; and forming an insulating film on the entire surface. forming a second conductive material layer on the entire surface including the exposed interconnection line, thereby forming a second conductive material layer on a sidewall of the contact hole; A method for manufacturing a semiconductor connection device, comprising the step of electrically connecting a material layer to an upper internal connection line. 6. The method of manufacturing a semiconductor connection device according to claim 5, wherein the insulating film for the insulating film spacer is an oxide film.