JPS6273741A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6273741A
JPS6273741A JP21530485A JP21530485A JPS6273741A JP S6273741 A JPS6273741 A JP S6273741A JP 21530485 A JP21530485 A JP 21530485A JP 21530485 A JP21530485 A JP 21530485A JP S6273741 A JPS6273741 A JP S6273741A
Authority
JP
Japan
Prior art keywords
insulating film
hole
film
photoresist
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21530485A
Other languages
Japanese (ja)
Inventor
Masamichi Murase
村瀬 眞道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21530485A priority Critical patent/JPS6273741A/en
Publication of JPS6273741A publication Critical patent/JPS6273741A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To microminiaturize a contact or through hole by opening an insulating film by photolithography, then uniformly bonding the second insulating film having different etching rate on the entire substrate, and then removing by anisotropically etching only the flat portion of the second film. CONSTITUTION:An insulating film I103 is formed on a conductor wiring 102 on a silicon substrate 101, the surface is coated with a photoresist, and a hole is opened. Then, with the photoresist 104 as a mask the film I103 is opened by anisotropically etching without side etching. Then, after the photoresist 104 is removed, an insulating film II106 is accumulated in a uniform thickness by different etching rate from the film I103 on the entire substrate. Subsequently, only the portion adhered to the surface substantially parallel to the substrate 101 of the film II106 is removed by anisotropically etching. Thus, the insulator II106 remains on the side 105 of the hole of the insulator I103, and a fine through hole can be formed beyond the limit of the photolithography by ultraviolet ray exposure.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に微細なコン
タクト及びスルーホールの開孔工程を有する集積回路装
置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an integrated circuit device having a step of forming fine contacts and through holes.

〔従来の技術〕[Conventional technology]

従来、集積回路装置の半導体領域上の絶縁膜のコンタク
ト及び配線上の絶縁膜のスルーホールは、例えば第3図
(al 、 (b)にスルーホールの場合を示すように
、シリコン基板301上の導体配線302上の絶縁膜3
03にフォトレジスト304全塗り紫外線露光音用いた
フォトリソグラフィによ!+ 305の開孔部が開孔さ
れていた。
Conventionally, contacts in an insulating film on a semiconductor region of an integrated circuit device and through holes in an insulating film on wiring have been formed on a silicon substrate 301, for example, as shown in FIGS. Insulating film 3 on conductor wiring 302
In 03, photoresist 304 was completely coated by photolithography using ultraviolet exposure sound! +305 holes were drilled.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した集積回路装置のコンタクト及びスルーホールの
開孔方法では現在の紫外光を用いたフォトリソグラフィ
を使用する為、光の波長により露光できる寸法に限界が
あり、微細なコンタクト及びスルーホール(例えば2μ
m0以下)全歩留り良く開孔することは不可能であると
いう欠点があった。その為、集積度の高く、かつ配線密
度の亮い集積回路装置全作ることが困難であるという欠
点があった2゜ 本発明は上述した従来方法の欠点を除去し、紫外線露光
によるフォトリングラフィの限界を超え几微細なコンタ
クト、又はスルーホール金容易に、かつ高歩留りで形成
できる半導体装置の製造方法全提供すること金目的とす
る。
The method for forming contacts and through holes in integrated circuit devices described above uses current photolithography using ultraviolet light, so there is a limit to the dimensions that can be exposed depending on the wavelength of the light.
There was a drawback that it was impossible to form holes with a good overall yield (m0 or less). Therefore, there was a drawback that it was difficult to fabricate an integrated circuit device with a high degree of integration and high wiring density.2 The present invention eliminates the drawbacks of the above-mentioned conventional method, and uses photophosphorography using ultraviolet light exposure. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can easily form fine contacts or through-holes that exceed the limits of semiconductor devices and with a high yield.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、−導電型を有する半
導体基板の一主面上に設けられ念異なる半導体領域上の
絶縁膜もしくは導体配線上の絶縁膜にフォトリソグラフ
ィを用いて開孔する工程と、前記開孔部を含み基板全体
に前記絶縁膜とはエツチングレートの異なる第2の絶縁
膜全均一に形成する工程と、前記第2の絶縁膜の平坦部
のみを異方性エツチングにより除去する工程とを含んで
構成される。
The method for manufacturing a semiconductor device of the present invention includes - a step of forming holes using photolithography in an insulating film on a different semiconductor region provided on one principal surface of a semiconductor substrate having a conductivity type or on an insulating film on a conductor wiring; and a step of uniformly forming a second insulating film having an etching rate different from the insulating film over the entire substrate including the opening, and removing only the flat part of the second insulating film by anisotropic etching. The process includes the steps of:

〔実施例〕〔Example〕

次に、本発明について図面全参照して説明する。 Next, the present invention will be explained with reference to all the drawings.

第1図(al〜(d)は本発明の第1の実施例を説明す
るために工程順に示した断面図である。第1の実施例で
は配線上の絶縁膜に微細スルーホールを形成する方法に
適用した例につき説明する。
Figures 1 (al to d) are cross-sectional views shown in the order of steps to explain the first embodiment of the present invention. In the first embodiment, fine through holes are formed in the insulating film on the wiring. An example applied to the method will be explained.

ます、第1図(a+に示すように、シリコン基板101
上の導体配線102上に絶縁膜1103t−設ける。
First, as shown in FIG. 1 (a+), the silicon substrate 101
An insulating film 1103t- is provided on the upper conductor wiring 102.

次いで表面にフォトレジスト’6塗布し開孔を設ける。Next, photoresist '6 is applied to the surface and openings are formed.

次に、第1図(′b)に示すように、フォトレジスト1
04 ′1にマスクとして異方性エツチングを施し、サ
イドエツチングのないように絶縁膜11031CIJ孔
する。しかるときは絶縁膜工103の開孔部側面105
はシリコン基板101に対して、はぼ垂直となる。
Next, as shown in FIG. 1('b), the photoresist 1
04'1 is subjected to anisotropic etching using a mask, and the insulating film 11031CIJ hole is formed so as to avoid side etching. In such a case, the side surface 105 of the opening of the insulating film 103
is almost perpendicular to the silicon substrate 101.

次に、第1図(C1に示すように、フォトレジスト10
4を除去した後、基板全面に減圧CVD(LPCVD 
)  等のカバレッジの非常によい膜であり、絶縁膜■
103とはエツチングレートの異なる絶縁膜n1Ofl
均一な厚さで堆積する。
Next, as shown in FIG. 1 (C1), a photoresist 10
After removing 4, low pressure CVD (LPCVD) is applied to the entire surface of the substrate.
), it is a film with very good coverage, and is an insulating film.
An insulating film n1Ofl having a different etching rate from 103.
Deposit with uniform thickness.

次に、第1図fdlに示すように、絶縁膜II 106
のうち、シリコン基板101とほぼ平行な面に付着し九
部分のみを、リアクティブ拳イオンやエツチング(RI
E )  等の異方性エツチングによυ除去する。いわ
ゆるエッチパック法を用いる。その結果、絶縁物■10
3の開孔部側面105には絶縁物■106が残っており
、こうして紫外線露光によるフォトリソグラフィの限界
奮起えて、微細なスルーホールを作成することができる
Next, as shown in FIG.
Of these, only the nine portions attached to the surface substantially parallel to the silicon substrate 101 are etched using reactive fist ions or etching (RI).
υ is removed by anisotropic etching such as E). A so-called etch pack method is used. As a result, insulator ■10
An insulator 106 remains on the side surface 105 of the opening 3, and thus a fine through hole can be created by pushing the limits of photolithography using ultraviolet light exposure.

第2図fat〜(elは本発明の第2の実施例全説明す
るために工程順に示した断面図である。第2の実施例で
は配線上のテーパー付微細スルーホール金形成する方法
に適用した例につき説明する。
Figure 2 fat~(el is a cross-sectional view shown in the order of steps to fully explain the second embodiment of the present invention.The second embodiment is applied to a method of forming tapered fine through-hole metal on wiring. An example will be explained below.

まず、第2図fatに示すように、シリコン基板201
上の導体配線202上に絶縁膜I 203、そしてその
上に絶縁膜Iとエツチングレートの異なる絶縁膜lI2
04e設ける。次いでフォトリソグラフィ技術により絶
縁膜■に開孔部を有するフォトレジスト205を形成す
る。
First, as shown in FIG.
An insulating film I 203 is formed on the upper conductor wiring 202, and an insulating film lI2 having an etching rate different from that of the insulating film I is formed thereon.
04e will be provided. Next, a photoresist 205 having an opening is formed in the insulating film (1) by photolithography.

次に、第2図(b)に示すように、フォ) IJソグラ
フィにより絶縁膜204のみをエツチングし開孔する。
Next, as shown in FIG. 2(b), only the insulating film 204 is etched by IJ lithography to form a hole.

この際絶縁膜■204の開孔部側面206にはテーパー
が付くようにエツチング金貸う。
At this time, etching money is applied so that the side surface 206 of the opening of the insulating film 204 is tapered.

次に、第2図(C1に示すように、第1の実施例と同様
にして、絶縁膜I 203 k異方性エッチングにより
サイドエノチングのないように開孔する。しかるときは
絶縁膜1203の開孔部側面207はシリコン基板20
1に対しほぼ垂直となる。
Next, as shown in FIG. 2 (C1), holes are formed in the insulating film 1203 by anisotropic etching without side etching in the same manner as in the first embodiment. The side surface 207 of the opening is located on the silicon substrate 20.
It is almost perpendicular to 1.

次に、第2図Fdlに示すように、フォトレジスト20
5を除去した後、基板表面に: LPGVD  等の方
法によりカバレッヂの非常によい膜であり、絶縁膜I、
絶縁膜■とはエツチングレートの異なる絶縁膜llI2
08f:均一な厚さで堆積する。
Next, as shown in FIG. 2 Fdl, a photoresist 20
After removing 5, a film with very good coverage is formed on the substrate surface by a method such as LPGVD, and the insulating film I
An insulating film llI2 with a different etching rate from the insulating film ■
08f: Deposited with uniform thickness.

次に、第2図(61に示すように、絶縁膜■208のう
ち、シリコン基板201とほぼ平行な面に付着した部分
のみをRIE等の異方性エツチングにより除去する。し
かるときは絶縁物I2O3の開孔部側面207には絶縁
物■ 208が残ったままであり、紫外線露光によるフ
ォトリングラフィの限界を超えて微細な、そしてかつテ
ーパーもつい友スルーホール金形成することができる。
Next, as shown in FIG. 2 (61), only the portion of the insulating film 208 attached to the surface substantially parallel to the silicon substrate 201 is removed by anisotropic etching such as RIE. The insulating material 208 remains on the side surface 207 of the I2O3 opening, and it is possible to form a fine through-hole gold that is fine and tapered beyond the limits of photolithography using ultraviolet exposure.

その為、第2導体配線等をその上にかぶせたときスルー
ホール端部での段切れ減少も期待できる。
Therefore, when the second conductor wiring or the like is placed over it, it can be expected that the breakage at the end of the through hole will be reduced.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明はフォトリソグラフなる絶縁
物を均一に付着する。その後、異方性エツチングにより
後者の絶縁物のみをエッチバックし、コンタクト又はス
ルーホールの側面のみに後者の絶縁物を残すようにする
ことにより、紫外線露光によるフォトリソグラフィの限
界を超えた微細なコンタクト、又はスルーホールを容易
にかつ、高歩留りで形成出来るという効果がある。
As explained above, the present invention uniformly deposits an insulator using photolithography. Then, by etching back only the latter insulator using anisotropic etching, leaving the latter insulator only on the sides of the contact or through hole, we can create fine contacts that exceed the limits of photolithography using ultraviolet exposure. , or through-holes can be formed easily and with high yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al〜(dlは本発明の第1の実施例を説明す
るために工程順に示した断面図、第2図tai〜fel
は本発明の第2の実施例全説明するために工程順に示し
た断面図、第3図(al 、 (b)は従来法全説明す
るために工程順に示した断面図である。 101 、201 、301・・・・・・シリコン基板
、102,20ス302・・・・・導体配線、 103
,203・・・・・・絶縁膜I、303・・・・・・絶
縁膜、104,205,304・・・・・・フォトレジ
スト、106,204・・・・・・絶縁膜工、105,
207・・・:・・絶縁膜■の開孔部側面、206・・
・・・絶縁膜1■の開孔部側面、305・・・・・開孔
部、208・・・・・絶縁膜L209・・・・・・絶縁
膜lの開孔部側面。 代理人 弁理士  内 原   晋 殆1 ゾ 第2ソ1 2θ/ごと刈憩のt甲…則顔 7.グ
Figure 1 (al~(dl) is a sectional view shown in the order of steps to explain the first embodiment of the present invention, Figure 2 (tai~fel)
101, 201 are cross-sectional views shown in the order of steps to fully explain the second embodiment of the present invention, and FIGS. 3A and 3B are cross-sectional views shown in the order of steps to fully explain the conventional method. , 301... Silicon substrate, 102, 20 302... Conductor wiring, 103
, 203... Insulating film I, 303... Insulating film, 104, 205, 304... Photoresist, 106, 204... Insulating film processing, 105 ,
207...:... Side surface of the opening of the insulating film ■, 206...
. . . Side surface of opening of insulating film 1■, 305 . . . Opening, 208 . . . Insulating film L209 . Agent Patent Attorney Susumu Uchihara 1 Zo 2 So 1 2θ/Goto Kari Iki no T A… Norikao 7. Group

Claims (1)

【特許請求の範囲】[Claims] 一導電型を有する半導体基板の一主面上に設けられた異
なる半導体領域上の絶縁膜もしくは導体配線上の絶縁膜
にフォトリソグラフィにより開孔を行う第1の工程と、
前記開孔部を含み基板全体に前記絶縁膜とはエッチング
レートの異なる第2の絶縁膜を形成する第2の工程と、
前記第2の絶縁膜の平坦部のみを異方性エッチングによ
り除去する第3の工程とを含むことを特徴とする半導体
装置の製造方法。
A first step of forming a hole by photolithography in an insulating film on a different semiconductor region or an insulating film on a conductor wiring provided on one main surface of a semiconductor substrate having one conductivity type;
a second step of forming a second insulating film having a different etching rate from the insulating film over the entire substrate including the opening;
and a third step of removing only the flat portion of the second insulating film by anisotropic etching.
JP21530485A 1985-09-27 1985-09-27 Manufacture of semiconductor device Pending JPS6273741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21530485A JPS6273741A (en) 1985-09-27 1985-09-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21530485A JPS6273741A (en) 1985-09-27 1985-09-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6273741A true JPS6273741A (en) 1987-04-04

Family

ID=16670101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21530485A Pending JPS6273741A (en) 1985-09-27 1985-09-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6273741A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH033324A (en) * 1989-05-13 1991-01-09 Hyundai Electron Ind Co Ltd Manufacture of semiconductor connector
JPH04267543A (en) * 1991-02-22 1992-09-24 Nec Corp Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH033324A (en) * 1989-05-13 1991-01-09 Hyundai Electron Ind Co Ltd Manufacture of semiconductor connector
JPH04267543A (en) * 1991-02-22 1992-09-24 Nec Corp Semiconductor device and manufacture thereof

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