KR100367489B1 - Method for forming fine contact hole in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a fine contact hole in a semiconductor device is provided to increase processing margins and to prevent short by using spacers having two-step structure. CONSTITUTION: A BPSG layer(27) and a silicon layer(28) are sequentially formed on a semiconductor substrate(21) having a transistor. The first groove is formed by selectively etching the silicon layer(28) and the BPSG layer(27). A silicon spacer(32) is formed at both sidewalls of the first groove. The second groove is formed by etching the BPSG layer(27) exposed by the silicon spacer(30). An oxide layer is formed on the resultant structure. An oxide spacer(32) is formed at both sidewalls of the second groove and a contact hole(29") is simultaneously formed by etching the exposed oxide layer and BPSG layer.

Description

Method of forming fine contact hole in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine contact hole in a semiconductor device. In particular, a silicon spacer is formed at an upper end of a contact hole, and a spacer having a double structure in which an oxide spacer is formed at a lower end of the contact hole is formed to miss the contact hole from a predetermined position. Even if the alignment occurs, the present invention relates to a method for forming a fine contact hole in a semiconductor device that can stably solve the lead connection avoiding contact with the subsequently deposited silicon lead.

In general, as semiconductor devices are gradually developed into ultra-high integration trends, wiring and contact holes are difficult to form. In particular, the formation of contact holes becomes more difficult than the formation of wiring, because when forming a contact hole, the position of the contact hole must be avoided without overlapping with the wiring provided in the adjacent portion, and at the same time, it is formed on the source and drain regions of the semiconductor substrate. to be.

A conventional method for forming a contact hole will be described with reference to the accompanying drawings.

1A and 1B are diagrams showing a state in which contact holes are formed using oxide film spacers according to the related art.

As the degree of integration of the memory device is increased to 256 M or more, the size of the contact hole becomes larger than the distance between the electrodes located adjacent to each other, thereby causing a problem of connecting to the subsequently deposited bit line or silicon for the charge storage electrode. As shown in the figure, after the silicon wiring 2 is formed on the semiconductor substrate 1, the interlayer oxide film 3 is formed and the interlayer oxide film 3 is etched, and then on both sidewalls of the etched insulating film. The contact hole 5 is formed by forming the oxide film spacer 4.

In the conventional method for forming a contact hole as described above, when the contact hole 5 deviates from a point where the contact hole 5 is to be formed, as shown in FIG. 1B, a silicon wiring ( 2) is covered with the interlayer oxide film 3, and on the other side, the oxide spacer 4 is thinned in the section where the adjacent silicon wiring 2 is exposed, so that the bit line or charge storage electrode and the silicon wiring 2 which are subsequently deposited are formed. There is a problem that is connected to cause a malfunction of the semiconductor device.

Therefore, in order to solve the above problem, the contact hole is formed by forming a spacer having a two-stage structure in which a silicon spacer is formed at the upper end of the contact hole and an oxide spacer is formed at the lower end of the contact hole when forming the contact hole. It is an object of the present invention to provide a method for forming a fine contact hole in a semiconductor device that can solve a problem of contacting a silicon conductor wire which is subsequently deposited even if it deviates from it.

The present invention for achieving the above object is to form a planarized first insulating film and a silicon layer on the semiconductor substrate,

Forming a first groove by etching a portion of the silicon layer and the first insulating layer by a photolithography process using a contact mask;

Forming a silicon spacer on a sidewall of the first groove;

Etching the first insulating film exposed by the silicon spacers to form a second groove;

Forming a second insulating film on the entire structure;

And etching the exposed first and second insulating films to form a second insulating film spacer on the sidewall of the second groove and to form a contact hole for exposing the semiconductor substrate.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2F are diagrams illustrating a process of forming a fine contact hole in a semiconductor device according to the present invention.

First, the field oxide film 22, the gate oxide film 23, the gate electrode 25, the oxide spacer 26 on the sidewalls of the gate electrode, and the source / drain regions 24 are formed on the silicon substrate 21 to insulate the devices. To form. (See also FIG. 2A)

Next, an interlayer oxide film 27 is formed on the entire structure, for example, BPSG (Boro Phospho Silicate Glass) film is formed, and then planarized by a heat treatment process, and then on the interlayer oxide film 27. Phosphorus (P) doped first silicon layer 28 is formed. (See also part 2B)

Next, the first silicon layer 28 and the interlayer oxide layer 27 are partially etched by a photolithography process using a contact hole forming mask (not shown) to form a first groove 29 having a predetermined depth. A second silicon layer is formed on the entire upper portion and then etched back to form a second silicon spacer 30 on sidewalls of the etched first silicon layer 18 and the interlayer oxide layer 27. In this case, a silicon layer doped with phosphorus (P) or an undoped silicon layer may be used as the second silicon layer. (See also 2C)

Here, in the drawing shown in FIG. 2C, the contact hole (referring to the first groove 29 in the drawing) is missed from the predetermined position in order to emphasize the problem in the case of forming the contact hole according to the conventional technique for convenience. An example of an aligned case is shown.

Next, the exposed interlayer oxide layer 27 is etched to form a second groove 29 ′ deeper than the first groove 29, and then an oxide layer 31 having excellent step coverage. On top of the entire surface. (See also 2D)

Next, the oxide film 31 is etched back to form an oxide film spacer 32 on the sidewall of the second groove 29 ′. At this time, the interlayer oxide layer 27 positioned below the second groove 29 'is also etched to form a contact hole 29 "through which the source / drain region 24 is exposed.

Next, after the doped third silicon layer 33 and the tungsten silicide layer 34 are deposited on the entire structure, the tungsten silicide layer 34 and the second layer are formed by a photolithography process using a bit line mask (not shown). The silicon layer 33 and the first silicon layer 28 are etched to form bit lines. (See also 2F.)

In this case, after forming the second silicon spacer 30 as described above, the contact hole (29 ″ in FIG. 2E) is etched to expose the upper surface of the silicon substrate 1 by etching the exposed interlayer oxide layer 27. A second groove 29 ′ that is not formed, the oxide film 31 is deposited on the entire surface, and the oxide film 31 is etched back, but overetched to form an oxide film on the lower end of the second silicon spacer 30. The spacer 32 is formed and the contact hole 29 "is formed.

Another embodiment of the present invention is as follows.

After forming the second silicon spacer 30, the exposed interlayer oxide layer 27 is etched to form a contact hole 29 ″ through which the silicon substrate 1 is exposed.

Next, an oxide film 31 is deposited on the entire surface including the contact hole 29 ″, and the oxide film spacer 32 is etched back to cover the lower end portion of the second silicon spacer 30. Form.

Therefore, by forming the second silicon spacer 30 and the oxide film spacer 32 in a two-stage structure as described above, it is possible to prevent a short circuit between devices due to contact hole misalignment and to improve a contact etch margin.

In the above-described embodiments of the present invention, when the bit lines are formed between the gate electrodes formed on the semiconductor substrate, the overall process steps for forming the contact holes have been described, but the contact hole formation according to the present invention as described above. The method is not limited to forming the bit line electrodes, and the same method can be used to form the charge storage electrode contact holes that bypass the gate electrode and the bit line. (See FIG. 3, 28 ': silicon layer, 29 ": contact hole, 30': silicon spacer, 32 ': oxide film spacer).

As described above, in the method for forming a fine contact hole of a semiconductor device according to the present invention, a silicon spacer is formed at an upper end of a contact hole, and a spacer having a two-stage structure in which an oxide spacer is positioned at a lower end of a contact hole. As a result, even if a misalignment deviates from a predetermined position where a contact hole is to be formed, a short circuit due to subsequent contact with a silicon conductor that is continuously deposited can be prevented, and the margin of manufacturing process due to contact hole formation is greatly increased. You can.

1A and 1B are diagrams showing a state in which contact holes are formed using oxide film spacers according to the related art.

2A through 2F illustrate a process for forming a bitline contact hole in accordance with the techniques of the present invention.

3 is a view showing a state in which a charge storage electrode contact hole is formed according to the method of the present invention.

〈Name of code for main part of the drawings〉

1, 21: semiconductor substrate 2: silicon wiring

3, 27: interlayer oxide film 4, 26, 32: oxide film spacer

5, 29, 29 ', 29 ": contact hole 22: field oxide film

23 gate oxide film 24 source / drain regions

25 gate electrode 27 BPSG oxide film

28: first silicon layer 30: second silicon spacer

31 oxide film 33 third silicon layer

34: tungsten silicide layer

Claims (8)

Forming a planarized first insulating film and a silicon layer on the semiconductor substrate; Forming a first groove by etching a portion of the silicon layer and the first insulating layer by a photolithography process using a contact mask; Forming a silicon spacer on a sidewall of the first groove; Etching the first insulating film exposed by the silicon spacers to form a second groove; Forming a second insulating film on the entire structure; And etching the exposed first and second insulating films to form a second insulating film spacer on the sidewall of the second groove and to form a contact hole for exposing the semiconductor substrate. Fine contact hole formation method. The method of claim 1 And forming the first insulating film as a BPSG oxide film. The method of claim 1, The silicon layer is a fine contact hole forming method of the semiconductor device, characterized in that the doped with phosphorus. The method of claim 1 And forming the contact hole in the bit line or the charge storage electrode contact process. Forming a planarized first insulating film and a silicon layer on the semiconductor substrate; Forming a groove by etching a portion of the silicon layer and the first insulating layer by a photolithography process using a contact mask; Forming a silicon spacer on the sidewall of the groove; Etching the first insulating film exposed by the silicon spacers to form a contact hole; And forming a second insulating film spacer at a lower end of the silicon spacer in the contact hole. The method of claim 5 And forming the first insulating film as a BPSG oxide film. The method of claim 5 The silicon layer is a fine contact hole forming method of the semiconductor device, characterized in that the doped with phosphorus. The method of claim 5, And forming the contact hole in the bit line or the charge storage electrode contact process.