JPS6054789B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6054789B2 JPS6054789B2 JP14989580A JP14989580A JPS6054789B2 JP S6054789 B2 JPS6054789 B2 JP S6054789B2 JP 14989580 A JP14989580 A JP 14989580A JP 14989580 A JP14989580 A JP 14989580A JP S6054789 B2 JPS6054789 B2 JP S6054789B2
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- resistance layer
- layer
- semiconductor device
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置に係り、特に著しく抵抗値の異な
る抵抗層を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having resistance layers having significantly different resistance values.
従来、例えば第１図ａ、ｂに示すような半導体装置にお
いて、Ｎ゛型拡散層１よりＡｌ配線２に電流（電子）が
流れる場合、ｘ＝０の部分に電流が集区することはよく
知られている（ＩＢＭＪ、Ｒｅｓ。Ｄｅｖｅｌｏｐ、１
２（１９６８）Ｐ、２４２）。ここで、３はＰ型シリコ
ン基板、４はＳｉＱ、膜である。このような現象が生じ
る原因は、基本的には拡散層１の有する抵抗（層抵抗）
とＡｌ配線２の有する抵抗の比が極めて大きい（１び〜
１０’倍）ことに由来している。Conventionally, in a semiconductor device as shown in FIGS. 1a and 1b, for example, when current (electrons) flows from the N-type diffusion layer 1 to the Al wiring 2, the current often concentrates in the area where x=0. Known (IBMJ, Res. Develop, 1
2 (1968) P, 242). Here, 3 is a P-type silicon substrate, and 4 is a SiQ film. The cause of this phenomenon is basically the resistance (layer resistance) of the diffusion layer 1.
and the resistance of the Al wiring 2 is extremely large (1 and 2).
10' times).
すなわち、電流は拡散層１よりＮ配線２を流れる方がよ
り流れやすいことによるものである。That is, this is because current flows more easily through the N wiring 2 than through the diffusion layer 1.
周知のように過度の電流集中が生じると、これにより配
線を構成している原子が吹き流される現象いわゆるエレ
クトロマイグレーション（Ｅｌｅｃｔｒｏｍｉｇｒａｔ
ｉｏｎ）を引き起こす。As is well known, when excessive current concentration occurs, the atoms that make up the wiring are blown away, a phenomenon called electromigration.
ion).
このエレクトロマイグレーションが起こると、エレクト
ロンの風下には吹きだまりが生じ、逆にエレクトロンの
風上では原子がなくなり欠損部（Ｖｏｉｄ）を生じ、つ
いには断線してしまう。ところで、上記電流集中の度合
はコンタクト５の大きさＷにほとんど依存しないで、主
としてＬに依存するが、その集中する度合は極めて鋭い
。When this electromigration occurs, a snowdrift occurs on the leeward side of the electron, and conversely, atoms disappear on the upwind side of the electron, creating a void, which eventually leads to a disconnection. Incidentally, the degree of current concentration hardly depends on the size W of the contact 5, but mainly depends on L, but the degree of current concentration is extremely sharp.
従つて、Ｌを大きくして電流集中の度合を低減しようと
するとより多くの面積が必要となり、経済的に不都合を
生じる。この発明は上記実情に鑑みてなされたもので、
その目的は、著しく抵抗層の異なる抵抗層間の接触面に
生じる電流集中を防止し、エレクトロマイグレーション
の発生を防止することのできる経済的な半導体装置を提
供することにある。Therefore, if an attempt is made to reduce the degree of current concentration by increasing L, a larger area is required, which is economically disadvantageous. This invention was made in view of the above circumstances.
The purpose is to provide an economical semiconductor device that can significantly prevent current concentration occurring at the contact surface between different resistance layers and prevent electromigration from occurring.
以下、図面を参照してこの発明の一実施例を説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
前述のように、電流集中を生じる基本的な原因は、金属
層の抵抗値が拡散層のそれに比べて低いこと、さらに補
足すれば第１図ａで示したｘ＝０の点より金属層までの
抵抗が最も小さいことによる。従つて、上記問題の解決
のためには、ｘ＝０に於ける抵抗を高くして、過度の電
流集中を防止する必要がある。そのためには、ｘ＝０を
含む領域に追加の抵抗層を設定することで充分であり、
それにより電流の分流が可能となる。理想的にはｘ＝０
の個所からの抵抗値が金属層との接触面で同一となるよ
うに設定するのが望ましいが、現実的な製造工程として
は困難である。従つて、最も容易であり、かつ効果の期
待できる方法は、第２図Ａ，ｂに示すように、Ｎ＋型拡
散層１１とＡ１配線層１２との間の一部にｘ＝０の部分
を覆うようにして追加抵抗層１３を加え、集中する電流
を２分割することである。工程の繁雑さを厭わなければ
、さらに追加の抵抗層を加えることで分割を細かくし、
理想的な状態に近づけることが可能である。従つて、電
流の集中を防止でき、エレクトロマイグレーションの発
生がなくなり断線等の事故がなくなる。第３図ａ−ｃは
上記構造の半導体装置の製造方法を示すものである。As mentioned above, the basic cause of current concentration is that the resistance value of the metal layer is lower than that of the diffusion layer. This is due to the fact that the resistance is the smallest. Therefore, in order to solve the above problem, it is necessary to increase the resistance at x=0 to prevent excessive current concentration. For that purpose, it is sufficient to set an additional resistance layer in the region containing x=0,
This allows current to be shunted. Ideally x=0
Although it is desirable to set the resistance value from the point to be the same at the contact surface with the metal layer, this is difficult as a practical manufacturing process. Therefore, the easiest and most effective method is to form a part where x=0 between the N+ type diffusion layer 11 and the A1 wiring layer 12, as shown in FIGS. 2A and 2B. An additional resistive layer 13 is added to cover it, and the concentrated current is divided into two. If you don't mind the complexity of the process, you can make the division finer by adding an additional resistance layer.
It is possible to approach the ideal state. Therefore, current concentration can be prevented, electromigration will not occur, and accidents such as wire breakage will be eliminated. 3a to 3c show a method of manufacturing a semiconductor device having the above structure.
ここではＮチャンネル形シリコン ゲートＭＯＳ（Ｍｅ
ｔａｌＯｘｉｄｅＳｅｍｉｃＯｎｄｕｃｔＯｒ）構造を
例にとつて説明する。まず、第３図ａに示すようにＰ型
シリコン基板（結晶方位：（１００））１４上に膜厚１
μｍ程度のフィールド酸化膜１５を選択的に形成し、活
性領域と非活性領域とを分離する。次に、熱処理を行い
膜厚１０００Ａのゲート酸化膜１６を成長させ、さらに
このゲート酸化膜１６上に多結晶シリコン層１７を積層
する。そして、ＰＥＰ（写真蝕刻工程）によりゲート領
域を形成すると共に、Ｎ型不純物例えばＡｓ（砒素）の
拡散によリソース、ドレイン領域等となるＮ＋型拡散層
１１を形成する。次に第３図ｂに示すように、ＣＶＤ（
ＣｈｅｍｉｃａｌＶａｐＯｕｒ′ＤｅｐｓｉｔｉＯｎ）
法により膜厚１ｐｍ程度のＳｉＯ２膜１８を形成し、Ｐ
ＥＰによりコンタクト・ホールの穴開けを行う。しかる
後、多結晶シリコン層を４０００Ａ程度積層し、ＰＥＰ
により電流の集中する個所に対応して追加抵抗層１３を
形成する。最後に、第３図ｃに示すように、に配線層１
２を積層し、所定の配線パターンにパターニングした後
、保護膜１９を形成し、取出し用電極を形成して全工程
を完了する。尚、上記実施例においては、抵抗値の異な
る高抵抗層及び低抵抗層の例として、Ｎ＋型拡散層１１
とＡｌ配線層１２の場合について説明したが、これに限
定するものではなく、例えば多結晶シリコン層とＡｌ配
線層間のように著しく抵抗値の異なるものの間において
も一般的に適用可能である。Here, an N-channel silicon gate MOS (Me
The structure will be explained by taking the structure (talOxideSemiconductOr) as an example. First, as shown in FIG. 3a, a film with a thickness of 1
A field oxide film 15 with a thickness of about .mu.m is selectively formed to separate active regions and non-active regions. Next, a heat treatment is performed to grow a gate oxide film 16 with a thickness of 1000 Å, and a polycrystalline silicon layer 17 is further laminated on this gate oxide film 16. Then, a gate region is formed by PEP (photo-etching process), and an N+ type diffusion layer 11, which will become a resource, a drain region, etc., is formed by diffusion of an N-type impurity, for example, As (arsenic). Next, as shown in Figure 3b, CVD (
ChemicalVapOur'DepsiOn)
A SiO2 film 18 with a thickness of about 1 pm is formed by
Drill a contact hole using EP. After that, a polycrystalline silicon layer of about 4000A is laminated, and PEP
Additional resistance layers 13 are formed corresponding to locations where current is concentrated. Finally, as shown in Figure 3c, the wiring layer 1 is
2 are laminated and patterned into a predetermined wiring pattern, a protective film 19 is formed, and an extraction electrode is formed to complete the entire process. In the above embodiment, the N+ type diffusion layer 11 is an example of the high resistance layer and the low resistance layer having different resistance values.
Although the case of the Al wiring layer 12 has been described, the present invention is not limited thereto, and is generally applicable to materials having significantly different resistance values, such as between a polycrystalline silicon layer and an Al wiring layer, for example.
以上説明したようにこの発明によれば、著しく抵抗値の
異なる２つの抵抗層の間において、電流の集中する個所
を覆うように追加の抵抗層を設け・る構成としたので、
電流集中を防止し、エレクトロマイグレーションの発生
を防止することのできる経済的な半導体装置を提供でき
る。As explained above, according to the present invention, an additional resistance layer is provided between two resistance layers having significantly different resistance values so as to cover the area where current is concentrated.
It is possible to provide an economical semiconductor device that can prevent current concentration and electromigration.
第１図Ａ，ｂは従来の半導体装置の構成を示す・もので
、ａは断面図、ｂは平面図、第２図Ａ，ｂはこの発明の
一実施例に係る半導体装置の構成を示すもので、ａは断
面図、ｂは平面図、第３図ａ〜ｃは上記装置の製造工程
を示す断面図てある。
１１・・・・・・Ｎ＋型拡散層、１２・・・・・・Ａ１
配線層、１７３・・・・・・追加抵抗層。1A and 1B show the structure of a conventional semiconductor device, where a is a cross-sectional view and b is a plan view, and FIGS. 2A and 2B show the structure of a semiconductor device according to an embodiment of the present invention. 3A is a sectional view, FIG. 3B is a plan view, and FIGS. 3A to 3C are sectional views showing the manufacturing process of the above device. 11...N+ type diffusion layer, 12...A1
Wiring layer, 173...Additional resistance layer.
Claims (1)
た第１の抵抗層と、この第１の抵抗層とは抵抗値が異な
り、かつこの第１の抵抗層に接触する接触部及び電流の
集中する個所に対応した非接触部を有する第２の抵抗層
と、この第２の抵抗層の非接触部に対応して設けられた
第３の抵抗層とを具備したことを特徴とする半導体装置
。 ２ 前記第３の抵抗層を多結晶シリコンで形成したこと
を特徴とする特許請求の範囲第１項記載の半導体装置。 ３ 前記第２の抵抗層は前記第１の抵抗層より低い抵抗
値を有することを特徴とする特許請求の範囲第１項記載
の半導体装置。[Claims] 1. A semiconductor substrate of one conductivity type, a first resistance layer provided on the main surface of this substrate, and a first resistance layer having different resistance values, and a second resistance layer having a contact portion that comes in contact with the current and a non-contact portion corresponding to a location where current is concentrated, and a third resistance layer provided corresponding to the non-contact portion of the second resistance layer. A semiconductor device characterized by comprising: 2. The semiconductor device according to claim 1, wherein the third resistance layer is made of polycrystalline silicon. 3. The semiconductor device according to claim 1, wherein the second resistance layer has a lower resistance value than the first resistance layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14989580A JPS6054789B2 (en) | 1980-10-25 | 1980-10-25 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14989580A JPS6054789B2 (en) | 1980-10-25 | 1980-10-25 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5773961A JPS5773961A (en) | 1982-05-08 |
| JPS6054789B2 true JPS6054789B2 (en) | 1985-12-02 |
Family
ID=15484959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14989580A Expired JPS6054789B2 (en) | 1980-10-25 | 1980-10-25 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6054789B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0277152A (en) * | 1988-06-01 | 1990-03-16 | Nec Corp | Semiconductor integrated circuit device |
| JP2594719B2 (en) * | 1991-07-19 | 1997-03-26 | 日本電気株式会社 | Semiconductor device |
-
1980
- 1980-10-25 JP JP14989580A patent/JPS6054789B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5773961A (en) | 1982-05-08 |
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