JPS6367752A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6367752A JPS6367752A JP21312186A JP21312186A JPS6367752A JP S6367752 A JPS6367752 A JP S6367752A JP 21312186 A JP21312186 A JP 21312186A JP 21312186 A JP21312186 A JP 21312186A JP S6367752 A JPS6367752 A JP S6367752A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bonding
- molybdenum silicide
- psg
- silicon dioxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 22
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims abstract description 16
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 16
- 239000011574 phosphorus Substances 0.000 claims abstract description 16
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 11
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- 230000002093 peripheral effect Effects 0.000 claims 1
- 230000007423 decrease Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000006866 deterioration Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 150000003017 phosphorus Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/0518—Molybdenum [Mo] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Abstract
Description
【発明の詳細な説明】
ｒ音量 ！−ｒピ■圧し等肝）
本発明は半導体装置に係り、特に半導体素子上のボンデ
ィングパッドの構造に関するものである。[Detailed description of the invention] r Volume! TECHNICAL FIELD The present invention relates to a semiconductor device, and particularly to the structure of a bonding pad on a semiconductor element.
従来、この種の半導体装置は、そのボンディングパッド
部分の断面および平面図をそれぞれ第３図、第４図に示
すように、回路素子が組み込まれたシリコン基板１の上
にフィールド酸化膜（Ｓｉ（ｈ ）２およびリンを含有
する二酸化硅素膜（以下、ＰＳＧ膜と称す）５を順次形
成したうえ、とのＰＳＧ膜５上に蒸着などによりアルミ
ニウム（以下、Ａｔと記す）膜６を形成する。そして、
これをパターニングした後、絶縁保護膜７を被着してそ
のＡＬ膜６上のボンディング部のみを開孔させることに
よシ、この開孔されたＡｔ膜６をボンディングパッドと
して金（Ａｕ）などのリード線（図示せず）にてポンデ
ィングするものとなってはる。なお、同図中、７ｍは絶
縁保護膜７に設けられた開孔部である。Conventionally, this type of semiconductor device has a field oxide film (Si( h) A silicon dioxide film (hereinafter referred to as PSG film) 5 containing 2 and phosphorus is sequentially formed, and an aluminum (hereinafter referred to as At) film 6 is formed on the PSG film 5 by vapor deposition or the like. and,
After patterning this, an insulating protective film 7 is deposited and holes are formed only on the bonding part on the AL film 6, and the opened At film 6 is used as a bonding pad using gold (Au, etc.). The lead wire (not shown) is used for bonding. In addition, in the same figure, 7m is an opening provided in the insulating protective film 7.
しかし、従来の半導体装置は以上のような構造を有して
いるので、ＰＳＧ膜５中の不純物特にリンのＡｔ膜６中
への拡散が起こシ易く、このリンの影響による初期ボン
ディング性の低下、あるいは金−Ａ４合金層の早期劣化
１侵入した水分とリンが反応するととＫよシ発生するリ
ン酸がＡｔを腐食させる耐温性不良現象などを引き起こ
すという問題点があった。However, since the conventional semiconductor device has the above structure, impurities in the PSG film 5, especially phosphorus, are likely to diffuse into the At film 6, and the initial bonding performance is deteriorated due to the influence of this phosphorus. , or early deterioration of the gold-A4 alloy layer 1. When phosphorus reacts with invading moisture, phosphoric acid generated from K causes a phenomenon of poor temperature resistance that corrodes At.
本発明は上記のような問題点を解消するためになされた
もので、その目的は、ボンディングパッドにＡｊを用い
る際にそのＡｔ膜へのリンの拡散を抑制することにより
、信頼性を向上させた半導体装置を提供することにある
。The present invention was made to solve the above-mentioned problems, and its purpose is to improve reliability by suppressing the diffusion of phosphorus into the At film when Aj is used for the bonding pad. The object of the present invention is to provide a semiconductor device with improved performance.
本発明に係る半導体装置は、シリコン基板上に形成され
たフィールド酸化膜の表面にポリシリコン膜およびモリ
ブデンシリサイド膜を設置し、このポリシリコン膜シよ
びモリブデンシリサイド膜の上にリンを含有する二酸化
硅素膜を設置して、この二酸化硅素膜のボンディング部
のみをエッチングにより除去して開孔部を設け、前記モ
リブデンシリサイド膜上にＡｔ膜を設置してそのＡｔ膜
のボンディングパッド部の周囲をエッチングにより除去
したうえ、この人を膜の周囲部を絶縁保護膜にて被覆さ
せて該Ａｊ膜と前記二酸化硅素膜を分離するようにした
ものである。In the semiconductor device according to the present invention, a polysilicon film and a molybdenum silicide film are provided on the surface of a field oxide film formed on a silicon substrate, and silicon dioxide containing phosphorus is provided on the polysilicon film and the molybdenum silicide film. A film is installed, and only the bonding part of this silicon dioxide film is removed by etching to form an opening, an At film is installed on the molybdenum silicide film, and the area around the bonding pad part of the At film is etched. In addition to removing the silicon dioxide film, the periphery of the film was covered with an insulating protective film to separate the Aj film from the silicon dioxide film.
本発明においては、ボンディングパッド部のＡｔ膜の下
にポリシリコン族およびモリブデンシリサイド膜を設け
、この人を膜の周囲のリンを含有する二酸化硅素膜つま
ｊ５ＰＳＧ膜を除去することによシ、前記Ａｔ膜とＰＳ
Ｇ膜は分離されて接触することがなくなｐ、ＰＳＧ膜中
のリンのＡｔ膜への拡散を防ぐことができる。In the present invention, a polysilicon group and molybdenum silicide film is provided under the At film in the bonding pad portion, and the phosphorus-containing silicon dioxide film and the PSG film surrounding the film are removed. At film and PS
The G film is separated and does not come into contact with each other, which prevents phosphorus in the PSG film from diffusing into the At film.
以下、本発明を図面に示す実施例に基づいて詳細に説明
する。Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.
第１図は本発明の一実施例による半導体装置のボンディ
ングパッド部分の概略断面図で、第２図はその平面図で
ある。この実施例では、シリコン基板１上に形成された
フィールド酸化膜２の表面にポリシリコンＪ［３および
モリブデンシリサイド膜４を形成し、このモリブデンシ
リサイド膜４の上にＰＳＧＳｂＯ２成する。そして、と
のＰＳＧＳｂＯ２ンディング部のみをエッチングにより
除去して開孔部５ａ を施したうえ、この開孔部５ａを
含むＰＳＧＳｂＯ２にＡｔ膜６を被着する。次いで、と
のＡ／！、ｌＪ６を所定の形状にパターニングしてその
ボンディング部の外周部およびそれに対応するモリブデ
ンシリサイド膜４．ポリシリコン膜３０部分をエッチン
グにより除去した後、その上に絶縁保護膜Ｔを被着して
、この膜７のボンディングパッドとなる部分を開孔させ
ることによシ、第１図に示すように、Ａｔ膜６の周囲部
を絶縁保護膜７にて被覆せしめて該Ａｔ膜６とＰＳＧＳ
ｂＯ２分離するようにしたものである。なお、図中、同
一符号は同一または相当部分を示している。FIG. 1 is a schematic sectional view of a bonding pad portion of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view thereof. In this embodiment, polysilicon J[3 and molybdenum silicide film 4 are formed on the surface of field oxide film 2 formed on silicon substrate 1, and PSGSbO2 is formed on molybdenum silicide film 4. Then, only the PSGSbO2 binding portions are removed by etching to form an opening 5a, and an At film 6 is deposited on the PSGSbO2 including this opening 5a. Next, A/! , lJ6 is patterned into a predetermined shape, and the outer periphery of the bonding portion and the corresponding molybdenum silicide film 4. After removing the polysilicon film 30 portion by etching, an insulating protective film T is deposited thereon, and holes are opened in the portions of this film 7 that will become bonding pads, as shown in FIG. , the periphery of the At film 6 is covered with an insulating protective film 7, and the At film 6 and PSGS
It is designed to separate bO2. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
このように上記実施例によると、Ａｔ膜６の下地処理と
してフィールド酸化膜２との中間に、ＡｔＨ！Ｘ６と同
等の外周を有するポリシリコン膜３およびモリブデンシ
リサイド膜４を設け、ＰＳＧＳｂＯ２ンディングパッド
としての）１膜６の下には形成することなく、そのボン
ディングパッドの周囲をエツチングにて除去することに
より、Ａｔ膜６とｐｓａｇ５とが分離して接触すること
はなくなる。As described above, according to the above embodiment, AtH! By providing a polysilicon film 3 and a molybdenum silicide film 4 having an outer circumference equivalent to that of X6, and removing the area around the bonding pad by etching without forming it under the film 6 (which serves as a PSGSbO2 bonding pad). , the At film 6 and psag 5 are no longer separated and come into contact with each other.
これによって、ＰＳＧ膜５中のリンのＡｔ膜６中への拡
散がなくな）、そのリンの影響による初期ボンディング
性の低下を防止できるとともに、膜の界面より侵入した
水分とＰＳＧ膜５中のリンとの反応を防止することがで
きる。さらに１ポンディング部の金−Ａｔ金属間化合物
層の劣化現象を促進するリンの拡散を防ぐことができる
など、長期的信頼性の向上がはかれる利点を奏する。This eliminates diffusion of phosphorus in the PSG film 5 into the At film 6), prevents deterioration of initial bonding properties due to the influence of phosphorus, and prevents moisture intruding from the interface of the film and the PSG film 5. Reaction with phosphorus can be prevented. Furthermore, it is possible to prevent the diffusion of phosphorus, which promotes the deterioration of the gold-At intermetallic compound layer in the first bonding part, and has the advantage of improving long-term reliability.
〔発明の効果〕
以上のように本発明によれば、ボンディングパッドの構
造を、ＡｔＭの下にポリシリコン膜とモリブデンシリサ
イド膜を設け、その人り膜の周囲のＰＳＧ膜を除去して
該Ａｔ膜とＰＳＧ膜が接触しないように構成したので、
ボンディング性の向上が計れるとともに、金−ＡＬ接合
部の早期劣化を防ぐととができ、これによって、半導体
素子の長期信頼性を確保することが可能となる。[Effects of the Invention] As described above, according to the present invention, the bonding pad structure is formed by providing a polysilicon film and a molybdenum silicide film under the AtM film, and removing the PSG film around the AtM film. Since the structure was configured so that the membrane and PSG membrane did not come into contact with each other,
In addition to improving bonding properties, it is possible to prevent early deterioration of the gold-AL bond, thereby ensuring long-term reliability of the semiconductor element.
第１図は本発明の一実施例による半導体装置のボンディ
ングパッド部を示す要部断面図、第２図は第１図の平面
図、第３図は従来の半導体装置のボンディングパッド部
の要部断面図、第４図は第３図の平面図である。
１ｅ・・・シリコン基Ｌ２−・・・フィールド醗化膜、
３・・・・ポリシリコン膜、４−・・・モリブデンシリ
サイド膜、５・・−・ＰＳＧ膜、５ａ ・・・・開孔部
、６・・・・アルミニウム（ＡＬ）Ｋ ７・・・・絶
縁保護族、７凰・・・・開孔部。FIG. 1 is a sectional view of a main part showing a bonding pad section of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view of FIG. 1, and FIG. 3 is a main part of a bonding pad section of a conventional semiconductor device. The sectional view, FIG. 4, is a plan view of FIG. 3. 1e...Silicon base L2-...Field oxide film,
3... Polysilicon film, 4-... Molybdenum silicide film, 5... PSG film, 5a... Opening part, 6... Aluminum (AL) K 7... Insulation protection group, 7 凰...opening part.
Claims (1)
体装置において、シリコン基板上に形成されたフィール
ド酸化膜の表面にポリシリコン膜およびモリブデンシリ
サイド膜を設置し、このポリシリコン膜およびモリブデ
ンシリサイド膜の上にリンを含有する二酸化硅素膜を設
置して、この二酸化硅素膜のボンディング部のみをエッ
チングにより除去して開孔部を設け、前記モリブデンシ
リサイド膜上にアルミニウム膜を設置してそのアルミニ
ウム膜のボンディングパッド部の周囲をエッチングによ
り除去したうえ、このアルミニウム膜の周囲部を絶縁保
護膜にて被覆させて該アルミニウム膜と前記二酸化硅素
膜を分離するようにしたことを特徴とする半導体装置。In a semiconductor device that uses an aluminum film as a bonding pad, a polysilicon film and a molybdenum silicide film are provided on the surface of a field oxide film formed on a silicon substrate, and phosphorus is contained on the polysilicon film and molybdenum silicide film. A silicon dioxide film is installed, and only the bonding part of this silicon dioxide film is removed by etching to create an opening. An aluminum film is installed on the molybdenum silicide film, and the area around the bonding pad part of the aluminum film is 1. A semiconductor device characterized in that the aluminum film is removed by etching and the peripheral portion of the aluminum film is covered with an insulating protective film to separate the aluminum film and the silicon dioxide film.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21312186A JPS6367752A (en) | 1986-09-09 | 1986-09-09 | Semiconductor device |
| US07/094,645 US4824801A (en) | 1986-09-09 | 1987-09-09 | Method of manufacturing aluminum bonding pad with PSG coating |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21312186A JPS6367752A (en) | 1986-09-09 | 1986-09-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6367752A true JPS6367752A (en) | 1988-03-26 |
Family
ID=16633921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21312186A Pending JPS6367752A (en) | 1986-09-09 | 1986-09-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6367752A (en) |
-
1986
- 1986-09-09 JP JP21312186A patent/JPS6367752A/en active Pending
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