JPS5937576B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5937576B2 JPS5937576B2 JP4765876A JP4765876A JPS5937576B2 JP S5937576 B2 JPS5937576 B2 JP S5937576B2 JP 4765876 A JP4765876 A JP 4765876A JP 4765876 A JP4765876 A JP 4765876A JP S5937576 B2 JPS5937576 B2 JP S5937576B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- thermal oxide
- oxide film
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 本発明は半導体装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor device.
たとえば集積回路（工Ｃ）等の半導体装置では、電極お
よび配線層が形成されたその表面に、表面保護安定化の
目的で第２層目のパッシベーション膜が形成される。For example, in a semiconductor device such as an integrated circuit (C), a second layer of passivation film is formed on the surface on which electrodes and wiring layers are formed for the purpose of surface protection and stabilization.
そして、このパッシベーション膜には写真蝕刻法等を用
いる孔開けによつてボンディングパッドと称する配線層
の一部表面が露出したところが形成され、前記ボンディ
ングパッドにおけるボンダビリテイおよび耐腐食性を良
好にするため、パッシベーション膜に形成された孔の周
辺部を被つて前記ボンディングパッド上に金（Ａｕ）層
を形成するようにすることが考えられる。ただこの場合
、アルミニウム（Ａｌ）等で形成された配線層と金（Ａ
ｕ）層とは接着性が良好でないことから、順次スパッタ
リング方法等で形成するタンタル（Ｔａ）層および白金
（ｐｔ）層等を介在させることが必要である。このよう
に形成されたボンディングパッド上には、外部端子と接
続するため、やはり金（Ａｕ）からなるワイヤがボンデ
ィングされるが、この際、前記ボンディングパッドにか
なり大きな荷重が加えられる。Then, in this passivation film, a part of the surface of the wiring layer called a bonding pad is formed by drilling using a photolithography method or the like, and in order to improve the bondability and corrosion resistance of the bonding pad, It is conceivable to form a gold (Au) layer on the bonding pad so as to cover the periphery of the hole formed in the passivation film. However, in this case, the wiring layer formed of aluminum (Al) etc. and the gold (A
Since the adhesion to layer u) is not good, it is necessary to interpose a tantalum (Ta) layer, a platinum (pt) layer, etc. which are sequentially formed by a sputtering method or the like. A wire made of gold (Au) is also bonded onto the bonding pad thus formed in order to connect it to an external terminal, but at this time, a fairly large load is applied to the bonding pad.
そしてこの荷重＆Ａパッドの一部の下に存在するパッシ
ベーション膜の下地層となつているアルミニウム（Ａｌ
）の配線層が軟らかいので、このパッシベーション膜に
曲げの歪みを生じさせる。このパッシベーション膜は、
一般にはＣＶＤ（ＣｈｅｍｉｃａｌＶａｐｏｕｒＤｅｐ
ｏｓｉｔｉｏｎ）方法、スパッタリング方法等で形成さ
れるシリコン酸イＵ漢、燐シリケートガラス層のような
堆積層であるため、硬度は大であるが上述の如き曲げの
歪みに対して破壊しやすいものである。The aluminum (Al
) is soft, causing bending distortion in this passivation film. This passivation film is
Generally, CVD (Chemical Vapor Dep)
Because it is a deposited layer such as a silicon oxide film or a phosphorous silicate glass layer formed by a method such as a sintering method or a sputtering method, it has high hardness but is easily destroyed by bending distortion as described above. be.
したがつてボンディングの際このパッシベーション膜に
割れが生ずる場合が往々にしてある。このように割れが
生じたパッシベーション膜は外気中の水分等を遮蔽する
ことができず、電極および配線層の腐食等をもたらす原
因となつていた。Therefore, cracks often occur in this passivation film during bonding. The passivation film with such cracks could not shield moisture from the outside air, causing corrosion of the electrodes and wiring layers.
本発明の目的は、ワイヤボンディングもしくはフェイス
ダウンボンディングの際に、堆積絶縁膜に割れが生じな
いような構成にした半導体装置を提供することにある。
この目的を達成するための本発明の構成は、半導体基体
主面上に形成された熱酸化膜と、その熱酸化膜上に形成
された第１の配線層と、その熱酸化膜上に形成され、上
記第１の配線層の一部を露出するようなコンタクト穴を
有する堆積絶縁膜と、上記コンタクト穴内において上記
第１の配線層に接し、かつ上記堆積絶縁膜上に延在する
第２の配線層と、その第２の配線層に連接するボンデイ
ングパツド部とを有し、そのボンデイングパツド部は上
記堆積絶縁膜がとりのぞかれた上記熱酸化膜の上に存在
させたことを特徴とするものである。An object of the present invention is to provide a semiconductor device having a structure in which cracks do not occur in a deposited insulating film during wire bonding or face-down bonding.
The structure of the present invention to achieve this object includes a thermal oxide film formed on the main surface of a semiconductor substrate, a first wiring layer formed on the thermal oxide film, and a first wiring layer formed on the thermal oxide film. a deposited insulating film having a contact hole that exposes a part of the first wiring layer; and a second deposited insulating film that is in contact with the first wiring layer in the contact hole and extends over the deposited insulating film. and a bonding pad portion connected to the second wiring layer, and the bonding pad portion is located on the thermal oxide film from which the deposited insulating film is removed. It is characterized by:
以下実施例を用いて本発明を具体的に説明する。第１図
は本発明に係るバィボーラ半導体装置の−実施例を示す
要部断面構成図である。同図においてたとえばＰ型半導
体基板１上にＮ型半導体層２がたとえばエピタキシヤル
成長により形成されている。そしてこのＮ型半導体層２
を半導体素子形成領域ごとに分離するためｐ＋型のアィ
ソレーシヨン層３が前記Ｐ型半導体基板１に達するまで
形成されている。このアイソレーシヨン層３によつて囲
まれたＮ型半導体層領域２ａにおいて、その底面にはＮ
＋型の埋込み層４が表面にはＰ型のベース層５が形成さ
れ、またこのベース層５表面にはＮ＋型のエミツタ層６
が形成されている。そしてこのような各層が形成されて
いるＮ型半導体層２の表面には絶縁膜である熱酸化膜７
が形成され、この熱酸化膜７にはＮ型半導体層領域２ａ
、ベース層５およびエミツタ層６それぞれ一部を露出さ
せてコンタクト孔が形成されている。各コンタクト孔に
はたとえば蒸着法でアルミニウム層が形成されこれらは
熱酸化膜７上を延在されて配線層８を形成している。な
おこの配線層８のうち外部端子に接続されるものはその
端部８′において比較的面積が大になつている。そして
これら配線層８が形成されている領域を被つて膜厚１〜
４μｍのパツシペーシヨン膜９が形成され、またこの表
面の一部には孔開けがなされて、外部端子に接続される
べき配線層８の端部８ｒ〆露出している。なお、こＱパ
ツシベーシヨン膜９はたとえばスバツタリング方法によ
る石英膜、ＣＶＤ方法による燐シリケートガラス層ある
いはブラズマＣＶＤ法等によるシリコン窒化膜等であり
、熱酸化膜７の端辺部までには及んでいなくても良い。
前記パツシベーシヨン膜９から露出された配線層８の前
記端部８′は耐腐食性の金属たとえば白金（Ｐｔ）層１
０が接続されこの層は延在されて熱酸化膜７上にまで及
んでいるが、パツシベーシヨン膜９および熱酸化膜７と
の接着性を強固にするため白金層１０の下にはタンタル
（Ｔａ）層１１が介在されている。またこの領域以外に
は前記パツシベーシヨン膜９を被つてタンタル酸化膜（
Ｔａ２Ｏ５）１２が形成されてパツシベーシヨンをより
信頼性のあるものにしている。そして熱酸化膜７上まで
延在された白金（Ｐｔ）層１０上にはたとえばメツキ方
法等で金（Ａｕ）層１３が形成されてボンデイングパツ
ド部を構成している。なお前記タンタル酸化膜（Ｔａ，
Ｏ５）１２を形成する場合に＆ζ次のように行なうこと
により工数低減を図ることができる。The present invention will be specifically described below using Examples. FIG. 1 is a cross-sectional configuration diagram of essential parts showing an embodiment of a bibolar semiconductor device according to the present invention. In the figure, for example, an N-type semiconductor layer 2 is formed on a P-type semiconductor substrate 1 by, for example, epitaxial growth. And this N-type semiconductor layer 2
A p+ type isolation layer 3 is formed until it reaches the P type semiconductor substrate 1 in order to separate each semiconductor element formation region. In the N-type semiconductor layer region 2a surrounded by this isolation layer 3, N
A P-type base layer 5 is formed on the surface of the + type buried layer 4, and an N+ type emitter layer 6 is formed on the surface of this base layer 5.
is formed. A thermal oxide film 7, which is an insulating film, is formed on the surface of the N-type semiconductor layer 2 in which each of these layers is formed.
is formed, and this thermal oxide film 7 has an N-type semiconductor layer region 2a.
, a contact hole is formed by exposing a portion of each of the base layer 5 and the emitter layer 6. An aluminum layer is formed in each contact hole by, for example, a vapor deposition method, and is extended over the thermal oxide film 7 to form a wiring layer 8. Note that the wiring layer 8 that is connected to the external terminal has a relatively large area at its end 8'. Then, the area where these wiring layers 8 are formed is covered with a film having a thickness of 1 to 1.
A passivation film 9 having a thickness of 4 μm is formed, and a hole is formed in a part of the surface of the passivation film 9 to expose an end portion 8r of the wiring layer 8 to be connected to an external terminal. Note that this Q passivation film 9 is, for example, a quartz film formed by a sputtering method, a phosphorous silicate glass layer formed by a CVD method, or a silicon nitride film formed by a plasma CVD method, etc., and does not extend to the edges of the thermal oxide film 7. It's okay.
The end portion 8' of the wiring layer 8 exposed from the passivation film 9 is covered with a layer 1 of a corrosion-resistant metal such as platinum (Pt).
0 is connected and this layer is extended to cover the thermal oxide film 7. However, in order to strengthen the adhesion between the passivation film 9 and the thermal oxide film 7, tantalum (Ta) is formed under the platinum layer 10. ) layer 11 is interposed. In addition, other than this area, the passivation film 9 is covered with a tantalum oxide film (
Ta2O5)12 is formed to make the passivation more reliable. A gold (Au) layer 13 is formed on the platinum (Pt) layer 10 extending up to the thermal oxide film 7 by, for example, a plating method, thereby forming a bonding pad portion. Note that the tantalum oxide film (Ta,
When forming O5) 12, the number of man-hours can be reduced by performing &ζ as follows.
つまりパツシベーシヨン膜９の全面および熱酸化膜７を
被つてタンタル（Ｔａ）膜をスパツタリング法等により
形成し、次に白金（Ｐｔ）層をやはリスパツタリング法
等により前記タンタル（Ｔａ）膜上に形成した後、写真
蝕刻技術による選択エツチングで所定形状の白金（Ｐｔ
）層１０を形成する。その後メツキ方法等で金（Ａｕ）
層１３を形成する。そして前記白金（Ｐｔ）層１０をマ
スクとして陽極酸化あるいは熱処理酸化することにより
前記マスクから露出しているタンタル（Ｔａ）膜をタン
タル酸化（Ｔａ２Ｏ３）膜にする。このようにボンデイ
ングパツドをＡｌ配線上に形成された部分を有するパツ
シベーシヨン膜でなく、熱酸化膜上に直接形成するよう
にすれば、ボンデイングの際の荷重が直接ＣＶＤ法等で
形成したパツシベーシヨン膜に及ぶことがないのでこの
パツシベーシヨン膜に割れが生ずることはない。That is, a tantalum (Ta) film is formed by sputtering or the like to cover the entire surface of the passivation film 9 and the thermal oxide film 7, and then a platinum (Pt) layer is formed on the tantalum (Ta) film by resputtering or the like. After forming platinum (Pt) into a predetermined shape, selective etching is performed using photolithography technology.
) forming layer 10; After that, gold (Au) is produced using the plating method etc.
Form layer 13. Using the platinum (Pt) layer 10 as a mask, the tantalum (Ta) film exposed from the mask is converted into a tantalum oxide (Ta2O3) film by anodic oxidation or thermal oxidation. If the bonding pad is formed directly on the thermal oxide film instead of the passivation film having a portion formed on the Al wiring, the load during bonding will be directly applied to the passivation film formed by CVD or the like. Therefore, cracks do not occur in this passivation film.
なお、熱酸化膜はシリコン（Ｓｉ）単結晶上に形成され
たもので、ボンディング荷重による歪みは発生し難く強
いのでボンデイングの際の荷重が加わつてもなんら損傷
を生ずることはない。またパツシベーシヨン膜上にタン
タル酸化（Ｔａ２Ｏ５）膜を形成しておけば、よりパツ
シベーシヨンの信頼性を向上させることができる。Note that the thermal oxide film is formed on a silicon (Si) single crystal, and is strong and is unlikely to be distorted by bonding loads, so that no damage will occur even if a load is applied during bonding. Furthermore, if a tantalum oxide (Ta2O5) film is formed on the passivation film, the reliability of the passivation can be further improved.
実施例で示した製造方法によればこのタンタルが酸化さ
れる際体積膨張（約２．５倍）を生ずるのでパツシベー
シヨン膜の欠陥部を封孔することができる。本実施例で
はポンディングパツドをパツシベーシヨン膜が形成され
ていない熱酸化膜上に形成しているものであるが、第２
図で示すように、配線層８領域つまり熱酸化膜７の外周
部まで延在するようにパツシベーシヨン膜９を形成し、
ここに孔を形成してボンデイングパツドを形成しても同
様の効果が得られる。According to the manufacturing method shown in the embodiment, when this tantalum is oxidized, it expands in volume (approximately 2.5 times), so that defects in the passivation film can be sealed. In this example, the bonding pad is formed on a thermal oxide film on which no passivation film is formed.
As shown in the figure, a passivation film 9 is formed to extend to the wiring layer 8 region, that is, to the outer periphery of the thermal oxide film 7,
A similar effect can be obtained by forming a hole here to form a bonding pad.
すなわちボンデイングパツド下には硬度の小なるアルミ
ニウムなどの配線層が存在せず硬度の大なる熱酸化膜の
みが存在するので、ボンデイングの際前記ボンデイング
パツドに加わる荷重によつてパツシベーシヨン膜９には
大きな歪みが生じないのである。また本実施例ではボン
デイングパツドまで導かれる導電層は白金（Ｐｔ）層を
用いているがこれに限ることはなく、パラジウム（Ｐｄ
）層等でもよく要は耐腐食性の金属層ならばよい。That is, since there is no wiring layer such as aluminum with low hardness and only a thermal oxide film with high hardness under the bonding pad, the passivation film 9 is damaged by the load applied to the bonding pad during bonding. does not cause large distortion. Furthermore, in this embodiment, a platinum (Pt) layer is used as the conductive layer leading to the bonding pad, but the conductive layer is not limited to this.
) layer, etc., as long as it is a corrosion-resistant metal layer.
またこの金属層の下層に形成する介在層もタンタル（Ｔ
ａ）層に限ることはなくチタン（Ｔｉ）層、ジルコニウ
ム（Ｚｒ）層であつてもよい。さらにボンディングパツ
ド部には金（Ａｕ）層を形成しているものであるが銀（
Ａｇ）層であつてもよい。また本実施例ではパツシベー
シヨン膜の上面にタンタル酸化（Ｔａ２Ｏ５）膜を形成
しよりパツシベーシヨンの信頼性を向上させているが、
これは本発明の要旨ではないことから形成してなくても
よい。Furthermore, the intervening layer formed below this metal layer is tantalum (T
The layer is not limited to the a) layer, and may be a titanium (Ti) layer or a zirconium (Zr) layer. Furthermore, although a gold (Au) layer is formed on the bonding pad, silver (
(Ag) layer. In addition, in this example, a tantalum oxide (Ta2O5) film is formed on the upper surface of the passivation film to further improve the reliability of the passivation.
Since this is not the gist of the present invention, it may not be formed.
さらに本実施例では一層配線による半導体装置を例に掲
げたものであるが層間絶縁膜を介した多層配線にも応用
できるものである。Furthermore, although this embodiment takes as an example a semiconductor device with single-layer wiring, it can also be applied to multi-layer wiring with interlayer insulating films interposed therebetween.
本発明はワイャボンディング用の半導体装置について述
べたものであるがフエースダウンボンディング用の半導
体装置においても、従来同様の欠点を有することから、
この半導体装置にも応用できるものである。Although the present invention describes a semiconductor device for wire bonding, semiconductor devices for face-down bonding also have the same drawbacks as conventional devices.
It can also be applied to this semiconductor device.
以上述べたように本発明による半導体装置によれば、ボ
ンデイングの際、パツシベーシヨン膜に割れが生ずるこ
とはなくなる。As described above, according to the semiconductor device according to the present invention, cracks do not occur in the passivation film during bonding.
第１図は本発明による半導体装置の一実施例を示す要部
断面構成図、第２図は本発明による半導体装置の他の実
施例を示す要部断面構成図である。
１・・・・・・Ｐ型半導体基板、２・・・・・・Ｎ型半
導体層、３・・・・・・アイソレーシヨン層、４・・・
・・・埋込み層、５・・・・・・ベース層、６・・・・
・・エミツタ層、７・・・・・・熱酸化膜、８・・・・
・・配線層、９・・・・・・パツシベーシヨン膜、１０
・・・・・・白金（Ｐｔ）層、１１・・・・・・タンタ
ル（Ｔａ）層、１２・・・・・・タンタル酸化（Ｔａ２
Ｏ。FIG. 1 is a cross-sectional configuration diagram of essential parts showing one embodiment of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional configuration diagram of essential parts showing another embodiment of a semiconductor device according to the present invention. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type semiconductor layer, 3... Isolation layer, 4...
...Embedded layer, 5...Base layer, 6...
... Emitter layer, 7... Thermal oxide film, 8...
...Wiring layer, 9...Passivation film, 10
...Platinum (Pt) layer, 11 ... Tantalum (Ta) layer, 12 ... Tantalum oxide (Ta2
O.
Claims (1)
酸化膜上に形成された第１の配線層と、その熱酸化膜上
に形成され、上記第１の配線層の一部を露出するような
コンタクト穴を有する堆積絶縁膜と、上記コンタクト穴
内において上記第１の配線層に接し、かつ上記堆積絶縁
膜上に延在する第２の配線層と、その第２の配線層に連
接するボンディングパッド部とを有し、そのボンディン
グパッド部は上記堆積絶縁膜がとりのぞかれた上記熱酸
化膜の上に存在させたことを特徴とする半導体装置。1 A thermal oxide film formed on the main surface of a semiconductor substrate, a first wiring layer formed on the thermal oxide film, and a part of the first wiring layer formed on the thermal oxide film. a deposited insulating film having an exposed contact hole; a second wiring layer in contact with the first wiring layer in the contact hole and extending over the deposited insulating film; 1. A semiconductor device comprising a bonding pad portion connected to the semiconductor device, the bonding pad portion being located on the thermal oxide film from which the deposited insulating film has been removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4765876A JPS5937576B2 (en) | 1976-04-28 | 1976-04-28 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4765876A JPS5937576B2 (en) | 1976-04-28 | 1976-04-28 | semiconductor equipment |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59089446A Division JPS59218761A (en) | 1984-05-07 | 1984-05-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52131455A JPS52131455A (en) | 1977-11-04 |
| JPS5937576B2 true JPS5937576B2 (en) | 1984-09-11 |
Family
ID=12781344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4765876A Expired JPS5937576B2 (en) | 1976-04-28 | 1976-04-28 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5937576B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5472958A (en) * | 1977-11-24 | 1979-06-11 | Hitachi Ltd | Electrode structure of semiconductor device |
| JPS54117680A (en) * | 1978-03-03 | 1979-09-12 | Nec Corp | Semiconductor device |
| JPS5984551A (en) * | 1982-11-08 | 1984-05-16 | Nec Corp | Semiconductor device |
-
1976
- 1976-04-28 JP JP4765876A patent/JPS5937576B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52131455A (en) | 1977-11-04 |
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