JPS6133257B2 - - Google Patents
Info
- Publication number
- JPS6133257B2 JPS6133257B2 JP4568378A JP4568378A JPS6133257B2 JP S6133257 B2 JPS6133257 B2 JP S6133257B2 JP 4568378 A JP4568378 A JP 4568378A JP 4568378 A JP4568378 A JP 4568378A JP S6133257 B2 JPS6133257 B2 JP S6133257B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- platinum
- semiconductor
- forming
- silicide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 20
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical group [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910021339 platinum silicide Inorganic materials 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 4
- 238000005275 alloying Methods 0.000 claims 1
- 239000010408 film Substances 0.000 description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 239000010703 silicon Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910001260 Pt alloy Inorganic materials 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Dicing (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかり特に半
導体装置のスクライブ方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of scribing a semiconductor device.
近来の半導体技術の進歩により、シヨツトキー
バリヤダイオードを含む集積回路等の複雑な構造
の装置が多くなつた。このシヨツトキーバリヤダ
イオードを作るには、たとえば白金の薄膜を蒸着
し、適当な熱処理を於して、白金−シリサイド層
を形成する等の方法がある。この時、第１図に示
すようにスクライブ領域Ａのスクライブ線上に白
金−シリサイド層５が形成される。この白金−シ
リサイド層５は硬度が高く、したがつてスクライ
ブ線上に白金−シリサイド層５があることにより
スクライブ作業性が悪くなり、スクライブ歩留り
が低下してしまう。 Recent advances in semiconductor technology have led to an increase in the number of devices with complex structures, such as integrated circuits that include Schottky barrier diodes. The Schottky barrier diode can be fabricated by, for example, depositing a thin film of platinum, followed by appropriate heat treatment to form a platinum-silicide layer. At this time, a platinum-silicide layer 5 is formed on the scribe line in the scribe area A, as shown in FIG. This platinum-silicide layer 5 has high hardness, and therefore, the presence of the platinum-silicide layer 5 on the scribe line deteriorates the scribing workability and reduces the scribing yield.
また、スクライブ領域Ａに白金−シリサイド層
ができないように、スクライブ線上に熱酸化膜２
を残しておくと、次に引き続いて形成されるパツ
シベーシヨンとなる窒化膜３、CVD酸化膜４が
重なつて第２図の様になる。このままスクライブ
しようとすると、スクライブ線が見えにくい上、
多層の種々の膜のためスクライブしにくくなり、
やはりスクライブ歩留りは低下する。又、スクラ
イブ線上の半導体基板を露出させようとすると、
酸化膜と窒化膜のエツチング液が異なるため、エ
ツチング工程が増えることとになる。 Also, in order to prevent a platinum-silicide layer from forming in the scribe area A, a thermal oxide film 2 is placed on the scribe line.
If this is left, the nitride film 3 and CVD oxide film 4, which will be successively formed as a passivation layer, overlap to form a structure as shown in FIG. 2. If you try to scribe in this state, the scribe line will be difficult to see, and
Due to the multi-layered various films, it becomes difficult to scribe,
The scribing yield also decreases. Also, if you try to expose the semiconductor substrate on the scribe line,
Since the etching solutions for the oxide film and the nitride film are different, the number of etching steps increases.
本発明の目的は、以上のように工程を増さず、
スクライブ作業性を良くし、スクライブ歩留りを
向上させた有効な半導体装置の製造方法を提供す
ることである。 The purpose of the present invention is to avoid increasing the number of steps as described above,
An object of the present invention is to provide an effective method for manufacturing a semiconductor device that improves scribing workability and improves scribing yield.
本発明の特徴は、スクライブ領域すなわちスク
ライブ線上に少なくとも２種類の金属の合金、た
とえばシヨツトキー障壁を作る金属、配線層の金
属とシリコンとの合金層を設けたことである。 A feature of the present invention is that an alloy of at least two kinds of metals, for example, a metal forming a Schottky barrier, and an alloy layer of a metal of a wiring layer and silicon, is provided on the scribe region, that is, the scribe line.
通常のシヨツトキーバリヤダイオードを含む集
積回路は白金−シリサイド層の上にアルミを蒸着
し、このアルミで半導体素子間の配線を行う。本
発明では、上記アルミ層をスクライブ線上の白金
−シリサイド層上に形成し、適切な熱処理をする
ことにより、スクライブ線上の白金−シリサイド
は白金とシリコンとアルミの合金となる。この合
金は白金−シリサイドほど硬くないのでスクライ
ブ作業性は良くなり、したがつてスクライブ歩留
りは向上する。また前記アルミ蒸着及び熱処理
は、通常のアルミ配線を行う場合のアルミ蒸着と
アルミアロイのための熱処理と同時に行えるので
工程が増えることはない。第３図は本発明によ
り、スクライブ線上の白金−シリサイド層上にア
ルミ層を形成したところを示し、第４図は熱処理
を施した後、白金−シリサイド層５が白金とシリ
コンとアルミ合金層８に変わつたところを示す。
このような半導体ウエハーをスクライブすれば、
半導体装置のスクライブされた端部は第５図に示
すように半導体基板１上に合金層８が形成されて
いることとなる。 Integrated circuits containing conventional Schottky barrier diodes are manufactured by depositing aluminum over a platinum-silicide layer, and using this aluminum to provide wiring between semiconductor devices. In the present invention, the aluminum layer is formed on the platinum-silicide layer on the scribe line and subjected to appropriate heat treatment, so that the platinum-silicide on the scribe line becomes an alloy of platinum, silicon, and aluminum. Since this alloy is not as hard as platinum-silicide, scribing workability is improved and therefore scribing yield is improved. Further, the aluminum vapor deposition and heat treatment can be performed simultaneously with the aluminum vapor deposition and heat treatment for aluminum alloy when performing normal aluminum wiring, so there is no increase in the number of steps. FIG. 3 shows that an aluminum layer is formed on the platinum-silicide layer on the scribe line according to the present invention, and FIG. 4 shows that after heat treatment, the platinum-silicide layer 5 is replaced with platinum, silicon, and aluminum alloy layer 8. This shows what has changed.
If you scribe such a semiconductor wafer,
At the scribed end of the semiconductor device, an alloy layer 8 is formed on the semiconductor substrate 1, as shown in FIG.
第１図および第２図はそれぞれ従来技術による
半導体装置を示す断面図である。第３図および第
４図は本発明の一実施例を工程順に示した断面図
であり、第５図は第４図をスクライブした本発明
一実施例の半導体装置の一部断面図である。
尚、図において、１……半酸導体基板、２……
熱酸化膜、３……窒化膜、４……CVD酸化膜、
５……白金−シリサイド層、７……アルミ層、８
……白金とシリコンとアルミの合金層、Ａ……ス
クライブ領域（スクライブ線）である。
FIG. 1 and FIG. 2 are sectional views each showing a semiconductor device according to the prior art. 3 and 4 are cross-sectional views showing an embodiment of the present invention in the order of steps, and FIG. 5 is a partial cross-sectional view of the semiconductor device of the embodiment of the present invention obtained by scribing FIG. 4. In the figure, 1... half acid conductor substrate, 2...
Thermal oxide film, 3...Nitride film, 4...CVD oxide film,
5...Platinum-silicide layer, 7...Aluminum layer, 8
. . . alloy layer of platinum, silicon, and aluminum, A . . . scribe area (scribe line).
Claims (1)
基板を露出せしめる工程と、半導体素子形成のた
めの金属被着と同時に前記スクライブ領域に第１
の金属を被着形成する工程と、熱処理することに
より前記第１の金属のシリサイド層を形成する工
程と、前記半導体素子を接続する配線層形成と同
時に前記シリサイド層に接して第２の金属を被着
形成する工程と、熱処理することにより前記シリ
サイド層を前記第２の金属と合金化せしめて合金
層を形成する工程と、前記合金層上からスクライ
ブを施す工程を含むことを特徴とする半導体装置
の製造方法。 ２ 前記半導体素子はシヨツトキー・バリヤ・ダ
イオードを含むことを特徴とする特許請求の範囲
第１項記載の半導体装置の製造方法。 ３ 前記シリサイド層は白金シリサイドであるこ
とを特徴とする特許請求の範囲第１項または第２
項記載の半導体装置の製造方法。 ４ 前記第２の金属はアルミニウムであることを
特徴とする特許請求の範囲第１項、第２項または
第３項記載の半導体装置の製造方法。[Claims] 1. A step of exposing the semiconductor substrate on the scribe region on the main surface of the semiconductor substrate, and simultaneously depositing metal on the scribe region for forming a semiconductor element.
a step of forming a silicide layer of the first metal by heat treatment; and a step of forming a second metal in contact with the silicide layer at the same time as forming a wiring layer connecting the semiconductor element. A semiconductor characterized by comprising the steps of depositing, forming an alloy layer by alloying the silicide layer with the second metal through heat treatment, and scribing from above the alloy layer. Method of manufacturing the device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor element includes a Schottky barrier diode. 3. Claim 1 or 2, wherein the silicide layer is platinum silicide.
A method for manufacturing a semiconductor device according to section 1. 4. The method of manufacturing a semiconductor device according to claim 1, 2, or 3, wherein the second metal is aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4568378A JPS54137273A (en) | 1978-04-17 | 1978-04-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4568378A JPS54137273A (en) | 1978-04-17 | 1978-04-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54137273A JPS54137273A (en) | 1979-10-24 |
| JPS6133257B2 true JPS6133257B2 (en) | 1986-08-01 |
Family
ID=12726185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4568378A Granted JPS54137273A (en) | 1978-04-17 | 1978-04-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54137273A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5780719A (en) * | 1980-11-07 | 1982-05-20 | Fujitsu Ltd | Semiconductor device |
| US11011381B2 (en) * | 2018-07-27 | 2021-05-18 | Texas Instruments Incorporated | Patterning platinum by alloying and etching platinum alloy |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4926740A (en) * | 1972-07-04 | 1974-03-09 |
-
1978
- 1978-04-17 JP JP4568378A patent/JPS54137273A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4926740A (en) * | 1972-07-04 | 1974-03-09 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54137273A (en) | 1979-10-24 |
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