JPS60176231A - Electrode forming process of compound semiconductor element - Google Patents

Electrode forming process of compound semiconductor element

Info

Publication number
JPS60176231A
JPS60176231A JP3171584A JP3171584A JPS60176231A JP S60176231 A JPS60176231 A JP S60176231A JP 3171584 A JP3171584 A JP 3171584A JP 3171584 A JP3171584 A JP 3171584A JP S60176231 A JPS60176231 A JP S60176231A
Authority
JP
Japan
Prior art keywords
insulating film
film
electrode
photoresist
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3171584A
Other languages
Japanese (ja)
Inventor
Hisahiro Ishihara
久寛 石原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3171584A priority Critical patent/JPS60176231A/en
Publication of JPS60176231A publication Critical patent/JPS60176231A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To form an electrode with high reliability by a method wherein a Ti/ Pt evaporated film formed for forming an electrode is heat-treated to form an alloy layer and then further evaporates Ti/Au to form multilayered metallic film. CONSTITUTION:A surface protective insulating film 2 is formed on the surface of a compound semiconductor 1 while photoresist 3 in a specific region on the film 2 is removed by coating, exposing and developing processes and then the insulating film below the removed region 3 is further removed by etching process to expose the surface of semiconductor 1. Firstly after evaporating Ti/Pt 5, a Ti4/ Pt5 film is selectively formed on a specific region by peeling off the photoresist 3. Then Ti, a semiconductor and an alloy layer are formed to obtain electrode ohmic. Later another surface protective insulating film 6 is formed again and another photoresist 7 in a specific region located on the Ti/Pt is removed by coating, exposing and developing processes. Secondly the insulating film 6 is selectively removed to evaporate Ti8/Au9. Finally the photoresist 7 is peeled off to form the bonding pad Ti8/Au9 selectively on the specific region.

Description

【発明の詳細な説明】 本発明は化合物半導体素子の電極の作シ方に関するもの
である。化合物半導体は光通信用素子あるいけ高速素子
等に広く用いられて来て−るが、これらの素子は場合に
よっては厳しい条件下で、か一つまた保守が困難という
状況下で使用される。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing electrodes of a compound semiconductor device. Compound semiconductors have been widely used in optical communication devices, high-speed devices, and the like, but these devices are sometimes used under harsh conditions and in situations where maintenance is difficult.

従ってこれらの素子には優れた特性と同時にその使用環
境によっては高い信頼性が要求される。信頼性に最も影
響する因子の1つに電極と半導体との反応によって進行
する電極劣化が挙げられ、る。
Therefore, these devices are required to have excellent characteristics and high reliability depending on the environment in which they are used. One of the factors that most affects reliability is electrode deterioration that progresses due to the reaction between the electrode and the semiconductor.

半導体素子には従来、少量のドーピング不純物(Zn、
Ge等)を含むAuを直接半導体に接触させる構造のオ
ーム性電極が広く用いられて来た。しかしこの構造にお
いてはAuが200’C程度から半導体と反応するため
、特には素子を著しく劣化させていた。これを改善する
ためにTi 、Pd、Pt 、W等の高融点金員を挾ん
だT i/(Pd 、 P t 、W)lAu多層構造
の電極が注目されて来た。’l’ i/P I lA 
u電極はアロイ層としてTi、ポンディングパッドとソ してAuを使用し、それら2層の間にAuのパーアメタ
ルとして高融点金属であるPt を挾んだ3層構造から
成っておシ、多層構造電極の中でも代表的なもので、強
い関心を集めている。
Semiconductor devices have conventionally contained small amounts of doping impurities (Zn,
Ohmic electrodes having a structure in which Au containing Ge, etc.) are brought into direct contact with a semiconductor have been widely used. However, in this structure, Au reacts with the semiconductor at about 200'C, which significantly deteriorates the device. In order to improve this, an electrode with a multilayer structure of Ti/(Pd, Pt, W)lAu in which high-melting point metals such as Ti, Pd, Pt, and W are sandwiched has attracted attention. 'l' i/P I lA
The u-electrode has a three-layer structure in which Ti is used as the alloy layer, Au is used as the bonding pad, and Pt, which is a high-melting point metal, is sandwiched between these two layers. It is a typical type of structured electrode and is attracting strong interest.

す しかしAuとバイアメタルとの相互拡散による金稿間反
応性は高温下では十分に小さいとは云い難い。このため
T i /P t /A u蒸着膜形成後の熱処理時I
/cPt%Tiを通り抜けて半導体との界面まで達する
Au原子が、半導体と反応を起こしてアロイスパイクを
生じさせ素子特性劣化の原因となる場合があった。
However, it is difficult to say that the intermetallic reactivity due to mutual diffusion between Au and via metal is sufficiently small at high temperatures. Therefore, during the heat treatment after forming the T i /P t /A u vapor deposited film, I
/cPt%Ti Au atoms that reach the interface with the semiconductor may react with the semiconductor to generate alloy spikes and cause deterioration of device characteristics.

本発明の目的は前記従来の欠点を解決し、信頼性の高い
化合物半導体素子の電極の形成方法を提供することにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks and provide a highly reliable method for forming electrodes of compound semiconductor devices.

この発明KJ:れば、電極形成のためにまずTi/Pt
 蒸着膜を形成した後熱処理によるアロイ層を得る工程
と、更にその上にT r /A u蒸着を行なりて多層
金属膜を形成する工程を含む化合物半導体素子の電極形
成方法が得られる。
This invention KJ: First, Ti/Pt is used for electrode formation.
A method for forming electrodes of a compound semiconductor device is obtained, which includes a step of forming a vapor-deposited film and then heat-treating it to obtain an alloy layer, and further forming a multilayer metal film by performing T r /Au vapor deposition thereon.

以下この発明について図面を用いて詳細に説明する。w
c1図は従来のTi/Pt/Au[極の断面図を表わす
This invention will be explained in detail below using the drawings. lol
Figure c1 represents a cross-sectional view of a conventional Ti/Pt/Au pole.

第1図(a)に示す構造では表面保6の絶縁膜2と電極
3,4,5との間にすき間が空いている。このためTi
3.Pt4.Au5の連続蒸着後の熱処理時における、
先に述べたAu5 の高反応性に起因する劣化の他に、
すき間の領域では半導体1の表面が露出しているため、
半導体表面は雰囲気からの汚染によシ表面状態が変化し
易くなる事による劣化という問題点が挙がって来る。
In the structure shown in FIG. 1(a), there are gaps between the insulating film 2 of the surface protector 6 and the electrodes 3, 4, and 5. For this reason, Ti
3. Pt4. During heat treatment after continuous deposition of Au5,
In addition to the deterioration caused by the high reactivity of Au5 mentioned above,
Since the surface of the semiconductor 1 is exposed in the gap region,
The problem of deterioration of the semiconductor surface is that the surface state is easily changed due to contamination from the atmosphere.

第1図(b) K示す構造では電極金属3.4.5が絶
縁膜2の端の部分を覆っておシ、半導体表面が露出する
事はない。
In the structure shown in FIG. 1(b) K, the electrode metal 3.4.5 covers the end portion of the insulating film 2, so that the semiconductor surface is not exposed.

しかし絶縁膜2の熱膨張係数が金属3,4.5や半導体
1に比べて小さ過ぎるため、熱処理時に絶縁膜2の端の
部分に応力が掛かり易く劣化の原因になって来る。
However, since the coefficient of thermal expansion of the insulating film 2 is too small compared to the metals 3, 4.5 and the semiconductor 1, stress is easily applied to the end portions of the insulating film 2 during heat treatment, causing deterioration.

また絶縁膜ステップ側面における金属の被覆がj合 悪い時にけAu5が金属3と絶縁膜2との界面に潰って
半導体表面まで浸透して反応劣化を誘起するタメ(a1
図の構造に比べてさらにアロイスパイクが生じ易くなる
In addition, when the metal coating on the side surface of the insulating film step is not suitable, Au5 collapses on the interface between the metal 3 and the insulating film 2 and penetrates to the semiconductor surface, causing reaction deterioration (a1
Compared to the structure shown in the figure, alloy spikes are more likely to occur.

次忙、本発明釦よるT i/P t/T i/Au電極
の形成方法の模式図を第2図(a)〜(h)に示す。
FIGS. 2(a) to 2(h) show schematic diagrams of the method for forming Ti/Pt/Ti/Au electrodes using the button of the present invention.

本発明によれば、まず第2図(a)に示す様に化合物半
導体10表面に表面保護絶縁膜2を形成し、さらに該絶
縁膜上に7オトレジスト3を塗布。露光、現像によシ特
定領域の7オトレジストを除去する。次に該特定領域の
絶縁膜をエツチングVc1シ除去し、半導体表面を露出
させる。(同図(b))Ti4/Pt5を蒸着(同図(
c) ) した後、フォトレジストを剥離する事にz6
特定領域のみに選択的にTi4/Pt5膜を形成する。
According to the present invention, first, as shown in FIG. 2(a), a surface protection insulating film 2 is formed on the surface of the compound semiconductor 10, and then a photoresist 3 is coated on the insulating film. The photoresist in a specific area is removed by exposure and development. Next, the insulating film in the specific region is removed by etching Vc1 to expose the semiconductor surface. ((b) in the same figure) Ti4/Pt5 is deposited (((b) in the same figure)
c)) After that, remove the photoresist.
A Ti4/Pt5 film is selectively formed only in a specific region.

(同図(d))この状態で熱処理を施し、Tiと半導体
とのアロイ層を形成して電極のオーミックを得る。しか
る後に同図(elに示す様に表面保護絶縁膜6を再び形
成、さらに7オトレジスト7を塗布。露光、現像によk
)Tilpt 上に位置する特定領域のフォトレジスト
を除去する。次に絶縁膜を選択的に除去しく同図(f)
)、T i 8/Au 9を蒸着する(同図(g))。
((d) in the same figure) Heat treatment is performed in this state to form an alloy layer of Ti and semiconductor to obtain ohmic properties of the electrode. After that, as shown in the same figure (el), the surface protection insulating film 6 is formed again, and the photoresist 7 is further applied.
) Remove the photoresist in specific areas located on the Tilpt. Next, the insulating film is selectively removed (see figure (f)).
), and T i 8/Au 9 is deposited ((g) in the same figure).

最後に7オトレジストを剥離する事によりポンディング
パッドT i 8/Au 9が特定領域に選択的に形成
される(同図(h))。
Finally, by peeling off the photoresist 7, bonding pads T i 8/Au 9 are selectively formed in specific areas (FIG. 4(h)).

本発明によれげ熱処理時にAuが相互拡散によりバリア
メタル中を通り抜け、半導体との界面に達して反応を起
こしア皇イ・スパイクを形成する事による素子特性の劣
化は無い。また熱処理時に電極金属と絶縁膜が接してい
ないので熱膨張係数の差に上る応力が加わる事もない。
According to the present invention, during heat treatment, Au passes through the barrier metal due to interdiffusion, reaches the interface with the semiconductor, causes a reaction, and does not cause deterioration of device characteristics due to the formation of spikes. Furthermore, since the electrode metal and the insulating film are not in contact with each other during heat treatment, stress due to the difference in thermal expansion coefficients is not applied.

・そして、電極形成前にクリーンな表面状態の下に形成
した第1の絶縁膜を残す事によシ、絶縁膜と半導体との
界面を安定に保つ事が出来る。更に最終的には絶縁膜が
段切れも無(Ti/Ptの端部までを覆う構造となるた
め半導体表面が雰囲気中に露出する部分は無く表面劣化
を防止出来、かつまた絶縁膜で電極金属を押さえる事に
よシミ極の密着性も高くなる。
- By leaving the first insulating film formed under a clean surface condition before electrode formation, the interface between the insulating film and the semiconductor can be kept stable. Furthermore, the final result is that the insulating film has no step breaks (it has a structure that covers all the way to the edges of the Ti/Pt, so no part of the semiconductor surface is exposed to the atmosphere, preventing surface deterioration. By pressing down, the adhesion of the stain electrode will also increase.

以上説明した様に、本発明によれば化合物半導体素子の
電極としてよル信頼性の高いものが得られる。
As explained above, according to the present invention, a highly reliable electrode for a compound semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図+al、(blはTi/Pt/Au 3層構造の
電極を有する化合物半導体素子の構造模式図、第2 [
(a) y(b) p (cl p (ct) 、 (
e) 、(r) p (gl 、 (h))は本発明の
一実施例の、Ti/Pt/Ti/Au4層構造の電極を
有する化合物半導体素子の高信頼電極の製造工程の模式
図である。図中1はAu % 2はPt、3はTi 、
4は絶縁膜、5は化合物半導体、6はフォトレジストを
示す。
Figure 1 + al, (bl is a structural schematic diagram of a compound semiconductor device having an electrode with a Ti/Pt/Au three-layer structure, Figure 2 [
(a) y(b) p (cl p (ct) , (
e), (r) p (gl, (h)) are schematic diagrams of the manufacturing process of a highly reliable electrode of a compound semiconductor device having a Ti/Pt/Ti/Au four-layer structure electrode according to an embodiment of the present invention. be. In the figure, 1 is Au%, 2 is Pt, 3 is Ti,
4 is an insulating film, 5 is a compound semiconductor, and 6 is a photoresist.

Claims (1)

【特許請求の範囲】[Claims] 第1の絶縁膜によって選択的に化合物半導体を露出させ
た領域にTi/Ptから成る第1の多層金属膜を絶縁膜
と接しないように被着させ、当該金員膜が形成された半
導体結晶を熱処理する工程と、しかる後に第2の絶縁膜
を形成、該第2の絶縁膜中、上記第1の多層金員膜上に
ある特定領域を選択的に除去、第1の多層金属膜表面を
露出させた領域ICT i lA uから成る第2の多
層金属膜を被着させる工程とから構成される事を特徴と
する化合物半導体素子の電極の形成方法。
A first multilayer metal film made of Ti/Pt is deposited on the region where the compound semiconductor is selectively exposed by the first insulating film so as not to be in contact with the insulating film, and a semiconductor crystal on which the metal film is formed is formed. and then forming a second insulating film, selectively removing a specific region on the first multilayer metal film in the second insulating film, and removing the surface of the first multilayer metal film. A method for forming an electrode of a compound semiconductor device, comprising the step of depositing a second multilayer metal film consisting of an exposed region ICT i lA u.
JP3171584A 1984-02-22 1984-02-22 Electrode forming process of compound semiconductor element Pending JPS60176231A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3171584A JPS60176231A (en) 1984-02-22 1984-02-22 Electrode forming process of compound semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3171584A JPS60176231A (en) 1984-02-22 1984-02-22 Electrode forming process of compound semiconductor element

Publications (1)

Publication Number Publication Date
JPS60176231A true JPS60176231A (en) 1985-09-10

Family

ID=12338757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3171584A Pending JPS60176231A (en) 1984-02-22 1984-02-22 Electrode forming process of compound semiconductor element

Country Status (1)

Country Link
JP (1) JPS60176231A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62189731A (en) * 1986-02-15 1987-08-19 Honda Motor Co Ltd Forming method for ohmic electrode on n-type gallium arsenide
JPS63124461A (en) * 1986-11-12 1988-05-27 Nec Corp Semiconductor device
JPH0243769A (en) * 1988-08-03 1990-02-14 Toshiba Corp Semiconductor device and manufacture thereof
JP2009206357A (en) * 2008-02-28 2009-09-10 Asahi Kasei Electronics Co Ltd Compound semiconductor device and method for manufacturing compound semiconductor device
JP2010172821A (en) * 2009-01-29 2010-08-12 Ckd Corp Filter device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62189731A (en) * 1986-02-15 1987-08-19 Honda Motor Co Ltd Forming method for ohmic electrode on n-type gallium arsenide
JPS63124461A (en) * 1986-11-12 1988-05-27 Nec Corp Semiconductor device
JPH0243769A (en) * 1988-08-03 1990-02-14 Toshiba Corp Semiconductor device and manufacture thereof
JP2009206357A (en) * 2008-02-28 2009-09-10 Asahi Kasei Electronics Co Ltd Compound semiconductor device and method for manufacturing compound semiconductor device
JP2010172821A (en) * 2009-01-29 2010-08-12 Ckd Corp Filter device

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