JPS60160120A - Formation of electrode for semiconductor element - Google Patents

Formation of electrode for semiconductor element

Info

Publication number
JPS60160120A
JPS60160120A JP1465284A JP1465284A JPS60160120A JP S60160120 A JPS60160120 A JP S60160120A JP 1465284 A JP1465284 A JP 1465284A JP 1465284 A JP1465284 A JP 1465284A JP S60160120 A JPS60160120 A JP S60160120A
Authority
JP
Japan
Prior art keywords
window
insulating film
layer
electrode
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1465284A
Other languages
Japanese (ja)
Inventor
Yoshiharu Tashiro
田代 義春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1465284A priority Critical patent/JPS60160120A/en
Publication of JPS60160120A publication Critical patent/JPS60160120A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent deterioration of a semiconductor element and to obtain a highly reliable electrode by a method wherein the window having a stepping is provided on an insulating film, and a prescribed metal and Au are laminated on the window and the stepping. CONSTITUTION:A window 8 is provided on the SiO2 film 2 located on an Si substrate 1, the resist mask 10 of window 9 larger than the window 9 is provided, and a stepping 7 is formed by performing an etching. Then, Ti 3, Pt 4 and Au 5 are vapor-deposited successively, and the layers 3-5 are removed together with the resist 10. According to this constitution, the disconnection of the Ti 3 and the Pt 4 can be prevented, the infiltration of Au generating when an annealing is performed can be prevented and the deterioration of Si element can also be prevented by having the small stepping 6 of the insulating film 2. Besides, a multilayer metal layer is composed of at least two kinds of Au selected from Ti, Pt, Pd and W.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体素子用電極の形成方法に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a method for forming an electrode for a semiconductor device.

〔従来技術〕[Prior art]

従来、半導体素子は広i用途で用−られているが、その
中には厳しい条件下でかつ保守が困難という状況で使用
されている場合が数多くめる。それらの素子には優れた
特性と同時に高い信頼性が要求される。信頼性を低下さ
せる原因の一つに電極と半導体との反応により進行する
劣化がある。
Semiconductor devices have heretofore been used for a wide range of purposes, many of which are used under harsh conditions and where maintenance is difficult. These devices are required to have excellent characteristics and high reliability. One of the causes of reduced reliability is the deterioration that progresses due to the reaction between the electrode and the semiconductor.

従来よシ、少量のドーピング不純物(Zn、8i。Conventionally, a small amount of doping impurity (Zn, 8i.

Ge等)を含むAuを直接半導体に接触させる構造のオ
ーム性電極が広く用いられてきたが、この構造では電極
金属と半導体が低い温度で反応するため時には素子を著
しく劣化させていたという問題があった。この問題を解
決するためにTI、Pi。
Ohmic electrodes with a structure in which Au containing Ge, etc.) are brought into direct contact with the semiconductor have been widely used, but this structure has the problem that the electrode metal and semiconductor react at low temperatures, which sometimes significantly degrades the device. there were. To solve this problem, TI, Pi.

pd、w等の高融点金、Mt−挾んだT i / (P
 t 、 P d 。
High melting point gold such as pd, w, Mt-sandwiched Ti/(P
t, Pd.

W)/Au多層金属の電極が注目されて来た。Ti/P
tlムU電極は合金層としてTi、ポンディングパッド
としてAut−使用し、それらの2層の間にAuの障壁
金属として高融点金属であるPtを挾んだ3層構造から
成っており、多属構造電極の中でも代表的な本ので強い
関心を果めている。
W)/Au multilayer metal electrodes have attracted attention. Ti/P
The TLM U electrode has a three-layer structure using Ti as an alloy layer, Au as a bonding pad, and Pt, a high melting point metal, as a barrier metal for Au sandwiched between these two layers. This is one of the most representative books on structural electrodes, and has attracted a lot of attention.

第1図は従来のTi/Pt/Au多縞構造電極を多重構
造電極素子の要部の断面図である。
FIG. 1 is a sectional view of a main part of a conventional Ti/Pt/Au multi-striped structure electrode element.

半導体基板1の上に絶縁膜2を設け、コンタクト用窓め
けをする。そして11層3.Pt層4゜Au層5を積層
して多層構造の電極を形成する。
An insulating film 2 is provided on a semiconductor substrate 1, and a contact window is provided. And 11 layers 3. A Pt layer 4 and an Au layer 5 are laminated to form a multilayer electrode.

コノ構造では、Ti/Pt/Auの三層の金jIIg#
が絶縁膜2の上を覆い、外部からの汚染を防ぐために絶
縁膜ステップ6上に電極金Jlを形成しているが、絶縁
膜ステップ6における金属の被覆が悪い時には熱処理時
にAu層5が11層3.Ptjd4と絶縁膜2の界面に
沿って半導体表面まで浸透し、Au原子が半導体と反応
を起こし深い位置まで合金層を進行させ、劣化の原因と
なることがあった。
In the cono structure, three layers of Ti/Pt/Au gold jIIg#
In order to cover the top of the insulating film 2 and prevent contamination from the outside, an electrode gold Jl is formed on the insulating film step 6. However, if the metal coverage in the insulating film step 6 is poor, the Au layer 5 may become 11 during heat treatment. Layer 3. The Au atoms penetrate to the semiconductor surface along the interface between the Ptjd 4 and the insulating film 2, and the Au atoms react with the semiconductor, causing the alloy layer to advance to a deep position, causing deterioration.

ここで、11層3.Pt層4を厚く形成することによシ
この劣化をなくすことも考えられる。その場合、Ti/
(Pt 、Pd、W)/Au電極では、電極パターニン
グを行う際、半導体をエツチングすることなしに電極の
みエツチングすることは難しく、スパッタエツチングで
は半導体基板に損傷を残す。また、電極パターニングを
行うのKはリフトオフ法が簡易であり一般によく用いら
れているが厚い金属に対しては歩留が悪くなる欠点があ
る。
Here, 11 layers 3. It is also possible to eliminate this deterioration by forming the Pt layer 4 thickly. In that case, Ti/
When patterning the (Pt, Pd, W)/Au electrode, it is difficult to etch only the electrode without etching the semiconductor, and sputter etching leaves damage to the semiconductor substrate. Furthermore, the lift-off method is simple and commonly used for electrode patterning, but it has the disadvantage of poor yield for thick metals.

また絶縁膜の全膜厚を薄くすることによってもこの劣化
をなくすことが考えられるが、表面保護膜のピンホール
が生じやすいことや素子によっては絶縁膜の厚さに最適
値を持つ場合も考えられ、むやみに絶縁膜を薄くするこ
とができない。
It is also possible to eliminate this deterioration by reducing the total thickness of the insulating film, but pinholes may easily occur in the surface protective film, and depending on the element, the thickness of the insulating film may have an optimum value. Therefore, the insulating film cannot be made thinner unnecessarily.

このように、従来の多層構造の電極形成方法では半導体
素子の劣化を生じやすく信頼性を低下させるという欠点
があった。
As described above, the conventional method for forming electrodes with a multilayer structure has the disadvantage that semiconductor elements tend to deteriorate, reducing reliability.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記欠点を除去し、半導体素子の劣化
を防ぎ、信頼性奪向上させた多層構造の半導体素子用電
極の形成方法を提供することにめるO 〔発明の構成〕 本発明の半導体素子用電極の形成方法は、半導体基板上
に絶縁膜を形成し該絶縁膜にコンタクト用窓あけを行う
工程と、前記絶縁膜上及び窓上にレジスト膜を被着し前
記窓を内側に含むよ)大きな窓を前記レジスト膜に形成
する工程と、前記レジスト膜をマスクとして前記絶縁膜
を厚さ方向に部分エッチして前記絶縁膜に段差部を形成
する工程と、前記絶縁膜の窓と段差部に多層金属を被着
する工程とを含むことを特徴として構成される。
An object of the present invention is to provide a method for forming an electrode for a multilayered semiconductor device, which eliminates the above-mentioned drawbacks, prevents deterioration of the semiconductor device, and improves reliability. [Structure of the Invention] The present invention The method for forming an electrode for a semiconductor device includes the steps of forming an insulating film on a semiconductor substrate and forming a contact window in the insulating film, and depositing a resist film on the insulating film and the window, and forming the window on the inside. a step of forming a large window in the resist film; a step of partially etching the insulating film in the thickness direction using the resist film as a mask to form a stepped portion in the insulating film; The method is characterized by including a step of depositing a multilayer metal on the window and the stepped portion.

仁こで、前記多層金属層は、Ti、Pt、Pd及びWか
ら成る群から選ばれた少くとも二つの金属の層とAu層
とから構成される。
Preferably, the multilayer metal layer is composed of at least two metal layers selected from the group consisting of Ti, Pt, Pd, and W, and an Au layer.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.

第2図(a)〜(d)は本発明の第1の実施例を説明す
るための工程順に示した断面図である。
FIGS. 2(a) to 2(d) are sectional views shown in order of steps for explaining the first embodiment of the present invention.

まず、第2図(a)に示すように、半導体基板1上Kl
i!!IIi&膜2を設け、コンタクト用窓8をあけ、
半導体基板10表面を露出せしめる。次に、絶縁膜2及
び窓8の上にレジスト膜10を被着し、窓8管内側に含
み窓8より大きい慾9をレジスト膜10に形成する。
First, as shown in FIG. 2(a), Kl on the semiconductor substrate 1 is
i! ! IIi & membrane 2 is provided, contact window 8 is opened,
The surface of the semiconductor substrate 10 is exposed. Next, a resist film 10 is deposited on the insulating film 2 and the window 8 , and a groove 9 that is larger than the window 8 and is included inside the window 8 tube is formed in the resist film 10 .

次に、第2図(b)に示すように、レジスト膜1゜をマ
スクとして絶縁膜2の産出部分を厚さ方向に部分エッチ
して段差部7を形成する。
Next, as shown in FIG. 2(b), the produced portion of the insulating film 2 is partially etched in the thickness direction using the resist film 1° as a mask to form a stepped portion 7.

次に、第2図(C)K示すように、11層3.Pi層4
 、 A u層5を順次蒸着して多層金属層を形成する
Next, as shown in FIG. 2(C)K, 11 layers 3. Pi layer 4
, Au layers 5 are sequentially deposited to form a multilayer metal layer.

次に、第2図(d)に示すように、レジスト膜10を除
去することによりその上の11層3.Pt44、Au層
5を共に除去する。これによりコンタクト用窓8 K 
T i /P t /Au三層の電極を形成すゐことが
できる。
Next, as shown in FIG. 2(d), by removing the resist film 10, 11 layers 3. Both the Pt layer 44 and the Au layer 5 are removed. As a result, the contact window 8K
A three-layer electrode of T i /P t /Au can be formed.

このようにすれば、絶縁膜2を部分的に薄くするのみで
絶縁膜2のステップ6を小さくでき、1M層3.Pt層
4のステップ6における切断部を生ずることがなく、従
ってアニール時におけるAu原子の浸透を防止し、半導
体素子の劣化を防ぐことができる。
In this way, the steps 6 of the insulating film 2 can be made smaller by only partially thinning the insulating film 2, and the 1M layer 3. A cut portion in step 6 of the Pt layer 4 is not generated, so that penetration of Au atoms during annealing can be prevented and deterioration of the semiconductor element can be prevented.

第3図(a)〜(d)は本発明の第2の実施例を説明す
るための工程順に示した断面図である。
FIGS. 3(a) to 3(d) are cross-sectional views showing the steps in order to explain the second embodiment of the present invention.

まず、第3図(a)に示すように、半導体基板1の上に
絶縁膜2を形成し、コンタクト用窓8をあける0 次に、第3図(b)に示すようにルジスト膜10を全面
に被着し、窓8を内側に含み窓8より大きい窓9をレジ
スト膜10に形成する。そして絶縁膜2の露出部分を厚
さ方向に部分エッチして段差部7を形成する。
First, as shown in FIG. 3(a), an insulating film 2 is formed on a semiconductor substrate 1, and a contact window 8 is opened. Next, as shown in FIG. 3(b), a resist film 10 is formed. The resist film 10 is coated on the entire surface, and a window 9 including the window 8 inside and larger than the window 8 is formed in the resist film 10 . Then, the exposed portion of the insulating film 2 is partially etched in the thickness direction to form a stepped portion 7.

次に、第3図(C)に示すように、Ti層3.Pt層4
を順次被着し、レジスト膜10t−除去すると共にその
上のTi層とPt層を除去する。このリフトオフ法によ
って窓8にTi/Pt二層電極を形成することができる
Next, as shown in FIG. 3(C), a Ti layer 3. Pt layer 4
are sequentially deposited, and the resist film 10t is removed, and at the same time, the Ti layer and Pt layer thereon are removed. A Ti/Pt two-layer electrode can be formed on the window 8 by this lift-off method.

次に、第3図(d)に示すように、レジスト膜と蒸着と
リフトオフ法とを用いて、11層11 、 A u層5
を積層し、T I / P t / T i /A u
四層の電極を形成する。
Next, as shown in FIG. 3(d), using a resist film, vapor deposition, and lift-off method, 11 layers 11, Au layers 5
are stacked, T I / P t / T i / A u
Form a four-layer electrode.

この実施例も第1の実施例と同様に、ステップ60段差
を小さくしているから段差部での11層3、Pt層4の
切断は生じにくく、更に、Pt層4の上にはこれより面
積の小さいTi1iill、Au/15を形成してめる
のでアニール時におけるAuの浸透は阻止され、従って
半導体素子の劣化を防止できる。
In this embodiment, as in the first embodiment, since the step 60 step difference is made small, cutting of the 11th layer 3 and the Pt layer 4 at the step part is less likely to occur. Since Ti1iill and Au/15 are formed with a small area, penetration of Au during annealing is prevented, and therefore deterioration of the semiconductor element can be prevented.

上記二つの実施例では、電極用金属とじTi。In the above two embodiments, the metal binding material for the electrode is Ti.

Pt、Auを用いたが、一般にはTi、Pt、Pd及び
Wから成る群から選ばれた少くとも二つの金属の層とA
u層とで構成することができる。
Pt, Au, but generally at least two metal layers selected from the group consisting of Ti, Pt, Pd, and W;
It can be configured with a u layer.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、半導体素
子の劣化を防ぎ、信頼性を向上させた多層構造の半導体
菓子用電極を形成することができる0
As described in detail above, according to the present invention, it is possible to form a multilayer electrode for semiconductor confectionery that prevents deterioration of semiconductor elements and improves reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のTi/Pt/Au多層構造電極を有する
半導体素子の要部の断面図、第2図(a)〜(d)は本
発明の第1の実施例を説明するための工程順に示した断
面図、第3図(a)〜(d)は本発明の第2の実施例を
説明するための工程順に示した断面図である0 1・・・・・・半導体基板、2・・・・・・絶縁膜、3
・・・・・・Ti層、4・・・・・・Pt層、5・・・
・・・Au層、6・・・・・・ステップ、7・・・・・
・段差部、8.9・・・・・・窓、10・・・・・・レ
ジスト膜、11・・・・・・Tt層。 代理人 弁理士 内 原 晋 郷ZT¥] 第一5図
FIG. 1 is a sectional view of the main part of a semiconductor device having a conventional Ti/Pt/Au multilayer structure electrode, and FIGS. 2(a) to 2(d) are steps for explaining the first embodiment of the present invention. 3(a) to 3(d) are cross-sectional views shown in the order of steps for explaining the second embodiment of the present invention. 0 1... Semiconductor substrate, 2 ...Insulating film, 3
...Ti layer, 4...Pt layer, 5...
...Au layer, 6...step, 7...
- Step portion, 8.9...Window, 10...Resist film, 11...Tt layer. Agent Patent Attorney Shingo Uchihara ZT¥] Figure 15

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に絶縁膜を形成し咳絶縁膜にコンタ
クト用窓めけを行う工程と、前記絶縁膜上及び窓上にレ
ジスト膜を被着し前記窓を内側に含むより大きな窓を前
記レジス)Millに形成する工程と、前記レジスト膜
をマスクとして前記絶縁膜に段差部を形成する工程と、
前記絶縁膜の窓と段差部に多層金属層を被着する工程と
を含むことを特徴とする半導体素子用電極の形成方法。
(1) A step of forming an insulating film on a semiconductor substrate and forming a contact window in the insulating film, and depositing a resist film on the insulating film and the window, and forming a larger window including the window inside. a step of forming a step in the insulating film using the resist film as a mask;
A method for forming an electrode for a semiconductor device, comprising the step of depositing a multilayer metal layer on the window and step portion of the insulating film.
(2)多層金属層がTi、Pi、Pd及びWから成る群
から選ばれた少くと4二つの金員の層とAu層とから成
る特許請求の範H第(1)項記載の半導体素子用電極の
形成方法。
(2) The semiconductor device according to claim H (1), wherein the multilayer metal layer comprises at least four metal layers selected from the group consisting of Ti, Pi, Pd, and W and an Au layer. Method of forming electrodes for use.
JP1465284A 1984-01-30 1984-01-30 Formation of electrode for semiconductor element Pending JPS60160120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1465284A JPS60160120A (en) 1984-01-30 1984-01-30 Formation of electrode for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1465284A JPS60160120A (en) 1984-01-30 1984-01-30 Formation of electrode for semiconductor element

Publications (1)

Publication Number Publication Date
JPS60160120A true JPS60160120A (en) 1985-08-21

Family

ID=11867132

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1465284A Pending JPS60160120A (en) 1984-01-30 1984-01-30 Formation of electrode for semiconductor element

Country Status (1)

Country Link
JP (1) JPS60160120A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01123418A (en) * 1987-11-09 1989-05-16 Nec Corp Manufacture of semiconductor device
JPH0677222A (en) * 1992-05-27 1994-03-18 Nec Corp Semiconductor device
JP2009206357A (en) * 2008-02-28 2009-09-10 Asahi Kasei Electronics Co Ltd Compound semiconductor device and method for manufacturing compound semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5633855A (en) * 1979-08-29 1981-04-04 Toshiba Corp Semiconductor device and its manufacture
JPS58197818A (en) * 1982-05-14 1983-11-17 Hitachi Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5633855A (en) * 1979-08-29 1981-04-04 Toshiba Corp Semiconductor device and its manufacture
JPS58197818A (en) * 1982-05-14 1983-11-17 Hitachi Ltd Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01123418A (en) * 1987-11-09 1989-05-16 Nec Corp Manufacture of semiconductor device
JPH0677222A (en) * 1992-05-27 1994-03-18 Nec Corp Semiconductor device
JP2009206357A (en) * 2008-02-28 2009-09-10 Asahi Kasei Electronics Co Ltd Compound semiconductor device and method for manufacturing compound semiconductor device

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