JPS60219772A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60219772A JPS60219772A JP7702484A JP7702484A JPS60219772A JP S60219772 A JPS60219772 A JP S60219772A JP 7702484 A JP7702484 A JP 7702484A JP 7702484 A JP7702484 A JP 7702484A JP S60219772 A JPS60219772 A JP S60219772A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- oxide film
- heat treatment
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000008018 melting Effects 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 abstract description 9
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 7
- 238000005260 corrosion Methods 0.000 abstract description 5
- 230000007797 corrosion Effects 0.000 abstract description 5
- 239000002253 acid Substances 0.000 abstract description 4
- 150000007513 acids Chemical class 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- 229910052719 titanium Inorganic materials 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000637 aluminium metallisation Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
- H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、熱処理工程におげろ金属膜ゲート電極への
悪影響ケ除去した半導体装置の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device in which harmful effects on a metal film gate electrode are removed during a heat treatment step.
従来のこの種の半導体装置の一例を第１図によって説明
する。この図において、シリコン等の基板１の主面上に
熱酸化法等によりゲー）５１化膜２を形成し、続いてモ
リブデン（Ｍｏ）、タングステン（Ｗ）、タンタル（Ｔ
ａ）、チタン（Ｔｉ）等の高融点金属からなる金属膜を
スパッタリング法、ＣＶＤ法、加熱蒸着法など忙より形
成する。An example of a conventional semiconductor device of this type will be explained with reference to FIG. In this figure, a Ga) 51 film 2 is formed on the main surface of a substrate 1 made of silicon or the like by a thermal oxidation method or the like, and then molybdenum (Mo), tungsten (W), tantalum (T), etc.
a) A metal film made of a high melting point metal such as titanium (Ti) is formed by a sputtering method, a CVD method, a heating vapor deposition method, or the like.
次に、写真製版およびエツチング法により選択的に金属
膜ゲート電極３ａおよび配！１（図示は省略。Next, the metal film gate electrode 3a and the pattern are selectively etched by photolithography and etching. 1 (Illustration omitted.
以下の説明においても同じ）を形成する。続いて。The same applies in the following explanation). continue.
イオン注入法等により不純物を注入した後、熱処理にて
不純物拡散層４を形成する。また、金属膜ゲート電極３
ａの低抵抗化欠目的とした７二−リングを行う。その後
、例えばシリコン酸化膜からなる絶縁膜５を形成し、ｉ
Ｉｋ後に、写真製版およびエツチング法により所要個所
忙コンタクト穴を形成し、アルミニウム配ｍｅと電気的
接触をとる。After implanting impurities by ion implantation or the like, an impurity diffusion layer 4 is formed by heat treatment. In addition, the metal film gate electrode 3
Perform 7-2 ringing with the purpose of lowering the resistance of a. Thereafter, an insulating film 5 made of, for example, a silicon oxide film is formed, and i
After Ik, contact holes are formed at required locations by photolithography and etching to establish electrical contact with the aluminum metallization.
このよ５に従来の半導体装置では、金属膜ゲート電極３
ａか露出した状態で高温熱処理を行っていたＯ
しかるに、Ｍｏ、Ｗ等からなる金属膜ゲート電極３ａは
、耐酸化性、酸などに対する耐腐蝕性か劣る。特に、Ｍ
ｏ、Ｗ等をまその酸化物が揮発性７有し昇華しやすく、
酸化物の形成および酸尋による腐蝕はプルセスおよびデ
バイスの信頼性に悪影響を及ばず。したがって、Ｍｏ、
Ｗ等は安定な熱処理を行うのが困難で、また、使用され
る薬品なども制限されるという欠点があった。5. In conventional semiconductor devices, the metal film gate electrode 3
However, the metal film gate electrode 3a made of Mo, W, etc. has poor oxidation resistance and corrosion resistance against acids and the like. In particular, M
Oxides such as O, W, etc. have volatility 7 and easily sublimate.
Oxide formation and acid corrosion do not adversely affect the reliability of the pulses and devices. Therefore, Mo,
W and the like have disadvantages in that it is difficult to perform stable heat treatment, and the chemicals that can be used are also limited.
この発明は、上記のような欠点を改良するためＫなされ
たもので、金属膜全体を比較的薄い酸化膜（Ｓｔ、、Ｍ
）または窒化膜（Ｓｉ、Ｈ，膜）で覆い、金属膜を熱処
理工程における酸化物および酸などＫよる腐蝕から保護
し、安定でしかも信頼性の高いプル七スＶ！！現できる
半導体装置の製造方法ｌ提供すること７目的としている
。以下、この発明についＣＭ５Ｌ明する。This invention was made to improve the above-mentioned drawbacks, and the entire metal film is covered with a relatively thin oxide film (St, M
) or nitride film (Si, H, film) to protect the metal film from corrosion by K such as oxides and acids during the heat treatment process, making it stable and highly reliable. ! The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can be used to produce a semiconductor device. This invention will be explained below.
第２図（ａ）〜（ｆ）はこの発明の一笑施例の製造工程
を示す断面図で、まず、第２図（ａ）、（ｂ）Ｋ示すよ
うに従来と同様の方法で、基板１上にゲート酸化膜２、
その上Ｋ Ｍ ｏ ＋ Ｗ、Ｔ ｔ 、Ｔ ａ等の高融
点金属からなる金属膜３を形成する。次いで、金属膜３
のパター−ニングを行い、金属膜ゲート電極３ａｌｌ（
形成した後、イオン注入法により不純物を注入する。FIGS. 2(a) to 2(f) are cross-sectional views showing the manufacturing process of a simple embodiment of the present invention. First, as shown in FIGS. 2(a) and 2(b)K, the substrate is 1, a gate oxide film 2,
Furthermore, a metal film 3 made of a high melting point metal such as K Mo + W, T t , Ta, etc. is formed. Next, metal film 3
The metal film gate electrode 3all (
After the formation, impurities are implanted by ion implantation.
続いて、第２図（ｃ）に示すようＩｃｃＶＤ法あるいは
スパッタリング法により比較的薄い酸化膜または窒化膜
１′ｆ：全面に形成した後、第２図（ｄ）Ｋ示すように
酸化性雰囲気中で熱処理を行い、不純物拡散層４Ｙｔ形
成する。その後、従来法と同様に第２図（ｅ）Ｋ示すよ
うにシリコン窒化膜等の絶縁膜５を全面忙形成した後、
第２図（ｆ）Ｋ示すように所要の部分忙コンタクト穴ゲ
設げ、アルミニウム配置１１６と電気的接触ケとる。Next, as shown in FIG. 2(c), a relatively thin oxide film or nitride film 1'f is formed on the entire surface by IccVD method or sputtering method, and then it is deposited in an oxidizing atmosphere as shown in FIG. 2(d)K. A heat treatment is performed to form an impurity diffusion layer 4Yt. After that, as in the conventional method, as shown in FIG. 2(e)K, an insulating film 5 such as a silicon nitride film is formed on the entire surface.
As shown in FIG. 2(f)K, the required partial contact holes are drilled to make electrical contact with the aluminum arrangement 116.
このように金属膜ゲート電極３ａは、酸化膜または窒化
膜７で囲まれているので、酸化性雰囲気中においても安
定で、また、Ｍｏ、Ｗなどの金属膜３はフッ酸と硝酸の
混合液以外には腐蝕されないため、熱処理工程において
金属膜ゲート電極３ａケ保護する効果がある。Since the metal film gate electrode 3a is surrounded by the oxide film or nitride film 7 in this way, it is stable even in an oxidizing atmosphere, and the metal film 3 made of Mo, W, etc. Since other parts are not corroded, it has the effect of protecting the metal film gate electrode 3a during the heat treatment process.
なお、上記実施例では１％にゲート酸化膜２に直接金属
膜ゲート電極３ａとして、Ｍｏ、Ｗ等の高融点金Ｍｗ配
置した構造で説明を行ったが、他の方法としてゲート酸
化膜２上に単結晶シリコン等の膜を介して、Ｍｏ、Ｗ等
の高融点金属を配置した構造にも適用できることはもち
ろんである。In the above embodiment, the structure was explained in which high melting point gold Mw such as Mo or W was placed directly on the gate oxide film 2 as the metal film gate electrode 3a. Of course, the present invention can also be applied to a structure in which a high melting point metal such as Mo or W is placed through a film such as single crystal silicon.
また、金属膜ゲート電極３ａＫ限らず、高融点金属から
なる配線にも適用することができる。Moreover, it is applicable not only to the metal film gate electrode 3aK but also to wiring made of a high melting point metal.
以上説明したように、この発明は、Ｍｏ、Ｗ等の高融点
金属からなる金属膜ゲート電極および配線全体火種うよ
うに酸化膜または窒化膜ケ形成したので、Ｍｏ、Ｗ等の
金属膜ゲート電極および配線ケ薬品による腐蝕や酸化か
ら防ぎ、安定な半導体装置の製造プロセスが実現できる
効果が得られる。As explained above, in the present invention, since an oxide film or a nitride film is formed so as to cause ignition all over the metal film gate electrode and wiring made of a high melting point metal such as Mo or W, the metal film gate electrode such as Mo or W can be Also, it is possible to prevent wiring from corrosion and oxidation caused by chemicals, thereby achieving the effect of realizing a stable semiconductor device manufacturing process.
第１図は従来の半導体装置の製造方法を説明するための
断面図、第２図（ａ）〜（ｆ）はこの発明の一冥施例を
説明するための断面図である。
図中、１は基板、２はゲート酸化膜、３は金属膜、３ａ
は金属膜ゲート電極、４は不純物拡散層、５は絶縁膜、
６はアルミニウム配線、Ｔは酸化膜または窒化膜である
。
なお、図中の同一符号は同一または相当部分を示す。
代理人 大 岩増雄 （外２名）
第１図
第２図FIG. 1 is a sectional view for explaining a conventional method of manufacturing a semiconductor device, and FIGS. 2(a) to 2(f) are sectional views for explaining one embodiment of the present invention. In the figure, 1 is a substrate, 2 is a gate oxide film, 3 is a metal film, 3a
is a metal film gate electrode, 4 is an impurity diffusion layer, 5 is an insulating film,
6 is an aluminum wiring, and T is an oxide film or a nitride film. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Figure 1 Figure 2
Claims (1)
属からなる金属膜ゲート電極および配線か施された半導
体装置の製造方法において、前記金属膜ゲート電極およ
び配ｍ”ｉ形成後、全面に酸化膜または窒化膜欠形成し
た後、所要の熱処理を施す工ａＶ含むこと火特徴とする
半導体装置の製造方法。In a method for manufacturing a semiconductor device in which a metal film gate electrode made of a high melting point metal and wiring are selectively formed on a gate oxide film formed on a substrate, after forming the metal film gate electrode and wiring m"i, the entire surface is 1. A method of manufacturing a semiconductor device, comprising the step of performing a necessary heat treatment after forming an oxide film or a nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7702484A JPS60219772A (en) | 1984-04-16 | 1984-04-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7702484A JPS60219772A (en) | 1984-04-16 | 1984-04-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60219772A true JPS60219772A (en) | 1985-11-02 |
Family
ID=13622178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7702484A Pending JPS60219772A (en) | 1984-04-16 | 1984-04-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60219772A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2443220A (en) * | 2006-10-23 | 2008-04-30 | Toshiba Res Europ Ltd | Encapsulated single photon emission device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5650570A (en) * | 1979-10-01 | 1981-05-07 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS6092664A (en) * | 1983-10-26 | 1985-05-24 | Nec Corp | High melting point metallic gate mos type semiconductor device and manufacture thereof |
-
1984
- 1984-04-16 JP JP7702484A patent/JPS60219772A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5650570A (en) * | 1979-10-01 | 1981-05-07 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS6092664A (en) * | 1983-10-26 | 1985-05-24 | Nec Corp | High melting point metallic gate mos type semiconductor device and manufacture thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2443220A (en) * | 2006-10-23 | 2008-04-30 | Toshiba Res Europ Ltd | Encapsulated single photon emission device |
| GB2443220B (en) * | 2006-10-23 | 2011-10-26 | Toshiba Res Europ Ltd | A semiconductor device and method of its manufacture |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS61142739A (en) | Manufacture of semiconductor device | |
| JPS6190445A (en) | Semiconductor device | |
| JPS6364057B2 (en) | ||
| JPS62113421A (en) | Manufacture of semiconductor device | |
| JPS5910271A (en) | Semiconductor device | |
| JPS60219772A (en) | Manufacture of semiconductor device | |
| JPS59200418A (en) | Manufacture of semiconductor device | |
| JPH01160009A (en) | Manufacture of semiconductor device | |
| KR100186985B1 (en) | Manufacture of semiconductor device | |
| JPS6350042A (en) | Multilayer interconnection and electrode film structure | |
| JPS62291146A (en) | Manufacture of semiconductor device | |
| JPS6151941A (en) | Manufacture of electrode wiring film | |
| JPH041497B2 (en) | ||
| JP3189399B2 (en) | Method for manufacturing semiconductor device | |
| JPH05308057A (en) | Manufacture of semiconductor device | |
| KR0179826B1 (en) | Method of forming metal interconnector in semiconductor device | |
| JPS58155767A (en) | Manufacture of metal oxide semiconductor type semiconductor device | |
| JPS61228661A (en) | Semiconductor device and manufacture thereof | |
| JPH0349229A (en) | Semiconductor device | |
| KR19990003485A (en) | Metal wiring formation method of semiconductor device | |
| JPH06152001A (en) | Semiconductor device and its manufacture | |
| JPH01287963A (en) | Manufacture of semiconductor device | |
| JPH04340255A (en) | Semiconductor device and manufacture thereof | |
| JPS62122124A (en) | Manufacture of semiconductor device | |
| JPS5889869A (en) | Manufacture of semiconductor device |