GB2443220A

GB2443220A - Encapsulated single photon emission device

Info

Publication number: GB2443220A
Application number: GB0621099A
Authority: GB
Inventors: David Ellis; Mark Stevenson; Robert Young; Andrew James Shields
Original assignee: Toshiba Research Europe Ltd
Current assignee: Toshiba Europe Ltd
Priority date: 2006-10-23
Filing date: 2006-10-23
Publication date: 2008-04-30
Anticipated expiration: 2026-10-23
Also published as: GB2443220B; GB0621099D0

Abstract

The device comprises a quantum dot and a Bragg reflector 32 formed from III-V semiconductor layers. An encapsulating layer of SiN 36 surrounds the device layer structure which prevents desorption of semiconductor material or the electrostatic electrode pattern 37 being affected during high temperature annealing. A photonic cavity may be used to define an optical cavity and electrostatic electrodes may be used to select one quantum dot from an ensemble for device operation. The encapsulating layer may be removed to complete the device fabrication process. The device may operate by electrical or optical excitation.

Description

1 2443220 M&C Folio: GBP95569 Document: I2Uloo, A semiconductor device

and method of its manufacture The present invention relates to the field of optical devices and methods for their fabrication. Particularly, the present invention is concerned with single quantum dot devices and their properties.

Single InAs quantum dots have recently attracted increasing interest due to their suitability as the basis for photon emission technology for applications in quantum information A schematic of a generic type I quantum dot 10 is shown in Figure 1. Confinement for electrons and holes is provided by a potential well 11 in the conduction band 12 and valance band 13 respectively. The small size of the dots ensures that only two electrons 14, 15 and holes 16, 17 can be confined in the lowest energy level, as shown. The spins of the electrons and holes are opposite in accordance with the Pauli exclusion principle.

Due to spin conservation, only two radiative recombination paths 1, and 2 exist. in path I, the spin up electron 14 recombines with the spin down hole 16 to emit the first left-hand (L) polarised photon 18, leaving the spin down electron 15 to recombine with the spin up hole 17, to emit the second photon 19, which is right hand (R) circularly polarised. In path 2, the spin down electron 15 recombines first, so the first and second photons 18, 19 are R and L polarised respectively. In general the energies of the first and second photons 18, 19 are different due to the different coulomb energy associated with the two electron, two hole biexciton (XX) state, compared to the one electron one hole exciton (X) state.

The biexciton state in a quantum dot decays radiatively via the exciton state to the ground state, emitting a pair of photons. For the case when the exciton state is degenerate as shown in Figure 2(a), the photon pair states emitted can only be distinguished by their polarisation. Therefore, the photon pair emitted exist in a superposition state of the two different polarisation outcomes. This two photon state is known as a polarisation entangled state. The measurement of the polarisation of one of the photons will give a random result, but will set the polarisation of the other photon.

Such action at a distance has many uses, including in quantum information and quantum imaging.

In ordinary quantum dots however, structural properties of the dot such as elongation and strain cause in-plane asymmetry in the electron-hole exchange interaction, resulting in the lifting of the degeneracy of the intermediate exciton state, resulting in a polarisation dependent energy splitting S. For this case, shown schematically in Figure 2(b), the photons emitted have either linear horizontal, or linear vertical polarisation, and can also be distinguished by their emission energy. The photon pairs emitted are therefore not polarisation entangled, and only classically polarisation correlated.

Therefore it is important to be able to control S in order to realise an entangled photon pair Source.

A decrease of fine-structure splitting in InGa1..As quantum dots after annealing has been observed by W. Langbein et al. in: Physical Review B, Vol. 69, 161301(R), 1 April 2004.

Tartakoskii et al. have reported the effect of thermal annealing and strain engineering on the fine structure of quantum dot excitons in Physical Review B, Vol. 70, 193303, November 2005 In single InAs quantum dots Young et al. have observed a decrease and elimination of the energetic splitting of the horizontally and vertically polarised components of the exciton doublet with thermal annealing (Physical Review B, Vol. 70, 113305, 8 September 2005).

Finally Rastelli et a!. have used localised laser annealing of individual quantum dots to obtain a blue-shift of the emission energy (QD 2006, Chainonjx (France), I May 2006).

An optical device in accordance with a first aspect of the present invention comprises means to provide modulation in refractive index, a barrier layer comprising at least one quantum dot, means to restrict the active area of the device to comprise a limited number of said quantum dots and a coating provided surrounding and in contact with said optical device.

Said barrier layer may be provided overlying said means to provide modulation in refractive index. Said barrier layer may be in contact with said means to provide modulation in refractive index.

The quantum dots may be comprised of InXGa(l.X)As The means to provide modulation in refractive index may comprise a distributed Bragg reflector (DBR). The distributed Bragg reflector (DBR) may be provided as a chirped reflector.

The means to provide modulation in refractive index may comprise in-plane periodic refractive index modulation.

The device may be a source of single photons or photon pairs.

The device may be a source of entangled photon pairs.

The protective layer may be a layer of SIN.

The active area of the device may be defined by a metal layer comprising an aperture of small area.

The number of quantum dots may be limited by a patterned layer to control the placing of dots The active area of the device may be restricted by mesas of small area etched into the quantum dot layer.

The active area of the device may be restricted by an aperture within the device for restricting the area of current flow or of the photonic mode.

The device may further comprise a patterned metallic layer; and a further protective layer to prevent deformation of said patterned layer, when the metal melts during annealing.

The device may have been annealed at a temperature and duration so as to achieve desired optical properties.

In another aspect of the present invention a method of manufacturing a semiconductor device comprises the steps of forming means to provide modulation in refractive index, forming a cavity layer and at least one quantum dot located in said cavity layer; forming means to restrict the active area of the device to comprise a limited number of said quantum dots; and fotming a protective layer encapsulating said device to prevent desorption of the semiconductor material during annealing.

Said barrier layer provided may be formed overlying said means to provide modulation in refractive index. The barrier layer may be formed in contact with said means to provide modulation in refractive index.

The optical device may further be annealed to tune the operation wavelength and/or exciton splitting.

The step of forming the quantum dot layer may be a seif-organising growth process.

The step of annealing may occur after having formed the means for restricting the active area of the device.

The step of annealing may comprise annealing the device at a predetermined temperature for a predetermined duration.

The step of forming the means for restricting the active area may comprise forming a metal layer comprising apertures of small area.

The step of forming the means for restricting the active area may comprise forming mesas of small area into the quantum dot layer.

The step of annealing may comprise annealing the device at a temperature and duration required to achieve zero splitting of the bright exciton state of a quantum dot.

The step of annealing may comprise annealing the device at a temperature and duration required to achieve a desired quantum dot transition wavelength.

The step of annealing may comprise annealing the device at a temperature and direction required to achieve a desired separation of the exciton and biexciton transition of a quantum dot transition wavelength.

The method may further comprise the steps of forming a patterned metallic layer; and forming a second protective layer to prevent deformation of said pattern when the metal melts during annealing.

Further a patterned metallic layer may be formed; and a second protective layer may be formed to prevent deformation of said pattern when the metal melts during annealing.

Any feature in one aspect of the invention may be applied to another aspect of the invention, in any appropriate combination. In particular, apparatus features may be applied to method features and vice versa.

The present invention will now be described with reference to the following nonlimiting embodiments in which: Figure 1 depicts the photon pair emission by a quantum dot; Figure 2 illustrates classical versus entangled photon pair emission by a quantum dot; Figure 3 is a schematic of a planar device in accordance with an embodiment of the present invention; Figure 4 is a schematic of another planar device in accordance with a further embodiment of the present invention; Figure 5 is a schematic of a further device in accordance with a preferred embodiment of the present invention; Figure 6 is a schematic of another device in accordance with another embodiment of the present invention; Figure 7 is a schematic of a device with three-dimensional confinement in accordance with another preferred embodiment of the present invention; Figure 8 is a top view and cross section of a device providing three-dimensional confmement in accordance with an embodiment of the present invention; Figure 9(a) shows a top view of triangular pattern, with the size of the holes nearest to the cavity reduced; Figure 9(b) shows a top view of a so-called L3 defect; Figure 9(c) shows a top view of a H2 defect; Figure 9(d) shows a top view of a Si cavity.

Figure 10 is a schematic of an electrically driven device in accordance with another embodiment of the present invention; Figure 11(a) illustrates a schematic of another electrically driven device in accordance with the present invention before annealing; Figure 11(b) illustrates a schematic of a completed electrically device in accordance with the present invention; Figure 12 illustrates the observation of blue-shift in emission with annealing; Figure 13 shows the dependence of polarisation splitting on the annealing temperature.

Figure 14 (a) is a schematic of a device in accordance with a fUrther embodiment of the present invention during growth; Figure 14 (b) is a schematic of a completed device in accordance with a further embodiment of the present invention.

Figure 15 illustrates a schematic of a device in accordance with a further embodiment of the present invention.

Figure 16 shows a schematic of another device in accordance with a further embodiment of the present invention.

A quantum dot is a region that confines charge carriers in three dimensions. The quantum dots discussed here are preferably formed by the Stranski-Krastinow technique, which relies on the strain mismatch between semiconductor layers to form a highly strained thin quantum well, known as the wetting layer, which contains relaxed islands of material which form the quantum dots. In accordance with the present invention, quantum dots are preferably grown by MBE growth of a thin (advantageously about 1.6 monolayers) layer of lAs, on GaAs, followed by a GaAs cap. Quantum dots may also be grown in other material systems or by other growth methods.

The layer structure is advantageously fabricated by an epitaxial growth technique such as molecular beam epitaxy. However, other common crystal growth techniques and lattice-inatchetj techniques may be employed, e.g. metal organic vapour deposition. The structures in the embodiments discussed below are preferably fabricated on a semi- insulating GaAs substrate. However, other types of substrates may also be used.

A barrier layer is formed with a material having a larger bandgap than that of the material used to form quantum dots within the barrier. The barrier ensures confinement of electrons and holes within the quantum dots. In the case of InGaAs quantum dots, a barrier material of GaAs or A1XGa(l.X)As may advantageously be used.

It is advantageous for embodiments to include a cavity region, to confine optical modes close to the dot, which may increase the emission efficiency of a device. Though a cavity region may be formed separately to the barrier, usually, and for all embodiments described here, the cavity region also confmes electrons and holes to the quantum dots, and thus also provides a barrier means. In the following description, all cavity structures are also barrier means.

Modulations in refractive index reflect light. By selecting appropriate structures with said modulation in refractive index, it is possible to control the optical mode in devices.

This is advantageous for example to increase device efficiency, or reduce the photon emission time. A periodic variation (or modulation) in refractive index may e.g. be used to generate a high quality reflector. Also, modulations in refractive index that are quasi-periodic, i.e. which deviate slightly from precise periodicity, may be used.

In order to control various properties of single quantum dots, devices are annealed at a temperature of 675 C for several minutes. At these temperatures, devices will ordinarily be destroyed due to the decomposition of gallium arsenide (GaAs) by the desorption of arsenic (As), and also by the melting of metallic layers of the structure. The devices in accordance with the present invention are protected by an encapsulating coating, using a transparent insulation layer, for example silicon nitride (Si3N4).

Turning now to Figures 3 and 4, embodiments of basic planar structures in accordance with the present invention will be discussed.

A schematic of a device in accordance with a preferred embodiment is shown in Figure 3. Optical device 30 comprises means 32 to provide modulation in refractive index. A barrier layer 33 comprises at least one quantum dot 35. Barner layer 33 is provided overlying and in contact with said means to provide modulation in refractive index 32.

Optical device 30 further comprises means 37 to restrict the active area of the device to comprise a limited number of said quantum dots and a coating 36 provided surrounding and in contact with said optical device.

The semiconductor layers are grown by molecular beam epitaxy (MBE) on an undoped GaAs substrate 31. A bottom Distributed Bragg Reflector (DBR) 32 is provided as means to provide modulation in refractive index overlying and in contact with said substrate 31. Said bottom DBR 32 comprises 12 repeats of layers with alternating refractive index of approximately ?J4 thickness. Suitable materials are alternating layers of GaAs and Alo.9sGaoo2As, A GaAs cavity 33 is provided in the form of a barrier layer overlying and in contact with said bottom DBR 32.

The lower section of the cavity 33 is approximately A12 thick, followed by a wetting layer of InAs 34 close to the critical thickness for quantum dot island formation of around 1.6 monolayers. The upper section of the cavity, provided overlying and in contact with said wetting layer 34 is also approximately A/2 thick. Quantum dots 35 are formed by strain relaxation of wetting layer 34.

A metal film 37 is provided overlying and in contact with said GaAs cavity 33. Metal film 37 preferably consists of titanium and has a layer thickness of approximately nm. Apertures 38 of diameter of approximately 2 ixm are foreseen in said metal film 37.

An encapsulating coating 36 is provided surrounding and in contact with said layer structure fonning optical device 30. Said coating 36 will preferably be selected from insulating material. Advantageously, this material will be transparent A suitable coating may be obtained by encapsulation with silicon nitride (SiN), the stoichiometry of which is nominally S13N4, but is not too critical. Other suitable encapsulating materials, such as S1O2, may also be selected.

The device according to Figure 3 is manufactured as follows. The semiconductor sample is grown by molecular beam epitaxy (MBE) on an undoped GaAs substrate.

Following a GaAs buffer layer, a bottom distributed Bragg reflector (DBR) is deposited, consisting of 12 repeats of alternating approximately A/4 thick layers of GaAs and Alo.,8GaAs. Next, a GaAs optical cavity is deposited, incorporating a layer of indium arsenide (InAs) quantum dots at the centre. The lower section of the cavity is about A12 thick, followed by a layer of InAs close to the critical thickness for quantum dot island formation of around 1.6 monolayers, and then the upper section of the cavity, also approximately A/2 thick.

Standard photolithographic evaporation and lift-off technique is used to fabricate a metal film with apertures therein having a diameter of about 2 jLm. The photoresist used for this procedure may be Sl805, and the metal may be titanium thermally evaporated to be approximately 4Onm thick.

An approximately 5x5 mm chip is taken from the wafer, and encapsulated with silicon nitride (SiN), the stoichiomctiy of which was nominally Si3N4, but is not too critical.

This may be achieved by plasma enhanced chemical vapour deposition (PECVD) of S13N4 to the front face of the sample, while maintaining a substrate temperature of approximately 400 C. This is followed by similar steps to protect the rear face of the sample. The thickness of the Si3N4 layer is approximately 100 nm.

Figure 4 illustrates a variation of the device of Figure 3. To avoid unnecessary repetition, like reference numerals are used to denote like features. In the device of Figure 4, the semiconductor layers are grown by molecular beam epitaxy (MBE) on an undoped GaAs substrate 31. A bottom Distributed Bragg Reflector (DBR) 32 is provided as means to provide modulation in refractive index overlying and in contact with said substrate 31. Said bottom DBR 32 comprises 12 repeats of alternating layers of approximately J4 thickness of GaAs and Al0ç5Ga002As. A GaAs cavity 33 is provided in the form of a barrier layer overlying and in contact with said bottom DBR 32.

The lower section of the cavity 33 is approximately J2 thick, followed by a wetting layer of JnAs 34 close to the critical thickness for quantum dot island formation of around 1.6 monolayers. The upper section of the cavity, provided overlying and in contact with said wetting layer 34, is also approximately W2 thick.

An encapsulating coating 36 is then provided surrounding and in contact with said layer structure forming optical device 30. Said coating 36 will preferably be selected from insulating material. Advantageously, this material will be transparent A suitable coating may be obtained by encapsulation with silicon nitride (SiN), the stoichiometry of which is nominally Si3N4, but is not too critical. Other suitable encapsulating materials, such as Si02, may also be selected.

A metal film 37 is provided overlying and in contact with said encapsulating coating 36.

Metal film 37 preferably consists of titanium and has a layer thickness of approximately nm. Apertures 38 of diameter of approximately 2 tm are foreseen in said metal film 37.

A further encapsulating coating 39 is provided overlying and in contact with said metal film 37. Said coating 39 will preferably be selected from the same insulating material as encapsulation coating 36.

The device according to Figure 4 is manufactured as follows. The semiconductor sample is grown by molecular beam epitaxy (MBE) on an undoped GaAs substrate.

Following a GaAs buffer layer, a bottom distributed Bragg reflector (DBR) is deposited, consisting of 12 repeats of alternating approximately ?14 thick layers of GaAs and Alo.9sGaooAs. Next, a GaAs optical cavity is deposited, incorporating a layer of indium arsenide (InAs) quantum dots at the centre. The lower section of the cavity is approximately ?J2 thick, followed by a layer of InAs close to the critical thickness for quantum dot island formation of around 1.6 monolayers, and then the upper section of the cavity, also approximately ?J2 thick.

An approximately 5x5 mm chip is taken from the wafer, and encapsulated with silicon nitride (SiN), the stoichiometzy of which was nominally Si3N4, but is not too critical.

This may be achieved by plasma enhanced chemical vapour deposition (PECVD) of Si3N4 to the front face of the sample, while maintaining a substrate temperature of approximately 400 C. This is followed by similar steps to protect the rear face of the sample. The thickness of the Si3N4 layer is approximately 100 nm.

Standard photolithographic technique is used to define the surface area of encapsulating coating 36 for metal deposition, leaving apertures of approximately 2 m. A typical photoresist used for this procedure may be S1805. A metal film 37 is deposited overlying and in contact with said encapsulating coating 36. A preferred deposition technique is by evaporation. Advantageously, titanium is thermally evaporated to a thickness of approximately 40 nm. Other metals could also be used, preferably those with high melting points. Standard lift-off technique removes the metal film from the apertures.

A further encapsulating coating 39 is then deposited overlying and in contact with the metal film, providing a pattern protector for subsequent annealing steps.

Embodiments of planar structures with top reflectors in accordance with the present invention will now be described with particular reference to Figures 5 and 6.

In Figure 5, a schematic of a device in accordance with a preferred embodiment is shown. The semiconductor layers are grown by molecular beam epitaxy (MBE) on an undoped GaAs substrate 31. A bottom Distributed Bragg Reflector (DBR) 32 is provided overlying and in contact with said substrate 31. Said bottom DBR 32 comprises 12 repeats of alternating layers of approximately A/4 thickness of GaAs and A1o.9gGa02As. A GaAs cavity 33 is provided overlying and in contact with said bottom DBR 32.

The lower section of the cavity 33 is approximately A/2 thick, followed by a wetting layer of InAs 34 close to the critical thickness for quantum dot island formation of around 1.6 inonolayers. The upper section of the cavity 33, provided overlying and in contact with said wetting layer 34, is also approximately f2 thick. An upper DBR 40 consisting of 2 repeats is provided overlying and in contact with said upper section of said cavity 33.

An encapsulating coating 36 is provided surrounding and in contact with said layer structure 30. Said coating 36 will preferably be selected from insulating material.

Advantageously, this material will be transparent. A suitable coating may be obtained by encapsulation with silicon nitride (SiN), the stoichiometry of which is nominally Si3N4, but is not too critical. Other suitable encapsulating materials, such as Si02, may also be selected.

A metal film 37 having apertures 38 with a diameter of about 2 pm is then provided overlying and in contact with the top surface of said encapsulating coating 36. In the case of the JnGaAs system, titanium is a suitable material for fabricating said metal film 37. However, the metal may be replaced by another opaque metal, for example, nichrome (NiCr), or a titanium/gold bi-layer (Ti/Au). In the case of Ti/Au, it is preferable to use the Ti under-layer to prevent Au from difihising into the semiconductor. It is further possible to reduce the thickness of said metal layer 37 such that the metal becomes semi-transparent.

Finally, an encapsulating coating 39 is provided overlying and in contact with said metal layer 37.

The embodiment of the device according to the present invention as shown in Figure 5 is preferably manufactured as follows. The semiconductor sample is grown by molecular beam epitaxy (MBE) on an undoped GaAs substrate. Following a GaAs buffer layer, a bottom distributed Bragg reflector (DBR) is deposited, consisting of 12 repeats of alternating approximately ?14 thick layers of GaAs and Alo.9gGao.o2As. Next, a GaAs optical cavity is deposited, incorporating a layer of indium arsenide (InAs) quantum dots at the centre. The lower section of the cavity is approximately ?J2 thick, followed by a layer of InAs close to the critical thickness for quantum dot island formation of around 1.6 monolayers, and then the upper section of the cavity, also approximately)J2 thick. An upper DBR consisting of 2 repeats completes the growth phase of the device. A chip of suitable size, for example approximately 5x5 mm, is taken from the wafer, and encapsulated with silicon nitride (SiN), the stoichiometiy of which should nominally be Si3N4, but is not too critical. This may preferably be achieved by plasma enhanced chemical vapour deposition (PECVD) of SN to the front face of the sample, while maintaining a substrate temperature of approximately 400 C This is followed by similar steps to protect the rear face of the sample. The thickness of the SiN layer is preferably about 100 nm. Apertures of a preferred diameter of approximately 2 pin were fabricated in a metal film of titanium, by standard photolithographic evaporation and lift-off technique. The preferred photoresist used for this procedure is S1805, and the titanium is preferably thermally evaporated to be approximately 40 nm thick. The metal mask is protected by depositing an additional layer of SiN.

We note that many variations on this design exist. For example, SiN may be replaced by other transparent protective materials such as Si02. Also, the metal may be replaced by another opaque metal, for example, nichrome (NiCr), or a titanium/gold bi-layer (Ti/Au). In case of Ti/Au, it is preferable to use a Ti under-layer to prevent Au from difThsing into the semiconductor.

It is also possible to foresee the devices with so-called chirped layer sequences, as will now be discussed with reference to Figure 6.

As shown in Figure 6, as device according to an alternative embodiment has the same layer sequence as the embodiment already describe with reference to Figure 5. In the embodiment of Figure 6, however, the periodicity of the DBR mirror layers is adjusted in order to provide a means to provide quasi periodic variation in the refractive index. In this example, the individual layer thicknesses in DBR 32 increase from A/4.2 close to the cavity 33, to ?13.8 at the substrate or surface interface. It is noted that other variations of strongly, though not perfectly, periodic variation in refractive index are also possible.

The device as shown in Figure 6 is manufactured according to the method disclosed in connection with Figure 5. In the embodiment of Figure 6, however, the thickness of the individual DBR mirror layers is adjusted from layer to layer in order to provide quasi periodic variation in the refractive index. It is noted that other variations of strongly, though not perfectly, periodic variation in refractive index are also possible.

It may be desirable to provide devices with three-dimensional confinement. These will now be discussed with reference to Figures 7 to 9.

The device shown in Figure 7 is grown as described with reference to the embodiment of Figure 5. An etch mask is defined using standard photo-resist and development.

Other etch masks such as patterned metallic layers, or cross-linked PMMA are also preferred. The masked areas have diameters preferably in the range O.l-5tm. Pillars are etched using reactive ion etching, preferably to a depth of several microns, passing through the cavity layer, and some or all of the bottom DBR. With the cavity layer restricted to the horizontal dimensions of the pillar, three-dimensional confinement is thus achieved. Following this process, the etch mask is removed, and the device is coated with a protective layer, as described with reference to Figure 3.

In Figure 8, another embodiment of a device with three-dimensional confinement in accordance with the present invention is illustrated. Using MBE a sacrificial layer of AIGaAs 51, preferably Alo.9gGaAs of a thickness of approximately 500 rim, is fabricated on a GaAs substrate and buffer layer. Then, a GaAs waveguide barrier layer 33 is grown, incorporating anInAs quantum dot layer 34 close to the centre. The thickness of the wavegiiide layer is preferably 150 rim. A pattern of holes, with period and diameter of the order of the wavelength of light is written using standard electron beam lithography. A missing hole, or set of holes, defines a cavity region as means to select a limited number of dots. Reactive ion beam etching with S1CJ4 is then used to etch holes through to the sacrificial layer 51. The array of holes 50 in waveguide 33 forms a structure with periodic refractive index in-plane. The refractive index modulates between that of the holes, and that of the semiconductor. This array of holes contains a single missing hole, such that light is confined to the cavity region defined by the waveguide layer, and the missing hole. Thus the array of holes serves as means to provide modulation in refractive index, in this case interwoven with the waveguide layer 33, which acts as the barrier. The structure is protected with a coating as already described above in connection with Figure 3.

After annealing of the structure to tune properties of the dot, the protective layer is removed. For SIN, this is achieved by wet etching using phosphoric acid (H3P04) or buffered Hydrofluoric Acid (BHF), or by reactive ion etching using a fluorine-based chemistry, for example CF4/02 or CHF3. Finally, removal of the sacrificial layer under the holes is achieved by wet etching, for example using a solution of hydrochloric acid.

Alternatively, BHF may be used to remove both SiN and the sacrificial layer.

Other possibilities to obtain three-dimensiona confinement will be described with reference to Figure 9. Pattern configurations for array of holes 50 in Figure 8 other than the triangular (or hexagonal) array of holes with a single missing hole to define a cavity exist, as shown in Figure 9. Figure 9(a) shows a triangular pattern, with the size of the holes nearest to the cavity reduced. Figure 9(b) shows a so-called L3 defect, where the cavity is defined by three missing holes. Figure 9 (c) shows a H2 defect, where the cavity is defined by 7 missing holes. Finally, Figure 9 (d) shows an Si cavity, where the array is square rather than triangular, and one hole is missing.

Electrically driven devices as shown in Figures 10 and 11 have advantages in that they are more convenient to use than optically driven counterparts. However, with the high annealing temperatures required to control the properties of the dot, care must be taken to ensure that undesirable side effects, such as dopant diffusion, and melting of metallic components, are avoided. It is usually advantageous to apply the highest temperature processes first, so it is preferable to anneal as an intermediate step before completion of the device. Additionally, annealing by focussing a laser spot to a small area of the order of approximately I m could be used which would apply heat more locally, thereby protecting the device better.

The embodiment of an electrically device in accordance with the present invention is shown schematically in Figure 10. This device is grown as described with reference to the device of figure 5, except that the bottom DBR is p-type (doped using e.g. carbon) and the upper DBR is n-type (doped using e.g. silicon). Areas of diameter approximately 20 tm are isolated using standard photolithography and wet etching through the bottom p-doped layers. A recess is then fabricated in a similar way, down to the p-type layers. A metallic top layer is fabricated using titanium, with apertures to isolate emission from single dots. The layer also acts as an ohmic contact to the n-type region. Other aperture layer constructions more suited for ohmic contacts include goldIgermanJi.IpjckeJ. An ohmic contact to the p-type region is fabricated using an alloy of gold and beryllium (AuBe), or indium and zinc (InZn). The contacts are then bonded using metal wires preferably with high melting point, such as titanium, but more usually with gold. The entire device is then encapsulated in a protective layer, as already described above in connection with figure 3. High anneal temperatures are likely to have detrimental effects on the contact and doping regions of this device. Therefore, preferably annealing is achieved by a focussed laser beam through the aperture 38, which heats the sample over a smaller area.

Turning now to Figure 11, a bottom DBR is fabricated as described in figure 5. Then, an inhra-cavity contact layer 45 is fabricated using GaAs, preferably p-doped which may advantageously be obtained with beryllium. Said intra-cavity contact layer 45 is formed overlying and in contact with bottom DBR 32. The thickness of layer 45 is preferably about 200 mn. Following, the bottom section of the cavity 33 is fabricated overlying and in contact with said inter-cavity layer 45 so that the total thickness of cavity layer 33, plus the intra-cavity contact layer 45, is preferably approximately 2?. A layer 34 of quantum dots 35 is then grown in the maimer already described above, followed by the top section of cavity layer 33. A top DBR is then fabricated, which may preferably be n-doped, advantageously e.g. using silicon as dopant.

After growth, isolation mesas and pillars may be etched in the following way. First, using standard photolithography, mesas of preferably approximately 20 i.tm in diameter are defined, and etched using standard wet chemical etching. The depth of the etch should pass the p-type contact layer. Pillars are fabricated as described for figure 7, with the etch depth controlled to stop in the intra-cavity contact layer.

The device is then protected as described above, and annealed so that the required properties of the dot are achieved. The properties can be monitored by photoluminescence, or other characterisat ion techniques such as transmission or reflection.

After annealing, the protective layer is removed as described above, and the electrically driven device is finished. First an insulator, such as polyamide, is spun onto the device.

The insulator is then etched back to expose the top of the pillar. The insulator is then recessed to allow ohmic contact to the p-type intra-cavity layer with an alloy of gold and beryllium (AuBe). Then, a transparent ohmic contact to the n-type top of the pillar is made, using for example ITO. A metallic contact is then evaporated to provide a contact pad, and connection to the ITO ohmic.

Figure 14 shows another preferred embodiment of the device. The complete device (b) comprises a substrate 31 of GaAs, a bottom reflector 32, with modulating refractive index, cavity layer 33, and quantum dot 35. The device is protected by coating 36. The means to isolate a single dot is provided by an etched pit 52, as shown in (a).

The device of figure 14 is fabricated as follows. The layers of the structure are grown by MBE, and bottom reflector 32 is grown as described with reference to figure 5. The lower section of cavity layer 33 is then deposited, approximately A12 thick. Pit 52 (or array of pits) was then defined by c-beam lithography, and reactive ion etching using SiCL. Alternative, wet etching with 1:8:700 H2S04:H202:H20 can be used. Typical pit sizes are in the region 10-200 nm. Remaining resist is then removed. For PMMA this is achieved using solvents and plasma ash. The surface is cleaned with hydrogen plasma, and growth continued. A lOnm GaAs buffer layer is then deposited followed by an InAs dot layer. The under lying pit 52 causes dots to nucleate above, thus providing a means to limit the number of dots in the active region. The top section of the cavity is then deposited. The structure is finally protected as described with reference to figure 3.

Figure 15 shows a variation of the embodiment of the device in accordance with the present invention. Here, a partially oxidized AlGaj. As barrier layer is used to isolate a number of quantum dots within the device.

A schematic of a device in accordance with a preferred embodiment is shown in Figure 15. The semiconductor layers are grown by molecular beam epitaxy (MBE) on an undoped GaAs substrate 31. A bottom Distributed Bragg Reflector (DBR) 32 is provided overlying and in contact with said substrate 31. Said bottom DBR 32 comprises 12 repeats of alternating layers of approximately A14 thickness of GaAs and A1o.95GaijAs. A GaAs cavity 33 is provided overlying and in contact with said bottom DBR32.

The lower section of the cavity 33 is approximately A12 thick, followed by a wetting layer of InAs 34 close to the critical thickness for quantum dot island formation of around 1.6 monolayers. The upper section of the cavity 33, provided overlying and in contact with said wetting layer 34, is also approximately J2 thick. An AlGai.As barrier layer 55 is overlying and in contact with said upper section of said cavity 33, which is partially oxidised to form an annulus of aluminium oxide (AlOx) 56 around a core of A1Ga1..As 57. An upper DBR 40 consisting of 1 repeat is provided overlying and in contact with said upper section of said cavity 33.

The wafer is processed into mesa structures 58, with diameter usually in the range 10-lOOnm, and preferably 30jzm. Finally, an encapsulating coating 36 is provided overlying and in contact with the device.

The device according to Figure 15 is preferably manufactured as follows. The semiconductor sample is grown by molecular beam epitaxy (MBE) on an undoped GaAs substrate. Following a GaAs buffer layer, a bottom distributed Bragg reflector (DBR) is deposited, consisting of' 12 repeats of alternating 4J4 thick layers of GaAs and A1o.98Ga0.02As. Next, a GaAs optical cavity is deposited, incorporating a layer of indium arsenide (InAs) quantum dots at the centre. The lower section of the cavity is 412 thick, followed by a layer of InAs close to the critical thickness for quantum dot island formation of around 1.6 monolayers, and then the upper section of the cavity, also about)J2 thick. An AlGaj.As barrier layer is then deposited, consisting of an approximately /2 thick layer of AlGaAs, a -.10 nm layer of AlAs and an about ?J4 thick layer of Alo.,oGao.rnAs. An upper DBR consisting of 2 repeats completes the growth phase of the device. An approximately 5x5 mm chip is taken from the wafer.

Mesas are defined by standard photolithography and etched preferably to a depth of several microns, passing through the cavity layer, and some or all of the bottom DBR using either a 1:8:80 H2S04:H202:H20 solution or by reactive ion etching using SiC14.

The photoresist used for this procedure is S 1805. The etch mask is then removed and the AlGai..As barrier layer is then partially oxidjsed in from the sidewalls by exposure to steam in a furnace at about 400 -500 C. The chip is then encapsulated with silicon nitride as described with reference to figure 3.

We note that many variations on this design exist. A hard mask, such as SiN may be used in preference to resist as an etch mask. This need not be removed prior to oxidation. In addition the AlGai.As barrier layer may consist of a single layer of Aluminium-rich (typically x > 0.85) AlGai.As, or a superlattice of GaAs and AlGai..As, or a muftulayer structure similar to that described above but in which the compositions and layer thicknesses vary.

The device schematically shown in Figure 16 is grown as described for figure 5, except that the bottom DBR 32 is p-type (doped using e.g. carbon) and the upper DBR 40 is n-type (doped using e.g. silicon). Areas of a diameter of about I 5jtm are isolated using standard photolithography and etched using wet etching or reactive ion etching, to a depth passing through the cavity and stopping in the p-doped layers. Neighbouring mesas are then isolated in a similar way, etching through the bottom p-doped layers.

The AlGa.As barrier layer 55 is then partially oxidised in from the sidewalls by exposure to steam in a furnace at approximately 400 -500 C to isolate the dots by limiting current through the structure to only those dots close to the aperture. A ring contact layer metallic top layer is fabricated using a titanium layer, with openings 60 to allow the emission of light from the top of the structure. We note that the number of active dots is limited by the oxide aperture 57, not the ring contact 59. The layer 59 makes an ohmic contact to the n-type region. Other aperture layer constructions more suited for ohmic contacts include gold/germaniumlnickel. An ohmic contact to the p-type region is fabricated using an alloy of gold and beryllium (AuBe), or indium and zinc (JnZn). The contacts are then bonded using metal wires preferably with high melting point, such as titanium, but more usually with gold. The entire device is then encapsulated in a protective layer, as described for figure 5. High anneal temperatures are likely to have detrimental effects on the contact and doping regions of this device.

Therefore, preferably annealing is achieved by a focussed laser beam through the current aperture 57, which heats the sample over a smaller area.

We note that many variations of these embodiments and the methods of their manufIcture exist. For example, Si3N4 may be replaced by other transparent protective materials such as SiC)2. Also, the metal may be replaced by another opaque metal, for example, nichiome (NiCr), or a titanium/gold bi-layer (Ti/Au). In case of Ti/Au, it is preferable to use the Ti under-layer to prevent Au from diffusing into the semiconductor.

Although described with reference to distributed Bragg reflectors, the means to provide modulation in refractive index may comprise photonic crystal mirrors. The photonic crystal mirror may comprise a chirped mirror.

Moreover, the cavity thickness may be different thickness than Other preferred thicknesses include n Xf2, where n is an integer.

With reference to Figure 12, the observation of blue-shift in emission with annealing will be discussed next. The sample was cooled to approximately 10 K in a continuous flow helium cryostat. Photoluminescence (PL) of a quantum dot was excited by focussing a laser spot onto the sample suthce using a microscope objective lens. The same lens was used to collect the emitted light, which was dispersed by a grating spectrometer, and measured by a charge couple device (CCD) camera. The PL spectra for a quantum dot A' was recorded after a series of 5 minute annealing treatments, and shown in Figure 12. The annealing was performed using a rapid thermal annealer, at a temperature of 675 C. The dotted line, shown as a guide to the eye, highlights a significant blue-shift of the quantum dot emission lines after repeated aimeal steps.

Therefore in this way, it is possible to tune single quantum dot devices to a desired operation wavelength. Three strong lines are seen in all spectra, corresponding to the exciton (X), biexciton (2X) and positively charged exciton (X+). We can observe that annealing changes the relative energies of these lines. For example, after annealing, the 2X line shifts from the higher to lower energy side of the X line, and the separation between the X+ and X decreases. This may also be useful in device fabrication, for example to enable the X and 2X photons to be emitted at the same wavelength. Finally, we note for this, and many other dots, the relative intensity of X+ is suppressed after annealing, which might be due to a reduction in the effectiveness of charge traps, and which consequently should improve the efficiency of the X emission.

Figure 13 shows the dependence of polarisation splitting on the annealing time. Though tuning the emission energies of a quantum dot is important for many applications, it is the control of the polarisation splitting S that is crucial in order to realise and entangled photon source. If the splitting S is not sufficiently small, i.e. within the homogeneous linewidth of the emission of approximately 2.teV, then photons can be identified by energy as well as polarisation, destroying entanglement. To investigate the effect of annealing on a single quantum dot B', we plot the linear polarisation dependent X and 2X emission after a series of annealing steps in Figure 8(a), as a function of the detuning from the average horizontally polarised X and 2X emission energies, respectively. The polarisation splitting of the 2X emission lines is seen to be equal and opposite to that of the X emission lines. This is to be expected, since in both cases it is the splitting of the exciton state that governs the polarisation splitting of the emitted photons. As the total anneal time increases, the splitting reduces, until for the longest anneal time, the order of the H polarised (black) and V polarised (dotted) lines is reversed, indicating that the exciton splitting has been reduced through zero.

The exciton splitting, determined by averaging the results obtained from the exciton and biexciton emission in order to remove systematic errors, is plotted as a function of exciton energy, which increases with anneal time, for both dots A' and B' in Figure 8(b). A smooth reduction in the splitting is observed for both dots, in both cases crossing zero on the vertical axis, indicating that the splitting has been reduced to zero during the annealing process. In fact, for both dots we have measured the splitting to be zero within experimental error, indicated by the points for which the horizontal S=O line intersects the error bars.

In accordance with the present invention, annealing may be performed using an oven, a rapid thermal annealer, a laser, or any other suitable device. The device will typically be annealed at a predetermined temperature for a predetermined duration. Various characteristics of the device may be tuned by suitable annealing. The device may be annealed at a temperature and duration required to achieve zero splitting of the bright exciton state of a quantum dot. It is also possible to anneal the device at a temperature and duration required to achieve a desired quantum dot transition wavelength. The device may also be annealed at a temperature and direction required to achieve a desired separation of the exciton and biexciton transition of a quantum dot transition wavelength. Finally, a desired separation of the exciton and biexciton transition of a quantum dot transition wavelength may be achieved by annealing the device at a suitable temperature and duration.

For a single photon source, the annealing according to the present invention may be used to tune the emission wavelength to a desired value or to coincide with a cavity mode. For an entangled photon source, the annealing according to the present invention may be used to cancel the exciton polarisation splitting, as required to generate entangled photons. For a quantum memory device, the annealing according to the present invention may be used to tune the quantum dot absorption wavelength to that of the photonic qubits.

It will be understood that the invention has been described above purely by way of example, and modifications of detail can be made within the scope of the invention.

Each feature disclosed in the description and (where appropriate) the claims and drawings may be provided independently or in any appropriate combination.

Claims

CLAIMS: I. An optical device comprising: a means to provide modulation

in refractive index; a barrier layer comprising at least one quantum dot; a means to restrict the active area of the device to comprise a limited number of said quantum dots; and a coating provided surrounding and in contact with optical device.
2. The device according to claim 1, wherein the quantum dots are comprised of InGai..As.
3. The device according to any one of claims I or 2, wherein the means to provide modulation in refractive index comprise a distributed Bragg reflector (DBR).
4. The device according to any of the preceding claims, wherein the means to provide modulation in refractive index comprise photonic crystal mirrors.
5. The device according to claim 4, wherein the mirror periodicity is chirped.
6. The device according to any of the preceding claims, wherein the device is a source of single photons or photon pairs.
7. The device according to any one of the preceding claims, wherein the device is a source of entangled photon pairs.
8. The device according to any one of the preceding claims, wherein the protective layer is a layer of SIN.
9. The device according to any one of the preceding claims, wherein the active area of the device is defined by a metal layer comprising an aperwre of small area.
10. The device according to any one of the preceding claims, wherein the means to limit the number of quantum dots is provided by a patterned layer beneath the dot to encourage fonnation of dots at predetermined positions.
11. The device according to any one of the preceding claims, wherein the active area of the device is restricted by mesas of small area etched into the quantum dot layer.
12. The device according to any one of the preceding claims, wherein the active area of the device is restricted by an aperture within the device for restricting the area of current flow or of the photonic mode.
13. The device according to any one of the preceding claims, wherein the device further comprises: a patterned metallic layer; a further protective layer to prevent deformation of said patterned layer, when the metal melts during annealing.
14. The device according to any one of the preceding claims, wherein the device has been annealed at a temperature and duration so as to achieve desired optical properties.
15. A method of manufacturing a semiconductor device, said method comprising the steps of: forming means to provide modulation in refractive index; forming a barrier layer and at least one quantum dot located in said barrier layer; forming means to restrict the active area of the device to comprise a limited number of said quantum dots; and forming a protective layer encapsulating said device to prevent desorption of the semiconductor material during annealing.
16. The method according to claim 15, further comprising the step of annealing the optical device to tune the operation wavelength and/or exciton splitting.
17. The method according to any one of claims 15 or 16, wherein the step of forming the quantum dot layer is a seif-organising growth process.
18. The method according to any one of claims 15 to 17, wherein the step of annealing occurs after having formed the means for restricting the active area of the device.
19. The method according to any one of claims 15 or 18, wherein the step of annealing comprises annealing the device at a predetermined temperature for a predetermined duration.
20. The method according to any one of claims 15 to 19, wherein the step of forming the means for restricting the active area comprises forming a metal layer comprising apertures of small area.
21. The method according to any one of claims 15 to 20, wherein the step of forming the means for restricting the active area comprises forming mesas of small area into the quantum dot layer.
22. The method according to any one of claims 15 to 21, wherein the step of annealing comprises annealing the device at a temperature and duration required to achieve zero splitting of the bright exciton state of a quantum dot.
23. The method according to any one of claims 15 to 21, wherein the step of annealing comprises annealing the device at a temperature and duration required to achieve a desired quantum dot transition wavelength.
24. The method according to any one of claims 15 to 21, wherein the step of annealing comprises annealing the device at a temperature and duration required to achieve a desired separation of the exciton and biexciton transition of a quantum dot transition wavelength.
25. The method according to any one of claims 15 to 24, wherein the method further comprises the steps of: forming a patterned metallic layer; and fonning a second protective layer to prevent deformation of said pattern when the metal melts during annealing.