JPH01160009A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01160009A
JPH01160009A JP31926487A JP31926487A JPH01160009A JP H01160009 A JPH01160009 A JP H01160009A JP 31926487 A JP31926487 A JP 31926487A JP 31926487 A JP31926487 A JP 31926487A JP H01160009 A JPH01160009 A JP H01160009A
Authority
JP
Japan
Prior art keywords
film
tisix
tin
diffusion layer
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31926487A
Other languages
Japanese (ja)
Inventor
Hideyuki Kojima
秀之 兒嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP31926487A priority Critical patent/JPH01160009A/en
Publication of JPH01160009A publication Critical patent/JPH01160009A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To interpose a TiN film between a TiSiX film and Al with giving no bad influence on the film and a device by injecting ions of a material, which does not change a film quality such as conductivity of TiSiX, into the TiSiX film part which is to be changed into the TiN film, so as to destroy its crystalline property for being made amorphous followed by giving heat treatment in a nitrogen atmosphere in order to form the TiN film. CONSTITUTION:Silicon ions (Si<+>) are implanted from the upper surface to destroy a crystal of a TiSiX film inside an electrode window 17 for being made an amorphous titan silicide (alpha-TiSiX) film 21. As for ion implantation conditions the acceleration voltage is 70keV, and a does amount 5X10<15>/cm<2>. Next, when heat treatment is performed in a nitrogen atmosphere at 900 deg.C, for about 10min, the alpha-TiSiX film 21 is converted into a TiN film 21'. At this time, since the temperature of its heat treatment is a relatively low besides the time being short, a TiSiX film 15 can bear the temperature and time, and reaction of the TiSiX film 15 to a diffusion layer 13 due to changed film quality and destruction of p-n junction excluded, and the junction of a metal diffusion layer, where the TiSiX films are piled up, and an Al wiring is favorably performed without deteriorating the device characteristics so that wiring resistance can be lowered by reducing contact resistance.

Description

【発明の詳細な説明】 [概要] 半導体装置の製造方法のうち、電極配線の形成方法に関
し、 TiSix膜とデバイスとに悪影響を与えることな(、
TiSix膜とAI (アルミニウム)との間にTiN
膜を介在させることを目的とし、 チタンシリサイド(TiSix ) II!を重ねた拡
散層の上に絶縁膜を被覆し、該絶縁膜を窓開けして前記
チタンシリサイド膜を電極窓内に露出させる工程、次い
で、前記電極窓内に露出したチタンシリサイド膜にイオ
ン注入してアモルファス化し、アモルファスチタンシリ
サイド膜を形成する工程、次いで、窒素雰囲気中で熱処
理して前記アモルファスチタンシリサイド膜をチタンナ
イトライド(TiN)膜に変成する工程が含まれてなる
ことを特徴とする。
[Detailed Description of the Invention] [Summary] Among the methods for manufacturing semiconductor devices, there is a method for forming electrode wiring that does not adversely affect the TiSix film and the device.
TiN between TiSix film and AI (aluminum)
For the purpose of interposing a film, titanium silicide (TiSix) II! A step of coating an insulating film on the overlapping diffusion layer, opening a window in the insulating film to expose the titanium silicide film within the electrode window, and then implanting ions into the titanium silicide film exposed within the electrode window. The method is characterized by comprising the steps of: converting the amorphous titanium silicide film into amorphous material to form an amorphous titanium silicide film; and then heat-treating the amorphous titanium silicide film in a nitrogen atmosphere to transform the amorphous titanium silicide film into a titanium nitride (TiN) film. .

[産業上の利用分野] 本発明は半導体装置の製造方法のうち、電極配線の形成
方法に関する。
[Industrial Field of Application] The present invention relates to a method of forming electrode wiring among methods of manufacturing a semiconductor device.

ICやLSIなどの半導体装置は益々高密度化。Semiconductor devices such as ICs and LSIs are becoming increasingly dense.

高集積化され、それに伴って電極配線も微細化されてい
るが、電極配線の微細化は配線抵抗の増大をきたし、現
在、この配線抵抗を低下させるための検討が続けられて
いる。
As integration becomes higher, the electrode wiring becomes finer, but the finer electrode wiring leads to an increase in wiring resistance, and studies are currently being carried out to reduce this wiring resistance.

[従来の技術と発明が解決しようとする問題点]半導体
装置の配線材料として、近年、タングステンシリサイド
、モリブデンシリサイF′、白金シリサイドやチタンシ
リサイドなどの高融点金属シリサイドが用いられており
、これは従前からの導電性多結晶シリコンと比べて電気
抵抗が低い利点があるからである。
[Prior art and problems to be solved by the invention] In recent years, high melting point metal silicides such as tungsten silicide, molybdenum silicide F', platinum silicide, and titanium silicide have been used as wiring materials for semiconductor devices. This is because it has the advantage of lower electrical resistance than conventional conductive polycrystalline silicon.

一方、半導体装置が微細化され、半導体基板内に設ける
不純物拡散層も低濃度な浅い層になるために抵抗の増加
をきたし、その拡散層を低抵抗化するために拡散層にチ
タンシリサイドを重ね合わせた構造とその形成法が提案
されている。それはチタン(Ti)がシリコン基板や絶
縁膜との密着性が良く、且つ、チタンシリサイド(Ti
Six )はシリサイドの中で最も電気抵抗が低いため
に考案された方式で、そのように構成すれば拡散層を低
抵抗化することができる。
On the other hand, as semiconductor devices become smaller, the impurity diffusion layer provided in the semiconductor substrate also becomes a shallow layer with a low concentration, resulting in an increase in resistance.In order to lower the resistance of the diffusion layer, titanium silicide is layered on the diffusion layer. A combined structure and its formation method are proposed. This is because titanium (Ti) has good adhesion to silicon substrates and insulating films, and titanium silicide (Ti
Six) is a method devised because it has the lowest electrical resistance among silicides, and if configured in this way, it is possible to lower the resistance of the diffusion layer.

第2図はそのTiSi2を拡散層に重ねて低抵抗化した
メタル拡散層の例を示している。図中、■はp型シリコ
ン基板、2はゲート絶縁膜、3はゲート電極、4は絶縁
膜、5はn型ソース層、6はn型ドレイン層、7はアル
ミニウム(八1)電極配線であるが、n型ソース層5お
よびn型ドレイン層6に重ねたTiSixからなるメタ
ルソース層8およびメタルドレイン層9が設けられてお
り、この構成によって拡散層が低抵抗化される。尚、こ
のTiSix層はシリコン基板にTi膜をスパック法で
被着し、窒素中の500〜600°Cにおいて高速アニ
ールすると形成される。
FIG. 2 shows an example of a metal diffusion layer in which resistance is reduced by overlapping TiSi2 on the diffusion layer. In the figure, ■ is a p-type silicon substrate, 2 is a gate insulating film, 3 is a gate electrode, 4 is an insulating film, 5 is an n-type source layer, 6 is an n-type drain layer, and 7 is an aluminum (81) electrode wiring. However, a metal source layer 8 and a metal drain layer 9 made of TiSix are provided over the n-type source layer 5 and n-type drain layer 6, and this structure lowers the resistance of the diffusion layer. Incidentally, this TiSix layer is formed by depositing a Ti film on a silicon substrate by a spackle method and then performing high-speed annealing at 500 to 600° C. in nitrogen.

ところが、このTiSixとAI電極とのコンタクト(
接続)部(第2図において、10はコンタクト部を示す
)が問題であり、TiSixとA1とを接触させて温度
400〜500℃の低温度でアニール(熱処理)すると
両者が著しく反応して合金化し、そのために近接した拡
散層と基板とのpn接合部が影響され、pn接合に欠陥
が生じてリーク電流が増大し、且つ、TiSixと八1
との接触部で接触抵抗が増加すると云う欠点がある。
However, the contact between this TiSix and the AI electrode (
The problem is the connection part (10 indicates the contact part in Figure 2), and when TiSix and A1 are brought into contact and annealed (heat treated) at a low temperature of 400 to 500 degrees Celsius, the two react markedly and form an alloy. This affects the pn junction between the nearby diffusion layer and the substrate, causing defects in the pn junction and increasing leakage current.
There is a drawback that contact resistance increases at the contact point with.

従って、現在、TiSixとAIとの間に、バリアメタ
ル(拡散防止膜)としてチタンナイトライド(窒化チタ
ン; TiN (Titan  N1tride))膜
を介在させる方法が考案されており、次に、そのT j
N l!Jを介在させてAl/TiN配線を形成する従
来の形成方法を説明する。
Therefore, a method is currently being devised in which a titanium nitride (TiN (Titan N1tride)) film is interposed as a barrier metal (diffusion prevention film) between TiSix and AI.
Nl! A conventional method of forming an Al/TiN wiring with J interposed therein will be described.

第3図(al〜(g+はメタル拡散層にAl/TiN配
線を接続する従来の形成方法の工程順断面図を示してお
り、順を追って説明すると 第3図(al参照;まず、p型シリコン基板11上に公
知のLOCO3法によってフィールド絶縁膜12を形成
した後、砒素イオンを注入し、熱処理炉で熱処理(アニ
ール)してn型拡散層13(膜厚2500〜3500人
)を形成する。
Figure 3 (al~(g+) shows a step-by-step cross-sectional view of the conventional forming method for connecting Al/TiN wiring to a metal diffusion layer. After forming a field insulating film 12 on a silicon substrate 11 by the well-known LOCO3 method, arsenic ions are implanted and heat-treated (annealed) in a heat treatment furnace to form an n-type diffusion layer 13 (film thickness: 2,500 to 3,500 layers). .

第3図[b)参照;次いで、スパッタ法によりTi膜1
4(膜厚600人前後)を被着する。
See FIG. 3 [b); Next, the Ti film 1 is formed by sputtering.
4 (film thickness around 600 people).

第3図(C)参照;次いで、窒素中で500〜600°
Cにおいてランプアニール等によって高速アニールする
。そうすると、Ti膜14と基板11とが反応してTi
Six膜15が形成されるが、その際、フィールド絶縁
膜上など、シリコン基板と接していない部分のTi膜1
4はTiN膜14′に変化する。
See Figure 3(C); then 500-600° in nitrogen.
At C, high-speed annealing is performed by lamp annealing or the like. Then, the Ti film 14 and the substrate 11 react and the Ti film 14 reacts with the substrate 11.
The Six film 15 is formed, but at this time, the Ti film 1 on the part not in contact with the silicon substrate, such as on the field insulating film, is formed.
4 changes into a TiN film 14'.

第3図Fdl参照;次いで、そのTiN膜14′を過酸
化水素とアンモニアとの混合液、または過酸化水素と硫
酸との混合液によってエツチング除去する。
Refer to FIG. 3 Fdl; Next, the TiN film 14' is etched away using a mixture of hydrogen peroxide and ammonia or a mixture of hydrogen peroxide and sulfuric acid.

第3図tel参照;次いで、絶縁膜16(膜厚0.3〜
0.4 μm)を被着し、フォトプロセスを用いて旧配
線を接続するための1μm角程度の電極窓17を窓開け
する。
Refer to tel in FIG. 3; Next, insulating film 16 (thickness 0.3~
0.4 .mu.m), and a photo process is used to open an electrode window 17 of about 1 .mu.m square for connecting the old wiring.

第3図(fl参照;次いで、上面に反応性スパッタ法に
よってTiN膜18(膜厚1000Å以下)を被着し、
更に、その上にスパッタ法によって旧膜19(膜厚30
00Å以上)を被着する。
FIG. 3 (see fl; next, a TiN film 18 (film thickness of 1000 Å or less) is deposited on the upper surface by reactive sputtering,
Furthermore, the old film 19 (thickness 30
00 Å or more).

第3図Fgl参照;次いで、フォトプロセスを用いて、
上面にレジスト膜20をマスクし、塩素系ガスを用いた
りアクティブイオンエツチング(RI E)によってA
I膜19およびTiN膜18をパターンニングしてTi
N膜を介したAI配線を形成し、最後にしシスト膜20
のマスクを有機溶剤で剥離除去する。
See Figure 3 Fgl; then, using a photo process,
A resist film 20 is masked on the upper surface, and A is etched using chlorine-based gas or active ion etching (RIE).
By patterning the I film 19 and the TiN film 18,
AI wiring is formed through the N film, and finally the cyst film 20 is formed.
Remove the mask using an organic solvent.

なお、第3図(glは第3図(f)の電極窓部のFF断
面図(第3図(f)に垂直な断面図)を示している。
Note that FIG. 3 (gl indicates an FF sectional view (a sectional view perpendicular to FIG. 3(f)) of the electrode window portion of FIG. 3(f).

ところが、上記の形成方法において、^1/TiN膜を
パターンニングするためのエツチング除去が非常に難し
く、溶液中ではΔlの電位がTiNの電位より低いため
に電池反応が生じて、レジスト膜の剥離除去の際にAI
が有機溶剤液に溶解して、AI配線が所定形状に精度良
く形成されないと云う問題がある。
However, in the above formation method, it is very difficult to remove the etching for patterning the ^1/TiN film, and because the potential of Δl is lower than the potential of TiN in the solution, a cell reaction occurs and the resist film peels off. AI during removal
There is a problem in that the AI wiring cannot be formed in a predetermined shape with high accuracy due to dissolution in the organic solvent solution.

一方、他の方法として、メタル拡散層を形成し、絶縁膜
を被覆して電極窓17を窓開けした後、窒素雰囲気中で
熱処理して電極窓内にTiN膜を生成する方法が考えら
れる。しかし、このTiN膜を被着せずに、窒素(N)
中でTiN膜を生成する方法は、その熱処理が950℃
以上、30分程度の高温長時間が必要になり、そのよう
な高温度で長時間熱処理するとTiSix膜15が膜数
5と反応して拡散層を浸食し、甚だしい場合はpn接合
を破壊することになる。即ち、物質の熱処理温度は溶融
点×0.6程度が最高処理温度であり、TiSix膜の
場合はそれが860℃程度であるから、それより高く加
熱すると反応が激しく、TiSix膜とデバイスが破壊
される。
On the other hand, as another method, a method can be considered in which a metal diffusion layer is formed, an insulating film is covered, the electrode window 17 is opened, and then a TiN film is generated in the electrode window by heat treatment in a nitrogen atmosphere. However, without depositing this TiN film, nitrogen (N)
The method for producing a TiN film inside is that the heat treatment is at 950°C.
As mentioned above, a high temperature and long time of about 30 minutes is required, and if the heat treatment is carried out at such a high temperature for a long time, the TiSix film 15 will react with the film number 5 and erode the diffusion layer, and in severe cases, the pn junction will be destroyed. become. In other words, the maximum heat treatment temperature for a substance is approximately 0.6 times the melting point, and in the case of a TiSix film, it is approximately 860°C, so heating higher than that will cause a violent reaction and destroy the TiSix film and device. be done.

本発明は上記の問題点を解消させて、TiSix膜とデ
バイスとに悪影響を与えることなく TiSix膜とA
Iとの間にTiN膜を介在させることを目的とした形成
方法を提案するものである。
The present invention solves the above problems and allows the TiSix film and A
This paper proposes a formation method for the purpose of interposing a TiN film between the TiN film and the TiN film.

[問題点を解決するための手段] その目的は、チタンシリサイド(TiSix )膜を重
ねた拡散層の上に絶縁膜を被覆し、該絶縁膜を窓開けし
て前記チタンシリサイド膜を電極窓内に露出させる工程
、次いで、前記電極窓内に露出したチタンシリサイド膜
にイオン注入してアモルファス化し、アモルファスチタ
ンシリサイド膜を形成する工程、次いで、窒素雰囲気中
で熱処理して前記アモルファスチタンシリサイド膜をチ
タンナイトライド(TiN)膜に変成する工程が含まれ
る半導体装置の製造方法によって達成される。
[Means for solving the problem] The purpose is to coat an insulating film on a diffusion layer in which a titanium silicide (TiSix) film is stacked, open a window in the insulating film, and insert the titanium silicide film into the electrode window. Next, a step of implanting ions into the titanium silicide film exposed in the electrode window to make it amorphous to form an amorphous titanium silicide film, and then heat-treating the amorphous titanium silicide film in a nitrogen atmosphere to make the amorphous titanium silicide film amorphous. This is achieved by a method for manufacturing a semiconductor device that includes a step of transforming into a nitride (TiN) film.

[作用コ 即ち、本発明は、TiN膜に変成させるTiSix膜部
分に、TiSixの導電性などの膜質を変化させない材
料のイオンを注入して、その結晶性を破壊させてアモル
ファス化した後、窒素雰囲気中で熱処理してTiN膜を
形成する。そうすると、TiN膜を形成する熱処理温度
は低温度、短時間となって、TiSix膜とデバイスと
に悪影響を与えることかない。
[In other words, in the present invention, ions of a material that does not change the film quality such as conductivity of TiSix are implanted into the TiSix film portion to be transformed into a TiN film to destroy its crystallinity and make it amorphous. A TiN film is formed by heat treatment in an atmosphere. In this case, the heat treatment temperature for forming the TiN film is low and for a short time, so that it does not adversely affect the TiSix film and the device.

[実施例コ 以下、図面を参照して実施例によって詳細に説明する。[Example code] Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図fal〜Fg)は本発明にかかる形成方法の工程
順断面図である。
FIGS. 1 (fal to Fg) are cross-sectional views in the order of steps of the forming method according to the present invention.

第1図(a)参照;従来例と同様に、p型シリコン基板
11上にフィールド絶縁膜12を形成した後、砒素イオ
ンを注入し、熱処理炉で950〜1000℃で熱処理し
てn型拡散層13(膜厚2500〜3500人)を形成
する。
See FIG. 1(a); similar to the conventional example, after forming a field insulating film 12 on a p-type silicon substrate 11, arsenic ions are implanted and heat-treated at 950 to 1000°C in a heat treatment furnace for n-type diffusion. Layer 13 (thickness: 2,500 to 3,500 layers) is formed.

第1図(bl参照;次いで、スパッタ法によりTi膜膜
種4膜厚600人前後)を被着する。
FIG. 1 (see BL; Next, a Ti film of 4 types and a thickness of about 600 layers) is deposited by sputtering.

第1図(C)参照;次いで、窒素中で500〜600℃
においてランプアニール等によって高速アニールして、
Ti膜膜種4基板11とを反応させてTiSix膜(膜
厚1000〜1200人)15を形成する。その際、フ
ィールド絶縁膜上など、シリコン基板と接していない部
分のTi膜膜種4TiN膜14′に形成される。
See Figure 1 (C); then at 500-600°C in nitrogen.
high-speed annealing by lamp annealing etc.
The Ti film type 4 is reacted with the substrate 11 to form a TiSix film 15 (thickness: 1000 to 1200). At this time, the Ti film type 4TiN film 14' is formed on a portion of the Ti film 14' that is not in contact with the silicon substrate, such as on the field insulating film.

第1図(d)参照;次いで、そのTiN膜141を過酸
化水素とアンモニアとの混合液、または過酸化水素と硫
酸との混合液によってエツチング除去した後、化学気相
成長(CV D)法によって絶縁膜16(膜厚0.3〜
0.4μm)を被着し、フォトプロセスを用いて1μm
角程度の電極窓(スルーホール)17を窓開けする。以
上の工程は従来法と同様である。
See FIG. 1(d); Next, the TiN film 141 is removed by etching with a mixture of hydrogen peroxide and ammonia or a mixture of hydrogen peroxide and sulfuric acid, and then chemical vapor deposition (CVD) is performed. The insulating film 16 (thickness 0.3~
0.4 μm) and 1 μm using photo process.
An electrode window (through hole) 17 about the size of a corner is opened. The above steps are similar to the conventional method.

第1図(e)参照;次いで、上面からシリコンイオン(
Si” )を注入して、電極窓17内のTiSix膜の
結晶を壊してアモルファスチタンシリサイド(α−Ti
Six )膜21にする。イオン注入条件は加速電圧7
0KeV、ドーズ量5×10%程度である。なお、注入
イオンはSiの他に窒素(N)や砒素(As) 、燐(
P)等の不純物、あるいは、NとAsとの混合物を用い
ても良い。
See Figure 1(e); Next, silicon ions (
Amorphous titanium silicide (α-Ti) is implanted to break the crystal of the TiSix film within the electrode window 17.
Six) film 21. Ion implantation conditions are acceleration voltage 7
0 KeV and a dose of about 5×10%. In addition to Si, the implanted ions include nitrogen (N), arsenic (As), and phosphorus (
Impurities such as P) or a mixture of N and As may also be used.

第1図(fl参照;次いで、窒素雰囲気中で900°C
210分程度の熱処理をすると、電極窓内のα−TiS
i×膜21はTiN膜21′に変成される。この時、そ
の熱処理温度は比較的低温度で、しかも、短時間である
からTiSix膜15は膜数5度1時間に耐えられ、膜
質が変化してTiSix膜15と膜数513とが反応し
たり、pn接合が破壊されることはない。
Figure 1 (see fl; then heated to 900°C in a nitrogen atmosphere)
After heat treatment for about 210 minutes, α-TiS inside the electrode window
The i× film 21 is transformed into a TiN film 21'. At this time, the heat treatment temperature is relatively low and the heat treatment is for a short time, so the TiSix film 15 can withstand the heat treatment for 5 degrees for 1 hour, and the film quality changes and the TiSix film 15 and the film 513 react. Also, the pn junction will not be destroyed.

第1図(gl参照;次いで、その上にスパッタ法によっ
てへ1膜19(膜厚3000Å以上)を被着し、次にフ
ォトプロセスを用い、リアクティブイオンエツチング(
RIE)によってAI膜19をパターンニングしてAI
配線19を形成する。そうすれば、レジスト膜20マス
ク (図示していない)を有機溶剤で剥離除去しても、
TiN膜は電極窓内にしか介在しないために、旧膜19
が腐食されてA1配線の形状が崩れる問題点は解消され
る。
FIG. 1 (see gl; next, a film 19 (thickness of 3000 Å or more) is deposited thereon by sputtering, followed by photoprocessing and reactive ion etching (
Patterning the AI film 19 by RIE)
Wiring 19 is formed. That way, even if the resist film 20 mask (not shown) is peeled off and removed using an organic solvent,
Since the TiN film is only present within the electrode window, the old film 19
The problem that the shape of the A1 wiring collapses due to corrosion is solved.

上記のような本発明にかかる形成方法によれば、TiS
ix膜を重ねたメタル拡散層とへ1配線との接続が都合
良くおこなわれ、デバイス特性を劣化させることなく、
接触抵抗を減少させて配線抵抗を低下させることができ
る。
According to the formation method according to the present invention as described above, TiS
The metal diffusion layer layered with the Ix film can be conveniently connected to the 1 wiring without deteriorating the device characteristics.
Wiring resistance can be lowered by reducing contact resistance.

尚、上記例はn型拡散層にTiSix膜を重ねる実施例
で説明したが、n型拡散層にTiSix膜を重ねる場合
も同様であり、その場合は注入イオンがAS。
The above example has been explained using an example in which a TiSix film is stacked on an n-type diffusion layer, but the same applies when a TiSix film is stacked on an n-type diffusion layer, and in that case, the implanted ions are AS.

Pの代わりに硼素(B)や弗化硼素などを用いておこな
う。
This is done using boron (B), boron fluoride, etc. instead of P.

[発明の効果] 以上の実施例の説明から明らかなように、本発明によれ
ば拡散層を低抵抗化したメタル拡散層とアルミニウムと
の接続が問題なくおこなわれ、配線抵抗を低下させるこ
とができ、ICの性能向上に顕著に寄与するものである
[Effects of the Invention] As is clear from the description of the embodiments above, according to the present invention, the metal diffusion layer with a low resistance diffusion layer and aluminum can be connected without any problem, and the wiring resistance can be reduced. This significantly contributes to improving the performance of the IC.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(al〜(glは本発明にかかる形成方法の工程
順断面図、 第2図はメタル拡散層を示す図、 第3図fal〜(glは従来の形成方法の工程順断面図
である。 図において、 11はp型シリコン基板、12はフィールド絶縁膜、1
3はn型拡散層、   14はチタン(Ti)膜、15
はチタンシリサイド(TiSix )膜、16は絶縁膜
、     17は電極窓、19はアルミニウム(AI
)膜、 21はアモルファスチタンシリサイド(α−TiSix
)膜、 211はチタンナイトライド(TiN)膜+LI   
          L+I            
  v従来め汗幻戊方及のコ 第31 〔蛭頒鉾曲図(ザリ2) 図
Figure 1(al~(gl is a step-by-step sectional view of the forming method according to the present invention, Figure 2 is a view showing a metal diffusion layer, Figure 3 is a step-by-step sectional view of the conventional forming method. In the figure, 11 is a p-type silicon substrate, 12 is a field insulating film, and 1 is a p-type silicon substrate.
3 is an n-type diffusion layer, 14 is a titanium (Ti) film, 15
1 is a titanium silicide (TiSix) film, 16 is an insulating film, 17 is an electrode window, and 19 is an aluminum (AI) film.
) film, 21 is amorphous titanium silicide (α-TiSix
) film, 211 is titanium nitride (TiN) film + LI
L+I
v Conventional sweat illusion 31 [Hiruhoboko zu (Zari 2) fig.

Claims (1)

【特許請求の範囲】  チタンシリサイド(TiSi_x)膜を重ねた拡散層
の上に絶縁膜を被覆し、該絶縁膜を窓開けして前記チタ
ンシリサイド膜を電極窓内に露出させる工程、 次いで、前記電極窓内に露出したチタンシリサイド膜に
イオン注入してアモルファス化し、アモルファスチタン
シリサイド膜を形成する工程、次いで、窒素雰囲気中で
熱処理して前記アモルファスチタンシリサイド膜をチタ
ンナイトライド(TiN)膜に変成する工程が含まれて
なることを特徴とする半導体装置の製造方法。
[Scope of Claims] A step of coating an insulating film on a diffusion layer overlaid with a titanium silicide (TiSi_x) film, and opening a window in the insulating film to expose the titanium silicide film in the electrode window. Step of implanting ions into the titanium silicide film exposed in the electrode window to make it amorphous to form an amorphous titanium silicide film, and then heat-treating in a nitrogen atmosphere to transform the amorphous titanium silicide film into a titanium nitride (TiN) film. 1. A method for manufacturing a semiconductor device, comprising the steps of:
JP31926487A 1987-12-16 1987-12-16 Manufacture of semiconductor device Pending JPH01160009A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31926487A JPH01160009A (en) 1987-12-16 1987-12-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31926487A JPH01160009A (en) 1987-12-16 1987-12-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01160009A true JPH01160009A (en) 1989-06-22

Family

ID=18108258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31926487A Pending JPH01160009A (en) 1987-12-16 1987-12-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01160009A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03280424A (en) * 1990-03-28 1991-12-11 Sony Corp Wiring formation process
JPH04226025A (en) * 1990-04-16 1992-08-14 Applied Materials Inc Method forming titanium silicide con- ducting layer on silicon wafer
JPH05244576A (en) * 1992-02-26 1993-09-21 Hitachi Ltd Transmission signal reproduction device
US6455875B2 (en) 1992-10-09 2002-09-24 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor having enhanced field mobility
US6624477B1 (en) 1992-10-09 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03280424A (en) * 1990-03-28 1991-12-11 Sony Corp Wiring formation process
JPH04226025A (en) * 1990-04-16 1992-08-14 Applied Materials Inc Method forming titanium silicide con- ducting layer on silicon wafer
JPH05244576A (en) * 1992-02-26 1993-09-21 Hitachi Ltd Transmission signal reproduction device
US6455875B2 (en) 1992-10-09 2002-09-24 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor having enhanced field mobility
US6624477B1 (en) 1992-10-09 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US6790749B2 (en) 1992-10-09 2004-09-14 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US7109108B2 (en) 1992-10-09 2006-09-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device having metal silicide
US7602020B2 (en) 1992-10-09 2009-10-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US7723788B2 (en) 1992-10-09 2010-05-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US8017506B2 (en) 1992-10-09 2011-09-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same

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