JPH04340255A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH04340255A JPH04340255A JP14145491A JP14145491A JPH04340255A JP H04340255 A JPH04340255 A JP H04340255A JP 14145491 A JP14145491 A JP 14145491A JP 14145491 A JP14145491 A JP 14145491A JP H04340255 A JPH04340255 A JP H04340255A
- Authority
- JP
- Japan
- Prior art keywords
- film
- point metal
- melting point
- high melting
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- 238000000059 patterning Methods 0.000 claims abstract description 13
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 6
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims abstract description 4
- 238000002844 melting Methods 0.000 claims description 42
- 230000008018 melting Effects 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005121 nitriding Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000012546 transfer Methods 0.000 abstract description 5
- 230000003287 optical effect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- AHKZTVQIVOEVFO-UHFFFAOYSA-N oxide(2-) Chemical compound [O-2] AHKZTVQIVOEVFO-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は半導体装置およびその
製造方法に関し、特に改良された配線構造とその容易な
製法を提供できるようにしたものに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a device capable of providing an improved wiring structure and an easy manufacturing method thereof.
【０００２】0002
【従来の技術】図２は従来の半導体装置のうち、特に２
層金属配線膜を形成した半導体装置の要部の断面構造図
である。[Prior Art] FIG. 2 shows two of the conventional semiconductor devices.
1 is a cross-sectional structural diagram of a main part of a semiconductor device in which a layered metal wiring film is formed; FIG.
【０００３】図において、１はシリコン単結晶などから
なる半導体基板（以下、単に基板と呼ぶ）、２は基板１
上に形成された第１の絶縁膜、３は第１の絶縁膜２上に
形成された第１の配線膜であり、４は第１の配線膜３を
被覆するように形成された第２の絶縁膜、５は第２の絶
縁膜４上に形成された第２の配線膜であり、５ａは低抵
抗金属膜からなる主たる導電膜（以下、導電膜と呼ぶ）
、５ｂは導電膜５ａ上に形成された高融点金属膜である
。In the figure, 1 is a semiconductor substrate (hereinafter simply referred to as a substrate) made of silicon single crystal or the like, and 2 is a substrate 1.
A first insulating film formed thereon, 3 a first wiring film formed on the first insulating film 2, and 4 a second wiring film formed to cover the first wiring film 3. 5 is a second wiring film formed on the second insulating film 4, and 5a is a main conductive film made of a low resistance metal film (hereinafter referred to as a conductive film).
, 5b is a high melting point metal film formed on the conductive film 5a.
【０００４】次に、前記構成による従来の配線膜構造の
主要な製造工程について述べる。まず、予め所期の素子
部を形成した基板１に対してシリコン酸化膜を形成し、
第１の絶縁膜２とする。次いで、シリサイド、例えばタ
ングステンシリサイド（ＷＳｉ）からなる金属膜をスパ
ッタ法で０．４μｍ程度の膜厚に形成し、レジストパタ
ーンをマスクに異方性エッチングし、レジストを除去し
第１の配線膜３とする。Next, the main manufacturing steps of the conventional wiring film structure having the above structure will be described. First, a silicon oxide film is formed on a substrate 1 on which a desired element portion has been formed in advance,
This is referred to as the first insulating film 2. Next, a metal film made of silicide, for example tungsten silicide (WSi), is formed to a thickness of about 0.4 μm by sputtering, anisotropically etched using the resist pattern as a mask, and the resist is removed to form the first wiring film 3. shall be.
【０００５】続いて、第１の配線膜３を覆うように８０
０℃程度の高温ＣＶＤ法でシリコン酸化膜を０．１μｍ
の膜厚に形成し、さらにボロン，リンを含むシリコン酸
化膜（以下、ＢＰＳＧ膜と呼ぶ）を常圧ＣＶＤ法で０．
８μｍ程度の膜厚に形成後、９００℃程度の温度で熱処
理，リフローし、その後、再び高温ＣＶＤ法でシリコン
酸化膜を０．１μｍ程度の膜厚に形成し、第２の絶縁膜
４とする。[0005] Next, a film 80 is coated to cover the first wiring film 3.
Silicon oxide film is deposited to a thickness of 0.1 μm using high-temperature CVD method at approximately 0°C.
A silicon oxide film (hereinafter referred to as BPSG film) containing boron and phosphorus is formed to a thickness of 0.0000000000000000000000000000000000000000,0012
After forming the film to a thickness of approximately 8 μm, heat treatment and reflow are performed at a temperature of approximately 900° C., and then a silicon oxide film is again formed to a thickness of approximately 0.1 μm by high-temperature CVD to form the second insulating film 4. .
【０００６】さらに、第２の絶縁膜４上にＡｌもしくは
Ａｌ合金、例えばアルミ・銅（ＡｌＣｕ）などからなる
金属膜をスパッタ法で０．４μｍ程度の膜厚に形成し、
導電膜５ａとした後、引き続き、高融点金属、例えばタ
ングステン（Ｗ）をスパッタ法で０．１μｍ程度の膜厚
に形成し、５ｂとする。その後、レジストパターンをマ
スクに異方性エッチングし、レジストを除去して、第２
の配線膜５とする。Furthermore, a metal film made of Al or an Al alloy, such as aluminum/copper (AlCu), is formed on the second insulating film 4 to a thickness of about 0.4 μm by sputtering.
After forming the conductive film 5a, a high melting point metal such as tungsten (W) is subsequently formed to a thickness of about 0.1 μm by sputtering to form the conductive film 5b. After that, anisotropic etching is performed using the resist pattern as a mask, the resist is removed, and the second
The wiring film 5 is as follows.
【０００７】このとき、高融点金属膜５ｂはレジストパ
ターニング時の転写光、例えば波長４３６ｎｍ（ｉ線）
に対する反射率が約６０％と高いため、高融点金属膜５
ａでの反射光でハレーションが生じ、レジストパターン
が所定の線幅より細くなる。このあと、所定の処理を施
すことによって図２に示した構造の半導体装置を得る。At this time, the high melting point metal film 5b is exposed to transfer light during resist patterning, for example, wavelength 436 nm (i-line).
The high melting point metal film 5 has a high reflectance of about 60%.
Halation occurs due to the reflected light at point a, and the resist pattern becomes thinner than a predetermined line width. Thereafter, a semiconductor device having the structure shown in FIG. 2 is obtained by performing predetermined processing.
【０００８】[0008]
【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、第２の絶縁膜では下地
の第１の配線膜３のため必然的に段差部を生じる。この
段差部で第２の配線膜を写真製版する際、転写光が第２
の配線膜で反射する方向は段差の形状によって一定では
なく、特に反射率が高い場合、反射光でレジストが感光
するため、下地段差によってレジストパターンが変形し
（以下、ハレーションと呼ぶ）、第２の配線膜の仕上が
り加工精度が悪くなるという問題があった。Since the conventional semiconductor device is constructed as described above, a stepped portion is inevitably formed in the second insulating film due to the underlying first wiring film 3. When photoengraving the second wiring film at this stepped portion, the transfer light is applied to the second wiring film.
The direction of reflection on the wiring film is not constant depending on the shape of the step, and when the reflectance is particularly high, the resist is exposed to the reflected light, so the resist pattern is deformed by the underlying step (hereinafter referred to as halation), and the second There was a problem in that the finishing accuracy of the wiring film deteriorated.
【０００９】この問題を解決するために高融点金属の材
料を反射率の低い材料、例えば窒化チタン（ＴｉＮ）等
に変更することが考えられるが、積層配線構造の本来の
目的であるストレスマイグレーション耐性及びエレクト
ロマイグレーション耐性の向上の観点から選択されるべ
き材料の選択技を限定する制約要因となり、材料の持つ
本来の特性を十分に生かせていなかった。In order to solve this problem, it may be possible to change the high-melting point metal material to a material with low reflectivity, such as titanium nitride (TiN), but this would reduce stress migration resistance, which is the original purpose of the layered wiring structure. This has become a constraining factor that limits the selection technique of materials that should be selected from the viewpoint of improving electromigration resistance, and the original characteristics of the materials cannot be fully utilized.
【００１０】この発明は上記のような問題点を解消する
ためになされたもので、第２の配線膜での反射、つまり
高融点金属膜での反射を抑え、加工精度の高い半導体装
置およびその製造方法を提供することを目的とする。The present invention has been made to solve the above-mentioned problems, and suppresses reflection on the second wiring film, that is, reflection on the high-melting point metal film, and provides a semiconductor device with high processing precision and its semiconductor device. The purpose is to provide a manufacturing method.
【００１１】[0011]
【課題を解決するための手段】この発明に係る半導体装
置は、高融点金属膜と低抵抗金属膜からなる配線構造に
おいて、高融点金属膜の表面が反射防止膜となる高融点
金属酸化物で被覆されるようにしたものである。[Means for Solving the Problems] A semiconductor device according to the present invention has a wiring structure consisting of a high melting point metal film and a low resistance metal film, in which the surface of the high melting point metal film is made of a high melting point metal oxide that serves as an antireflection film. It is designed to be covered.
【００１２】また、この発明に係る半導体装置の製造方
法は、高融点金属膜と低抵抗金属からなる配線構造を形
成する方法において、低抵抗金属膜を形成する工程と高
融点金属膜を形成する工程と高融点金属膜を酸化する工
程とを含むものである。[0012] The method for manufacturing a semiconductor device according to the present invention also includes a step of forming a low-resistance metal film and a step of forming a high-melting-point metal film in a method of forming a wiring structure made of a high-melting point metal film and a low-resistance metal. and a step of oxidizing the high melting point metal film.
【００１３】[0013]
【作用】この発明における半導体装置は、高融点金属膜
の表面を高融点酸化膜で被覆したことにより、光学的特
性から反射率が低くなるので、下地からの反射によるハ
レーションが防止でき、精度の高い配線加工が可能とな
る。[Function] In the semiconductor device of the present invention, the surface of the high-melting point metal film is coated with a high-melting point oxide film, which lowers the reflectance due to its optical properties, so it is possible to prevent halation due to reflection from the base, and improve precision. High-quality wiring processing becomes possible.
【００１４】また、この発明における半導体装置の製造
方法においては、高融点金属膜を形成する工程の後、高
融点金属膜自身を酸化するようにしたので、製造工程を
１つ追加するだけで容易にその反射率を低減でき、かつ
転写する光の波長に合わせ、最適な反射率を選択できる
ため、下地からの反射によるハレーションが防止され、
パターニング精度が向上する。In addition, in the method for manufacturing a semiconductor device according to the present invention, the high melting point metal film itself is oxidized after the step of forming the high melting point metal film, so that the manufacturing process can be easily performed by adding one manufacturing step. The reflectance can be reduced, and the optimal reflectance can be selected according to the wavelength of the light to be transferred, preventing halation caused by reflection from the substrate.
Patterning accuracy is improved.
【００１５】[0015]
【実施例】以下、この発明の一実施例を図について説明
する。なお、従来の技術の説明と重複する部分は、適宜
その説明を省略する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Note that the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.
【００１６】図１はこの発明の一実施例の半導体装置の
主要構造を示す断面図である。図において、１〜５，５
ａ，５ｂは従来のものと同じものである。５ｃは高融点
金属膜５ｂ上に形成された高融点金属酸化膜等からなる
低反射膜である。FIG. 1 is a sectional view showing the main structure of a semiconductor device according to an embodiment of the present invention. In the figure, 1 to 5,5
a and 5b are the same as the conventional one. 5c is a low reflection film made of a high melting point metal oxide film or the like formed on the high melting point metal film 5b.
【００１７】以下、このような構造の半導体装置の製造
方法を説明する。まず、基板１上にシリコン酸化膜を形
成し、第１の絶縁膜２とする。次いで、シリサイド膜を
０．４μｍ程度の膜厚に形成してパターニングし、第１
の配線膜３とする。さらに、高温ＣＶＤ法によるシリコ
ン酸化膜，ＢＰＳＧ膜を所定の膜厚に形成し、第２の絶
縁膜とする。A method of manufacturing a semiconductor device having such a structure will be explained below. First, a silicon oxide film is formed on a substrate 1 to serve as a first insulating film 2. Next, a silicide film is formed to a thickness of about 0.4 μm and patterned.
The wiring film 3 is as follows. Furthermore, a silicon oxide film and a BPSG film are formed to a predetermined thickness by high-temperature CVD to serve as a second insulating film.
【００１８】続いて、第２の絶縁膜４上にＡｌ合金から
なる金属膜を所定の膜厚に形成し、導電膜５ａとした後
、引き続き、高融点金属膜、例えばＷを形成し、高融点
金属膜５ｂとする。この後、酸素プラズマにさらすこと
で、高融点金属膜５ｂの表面の０．０１μｍ程度を酸化
し、高融点酸化膜、つまり酸化タングステン膜（ＷＯ膜
）を形成して低反射膜５ｃとする。このＷＯ膜はｉ線の
光に対する反射率は２５％程度で、Ｗ単体の反射率６０
％に比べると半分以下となり、低反射膜として広く用い
られているアモルファスシリコン膜の３０％，ＴｉＮ膜
の２０％と比較して十分に低い反射率となる。その後、
レジストパターンをマスクとして異方性エッチングし、
レジスト除去後、第２の配線膜５とする。以上の工程を
経て、図１に示す半導体装置が完成する。Next, a metal film made of an Al alloy is formed to a predetermined thickness on the second insulating film 4 to form a conductive film 5a, and then a high melting point metal film, for example W, is formed to form a high melting point metal film. A melting point metal film 5b is used. Thereafter, by exposing to oxygen plasma, about 0.01 μm of the surface of the high melting point metal film 5b is oxidized to form a high melting point oxide film, that is, a tungsten oxide film (WO film), thereby forming the low reflection film 5c. This WO film has a reflectance of about 25% for i-line light, and the reflectance of W alone is 60%.
%, and the reflectance is sufficiently low compared to 30% for amorphous silicon films and 20% for TiN films, which are widely used as low-reflection films. after that,
Anisotropic etching is performed using the resist pattern as a mask.
After removing the resist, a second wiring film 5 is formed. Through the above steps, the semiconductor device shown in FIG. 1 is completed.
【００１９】このような本実施例では、導電膜５ａおよ
び高融点金属膜５ｂからなる第２の配線膜上に低反射膜
５ｃを形成したので、第２の配線膜のパターニング時に
下地反射の影響が小さくなり、下地段差によらない高い
精度のパターニングが実施できる。In this embodiment, since the low reflection film 5c is formed on the second wiring film made of the conductive film 5a and the high-melting point metal film 5b, the influence of the reflection of the base layer is eliminated when patterning the second wiring film. becomes smaller, and highly accurate patterning can be performed without depending on the level difference between the substrates.
【００２０】また、上記実施例の製造方法によれば、高
融点金属膜を形成した後、それ自身を酸化するようにし
たので、反射率を低減するために新たに増す工程数を最
小限にすることができ、しかも、この低反射膜の存在に
よってパターニング精度が大きく向上する。Furthermore, according to the manufacturing method of the above embodiment, after forming the high-melting point metal film, the film itself is oxidized, so that the number of newly added steps for reducing the reflectance can be minimized. Furthermore, the presence of this low-reflection film greatly improves patterning accuracy.
【００２１】なお、上記実施例では、高融点金属膜とし
てタングステンをあげたが、チタン（Ｔｉ），モリブデ
ン（Ｍｏ）であってもよく、適宜選択されればよい。In the above embodiments, tungsten is used as the high-melting point metal film, but titanium (Ti) or molybdenum (Mo) may be used as appropriate.
【００２２】また、低反射膜を形成する方法として、酸
素プラズマで酸化する例をあげたが、炉中での酸化，酸
化イオン注入，待機中でのホットプレートベークなどの
方法であってもよく、その方法はこれに限定されず、そ
の膜厚も転写光の波長に合わせて適宜決定されればよい
。[0022]Although oxidation with oxygen plasma has been given as an example of a method for forming a low-reflection film, other methods such as oxidation in a furnace, oxide ion implantation, and hot plate baking during standby may also be used. However, the method is not limited to this, and the film thickness may be appropriately determined according to the wavelength of the transfer light.
【００２３】さらに、上記実施例では、低反射膜５ｃと
して高融点金属酸化膜のものを示したが、高融点金属を
窒化した高融点金属窒化膜、例えば窒化タングステン（
ＷＮ），窒化チタン（ＴｉＮ）でもよく、窒化モリブデ
ン（ＭｏＮ）でも同様の効果を期待できる。Further, in the above embodiment, a high melting point metal oxide film was used as the low reflection film 5c, but a high melting point metal nitride film obtained by nitriding a high melting point metal, such as tungsten nitride (
WN), titanium nitride (TiN), and molybdenum nitride (MoN) can also be expected to produce similar effects.
【００２４】また、高融点金属酸化膜の形成方法，窒化
等の処理方法により、その膜厚で転写する光の波長に対
する反射率が異なるため、表面処理を変えるだけで転写
光に対し最適な反射率を選択することもできる。Furthermore, depending on the method of forming the high melting point metal oxide film and the treatment method such as nitriding, the reflectance for the wavelength of the transferred light varies depending on the thickness of the film, so simply changing the surface treatment can achieve the optimum reflection for the transferred light. You can also choose the rate.
【００２５】さらに、低反射膜５ｃは水素雰囲気下で高
融点金属を熱処理しても得られ、低反射膜５ｃの材料，
形成方法は、加工しやすさ，転写光の波長に合わせ適宜
選択されればよい。Furthermore, the low reflection film 5c can be obtained by heat treating a high melting point metal in a hydrogen atmosphere, and the material of the low reflection film 5c,
The forming method may be appropriately selected depending on the ease of processing and the wavelength of the transfer light.
【００２６】さらに、また上記実施例では、配線膜のパ
ターニングについて説明したが、さらに絶縁膜を介し、
上層の配線膜と接続するためのコンタクトホールのパタ
ーニングの際も下層の配線膜からの反射が影響するため
上記実施例と同様の効果を奏する。Furthermore, in the above embodiment, the patterning of the wiring film was explained, but furthermore, the patterning of the wiring film through the insulation film,
When patterning a contact hole for connection to an upper wiring film, the same effects as in the above embodiments can be achieved because the reflection from the lower wiring film affects the patterning.
【００２７】[0027]
【発明の効果】以上のように、この発明に係る半導体装
置によれば、高融点金属膜と低抵抗金属膜からなる積層
配線の高融点金属膜の上を、反射率の低い高融点金属酸
化膜または高融点金属窒化膜で被覆する構造としたので
、配線膜からの反射が抑制され、下地段差の形状によら
ないパターニングが可能となる効果がある。As described above, according to the semiconductor device of the present invention, a high melting point metal film having a low reflectance is coated on a high melting point metal film of a laminated wiring consisting of a high melting point metal film and a low resistance metal film. Since the structure is coated with a film or a high melting point metal nitride film, reflection from the wiring film is suppressed and patterning can be performed without depending on the shape of the underlying step.
【００２８】また、この発明に係る半導体装置の製造方
法によれば、高融点金属膜と低抵抗金属膜からなる積層
配線構造を形成する製造方法において、高融点金属膜を
形成後、それ自身を酸化もしくは窒化して低反射膜を形
成するようにしたので、反射率を低減するために新たに
増す工程数を最小限にすることができ、しかも、この低
反射膜の存在によってパターニング精度が向上するとい
う大きな効果がある。Further, according to the method for manufacturing a semiconductor device according to the present invention, in the method for forming a laminated wiring structure consisting of a high melting point metal film and a low resistance metal film, after forming the high melting point metal film, the semiconductor device itself is Since a low-reflection film is formed by oxidation or nitridation, the number of additional steps required to reduce reflectance can be minimized, and the presence of this low-reflection film improves patterning accuracy. This has a big effect.
【図１】この発明の一実施例による２層金属配線膜を形
成した半導体装置の主要部を示す断面図である。FIG. 1 is a sectional view showing the main part of a semiconductor device in which a two-layer metal wiring film is formed according to an embodiment of the present invention.
【図２】従来の半導体装置の製造方法を示す断面図であ
る。FIG. 2 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
５ 第２の配線膜 ５ａ 導電膜 ５ｂ 高融点金属膜 ５ｃ 低反射膜 5 Second wiring film 5a Conductive film 5b High melting point metal film 5c Low reflection film
Claims (2)
膜と低抵抗導電膜とからなる積層配線構造を有する半導
体装置において、前記積層配線膜上に、高融点金属酸化
膜、もしくは高融点金属窒化膜が形成され、当該膜はパ
ターニング時の反射光を低減するものであることを特徴
とする半導体装置。1. A semiconductor device having a laminated wiring structure consisting of a high melting point metal film and a low resistance conductive film formed on a semiconductor substrate, wherein a high melting point metal oxide film or a high melting point metal film is formed on the laminated wiring film. A semiconductor device characterized in that a nitride film is formed, and the film reduces reflected light during patterning.
膜と低抵抗導電膜とからなる積層配線構造を有する半導
体装置を製造する方法において、低抵抗導電膜を形成す
る工程と、高融点金属膜を形成する工程と、前記高融点
金属膜を酸化する工程、もしくは窒化する工程を含むこ
とを特徴とする半導体装置の製造方法。2. A method for manufacturing a semiconductor device having a stacked wiring structure consisting of a high melting point metal film and a low resistance conductive film formed on a semiconductor substrate, including the steps of: forming a low resistance conductive film; A method for manufacturing a semiconductor device, comprising the steps of forming a film and oxidizing or nitriding the high melting point metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14145491A JPH04340255A (en) | 1991-05-16 | 1991-05-16 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14145491A JPH04340255A (en) | 1991-05-16 | 1991-05-16 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04340255A true JPH04340255A (en) | 1992-11-26 |
Family
ID=15292285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14145491A Pending JPH04340255A (en) | 1991-05-16 | 1991-05-16 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04340255A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100274149B1 (en) * | 1997-12-22 | 2000-12-15 | 정선종 | Metal thin film patterning method |
| KR100382999B1 (en) * | 1995-12-31 | 2003-07-07 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device |
-
1991
- 1991-05-16 JP JP14145491A patent/JPH04340255A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100382999B1 (en) * | 1995-12-31 | 2003-07-07 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device |
| KR100274149B1 (en) * | 1997-12-22 | 2000-12-15 | 정선종 | Metal thin film patterning method |
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