JPH10270553A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of an upper-layer wiring contact at a borderless contact. SOLUTION: When the overlapping of a contact hole 6b, whose diameter is approximately equal to the wiring width, is deviated on a lower wiring 5 containing a first-layer metal film 3 comprising an Al-based material, a minute depressed part 9 is formed at a hole bottom causing the trouble in the later formation of a plug. Then, sintering is performed after the opening of the hole, and the depressed part 9 is embedded with a hillock 3h, which is grown from the side wall surface of the first metal film 3. Since a first-layer reflection preventing film 4 suppresses the hillock growing, the hillock does not grow in a contact hole 6a without the overlap deviation. As the result that the entire hole bottom surface is approximately flattened, the coverage of the following second-layer contact film 10 is improved. Thus, the embedding property of a blanket W film in the later process is improved, and the excellent ohmic contact through the plug can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for improving the reliability of upper layer wiring contacts by reliably filling connection holes with a conductive material film in a so-called borderless contact process.

[0002]

2. Description of the Related Art In the field of manufacturing semiconductor devices, in which the miniaturization of patterns and the high integration of elements have advanced to a high degree, the area ratio of wiring portions to the total area of device chips tends to increase. In order to suppress the increase in the size of the device chip as much as possible, the importance of a multilayer wiring technique of vertically stacking a plurality of wiring layers on a substrate with an insulating film interposed therebetween is increasing.

In a general process of the multilayer wiring technique, first, a lower wiring is covered with an insulating film, a photolithography is performed on the insulating film to form a resist pattern, and a connection hole is formed in the insulating film using the pattern as a mask. (contact·
A hole is opened, and the upper wiring is brought into contact with the lower wiring exposed on the bottom surface. What is important in the above process is that the lower layer wiring and the connection hole overlap (alignment).
Is the accuracy of The overlay accuracy is a value determined by the performance of the exposure apparatus.
Under a fine design rule after m, it is more difficult to improve the resolution. For this reason, in the so-called normal aligned contact process in which the connection holes are correctly overlapped with the lower wiring, a margin for the variation in the overlay is set so that even if the opening position of the connection hole is slightly shifted, the connection hole does not come off the lower wiring. It is common practice to widen a part of the line width of the lower wiring in anticipation.

FIG. 7 shows the structure of a typical aligned contact. In this figure, a lower wiring 22 formed on an insulating film 21 is covered with an interlayer insulating film 23, a contact hole 23a is opened in the interlayer insulating film 23, and an upper wiring 24 is formed through the contact hole 23a. FIG. 7A shows a state in which contact is made, (a) is a top view,
(B) is a sectional view taken along line AA. In the lower layer wiring 22 formed on the insulating film 21, the width P of the pad portion 22p, which is a contact formation site, is larger than the line width L of the routing portion (L <P). It is a value obtained by adding a margin of misalignment to the diameter D of the contact hole 23a. If you try to realize such a layout within a minimum area, minimum feature size of the space S ₂ between adjacent pads 22p in the design rule S
_{It has to be min} . Therefore, to equalize the inter-wiring space S ₁ of the adjacent lower wiring 22 and the minimum processing dimension S _min is impossible in principle, this is a factor limiting the reduction of the device chip.

On the other hand, a technique proposed in recent years to solve this limitation is a borderless contact process. FIG. 8 shows the structure of a typical borderless contact. In this drawing, a lower wiring 32 formed on an insulating film 31 is covered with an interlayer insulating film 33, a contact hole 33a is opened in the interlayer insulating film 33, and an upper wiring 34 is formed through the contact hole 33a. FIG. 7A shows a state in which contact is made, (a) is a top view,
(B) is the BB sectional drawing. Lower wiring 32 formed on the insulating film 31 is the line width L is always constant, yet the diameter D of the line width L and the space between wirings S ₃ contact holes 33a are all substantially equal. According to this layout, by the inter-wire spaces S ₃ the minimum processing dimension S _min in the design rules, the considerably reducible the device chip.

In the case of the borderless contact, if the overlapping of the lower wiring 32 and the contact hole 33a is slightly shifted, the exposed area of the upper surface of the lower wiring 32 at the bottom of the contact hole 33a is reduced. However, in the dry etching for opening the contact hole 33a in the interlayer insulating film 33, the etching speed of the interlayer insulating film 33 is higher than the etching speed of the lower wiring 32. Go deeper. As a result, the contact hole 33a
A concave portion due to misalignment, that is, a recess 35 is formed on the bottom surface of the lower wiring 3.
At least a part of the side wall surface of the second is exposed. Therefore,
By embedding a conductive material film in the contact hole 33a including the recess 35, an upper wiring contact can be formed with a sufficient contact area between the conductive material film and the lower wiring 32 secured.

[0007]

However, it is actually very difficult to embed the conductive material film up to the minute recess 35 as described above. In recent years, due to the reduction of the diameter of the contact hole and the flattening of the interlayer insulating film, some contact holes have an aspect ratio of 4 to 5 or more. In the sputter deposition of a conductive material film, when the aspect ratio is 3 or more, the embedding characteristics are significantly deteriorated.
Applying a plug forming technique to fill holes is the mainstream. The plug formation technique is to cover the entire surface of the substrate once with a blanket-shaped conductive material film formed by a method having excellent step coverage (step coverage) such as a CVD method, and then etch back or perform CMP.
In this method, the conductive material film on the interlayer insulating film is removed by a flattening method such as (chemical mechanical polishing) or the like, and a contact is made using the conductive material film (plug) remaining in the contact hole.

[0008] The material for forming the plug is a so-called high material such as tungsten (W), molybdenum (Mo), tantalum (Ta) or the like so that the contact reliability can be maintained even if current is concentrated in the fine contact hole. A melting point metal film is used. However, these refractory metal films are
Since adhesion to an interlayer insulating film made of an Ox-based material film is generally low, it is indispensable to provide an adhesion film made of a Ti-based material as a base film. As a method of forming the adhesion film, a CVD method using an organometallic compound has been proposed, but there are still many problems, and at present, it is necessary to rely on sputtering.

However, it is almost impossible for the sputtered particles to reach the depth of the finer recess 35 formed at the bottom of the fine contact hole. this is,
This is because in sputtering, the angle of incidence of sputtered particles on the substrate is limited to a relatively narrow range, and a shadowing effect due to the peripheral shape acts. As a result, for example, as shown in FIG.
When the coverage of the adhesion film 36 in FIG.
As shown in FIG.
The filling property of the contact hole 33a by the film 37 is also deteriorated, and a cavity 38 is formed in the recess 35. This prevents the formation of a stable ohmic contact.

It is an object of the present invention to solve the above-mentioned problems and to provide a method of manufacturing a semiconductor device capable of achieving a stable ohmic contact even when a borderless contact is employed.

[0011]

According to a method of manufacturing a semiconductor device of the present invention, an Al-based metal film used as a typical wiring material generates a hillock due to a stress difference from a surrounding film in accordance with a heat history. By performing sintering after opening the contact hole, the contact hole
A recess formed by misalignment at the bottom of the hole, that is, a hillock is grown toward the inside of the depression, and the bottom is substantially flattened, and then the contact hole is buried with a conductive material film. This is to solve the above-mentioned problem.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is intended to restore the shape of the bottom surface of a contact hole in a self-aligned manner by effectively utilizing the generation of hillocks in an Al-based metal film, which has been regarded as an undesirable phenomenon. It is. Here, the Al-based metal film is typically a pure Al film, an Al-Si alloy film, an Al-S film.
They are an i-Cu alloy film and an Al-Cu alloy film. The Al-based metal film is usually formed on a silicon substrate or an insulating film, and after being patterned into wiring, is covered with an interlayer insulating film or a passivation film. However, since the semiconductor process continues after going through various heat treatments, a compressive stress is generated in the wiring during the temperature rise process due to a difference in thermal expansion coefficient between the wiring and the surrounding film. When relaxing this compressive stress, A
The protrusion formed on the surface of the l-type metal film by itself is a hillock. Since the Al-based metal film has a low recrystallization temperature and a low activation energy for self-diffusion, hillocks are easily generated even when the substrate is heated to about 200 ° C.

The hillock height may reach the order of 1 μm depending on the thickness of the Al-based metal film. Borderless contacts are used in processes where the design rule is 0.3 μm or later, and the misalignment between the lower wiring and the contact holes is reduced by a factor of 0.3.
Assuming that it occurs on the order of 1 μm, that is, the width of the depression is on the order of 0.1 μm, it is sufficiently possible to cover the volume of the depression with the hillock volume and embed it. is there.

The sintering of the Al-based metal film has been performed after the wiring patterning for the purpose of aligning the crystal grains of Al. However, the sintering after the opening of the contact hole in the present invention is basically performed. It can be performed under the same conditions as in the past. Typical processing temperature range is
The hillock can be generated and the melting point of Al is set to a range lower than the melting point. The processing time depends on the temperature, but about 1 minute to
Set appropriately within a range of one hour. In addition, the sintering atmosphere is the same as the usual forming gas (4
% N ₂ gas containing less than ₂ % H ₂ gas). Alternatively, sintering may be performed in an atmosphere of a rare gas such as Ar or under a high vacuum.

Since the hillock may grow to a large size as described above, if the hillock extends upward from the bottom surface of the contact hole, it may hinder the filling of the contact hole with the conductive material film. Alternatively, there is a possibility that the essential depression may not be sufficiently implanted. Therefore, as a configuration of the lower layer wiring in the present invention, it is particularly preferable that an antireflection film capable of suppressing hillock growth is laminated on the Al-based metal film. The anti-reflection film is generally extremely thin as compared with the Al-based metal film, and remains only on the upper surface of the Al-based metal film by being patterned simultaneously with the Al-based metal film. Therefore, the hillock growth surface of the lower wiring is limited to the side wall surface, and the recessed portion can be more reliably buried. On the other hand, no depression is formed on the bottom surface of the contact hole where no misalignment occurs, and the antireflection film is completely exposed on the bottom surface. Is suppressed. The antireflection film is considered to be essential for improving the resolution characteristics of photolithography in a semiconductor process having a design rule of 0.3 μm or less. Does not cause an increase in man-hours compared to existing processes.

In the present invention, since the bottom surface of the contact hole is substantially flattened as described above, the subsequent filling of the contact hole with a conductive material film becomes easy. The conductive material film may be an Al-based metal film formed by sputtering, of course. However, when the aspect ratio of the contact hole is as large as 3 or more, and this is to be embedded by applying a plug forming technique. In this case, the present invention is particularly effective. This is because, in the case of the plug formation technology, the formation of an adhesion film is indispensable, and if the coverage of the adhesion film is improved by substantially flattening the bottom surface of the contact hole, the embedding with the high melting point metal film is easy. This is because it is performed reliably.

When the adhesion film is formed by sputtering,
Sintering, which is a pre-process, can also be performed in the same sputtering apparatus. For example, taking a Ti film and a TiN film, which are typical adhesion films, as an example, these films are usually formed continuously in the same apparatus while changing the atmosphere gas. That is, first, using Ar gas, Ti
A Ti film is formed by sputtering the target,
Next, the TiN film is formed by changing the ambient gas to N ₂ gas and performing reactive sputtering of a Ti target. In addition, the sputtering apparatus includes a heating means for the substrate in order to promote the surface migration of the film-forming particles.

Therefore, the substrate having the contact holes opened is carried into a sputtering apparatus, the inside of the apparatus is evacuated to a high vacuum, and sintering is performed using the above-mentioned heating means. , N ₂ gas, and the adhesion film can be continuously formed. The sintering in this case can be performed under high vacuum as it is after evacuation of the inside of the apparatus. However, since this sputtering apparatus has a supply system of Ar and N ₂ , the sintering is performed under an Ar atmosphere or N ₂ It can also be performed in an atmosphere. In addition, after the sintering, if necessary, reverse sputtering using Ar gas can be performed to perform pretreatment for cleaning the contact bottom surface. In any case, if the apparatus is shared between the processes, the number of times of loading and unloading the substrate between various processing apparatuses can be reduced, which is extremely effective in preventing contamination and improving throughput.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described.

Example 1 In this example , Al-coated on the surface was coated with a TiN anti-reflection film.
A process example in which a contact hole is opened facing a lower wiring including a 1% Si-0.5% Cu film, sintering is performed in a forming gas atmosphere, and then a W plug and an upper wiring are formed. This will be described with reference to FIGS.

FIG. 1 shows a state in which resist patterning has been performed on an interlayer insulating film in which a contact hole is to be opened. Describing the steps so far, first, the lower wiring 5 was formed on the insulating film 1 made of, for example, SiOx. The insulating film 1 may be any one of an interlayer insulating film, a field oxide film, and an SOI substrate. The lower-layer wiring 5 has a first-layer adhesion film 2 (Ti) in which a Ti film formed by sputtering to a thickness of about 30 nm and a TiN film formed by sputtering to a thickness of about 70 nm are laminated in this order.
/ TiN), A formed by sputtering to a thickness of about 500 nm
A first-layer metal film (Al) made of 1-1% Si-0.5% Cu film, and a TiN film formed by sputtering to a thickness of about 25 nm on the assumption that KrF excimer laser lithography is performed. The first anti-reflection film (TiN) is sequentially laminated, and this laminated film has a thickness of 0.25 μm.
This is obtained by processing into a line and space shape.

Next, the entire surface of the substrate is covered with an interlayer insulating film 6 (SiOx) made of a SiOx-based material film to make it substantially flat, and then, for example, a positive-type chemically amplified photoresist is formed on the interlayer insulating film 6. A resist pattern 7 was formed by performing photolithography using a KrF excimer laser stepper. The resist pattern 7 serves as a mask for contact hole etching, and has a diameter of 0.25 μm following the hole pattern.
m openings 8a and 8b. However, while the opening 8a was formed at the correct overlapping position with respect to the lower wiring 5, the opening 8b caused a misalignment of about 0.08 μm in the line width direction with respect to the lower wiring 5.

Next, dry etching of the interlayer insulating film 6 is performed, and as shown in FIG.
6b was opened. The dry etching conditions at this time are as follows:
For example: Apparatus Magnetron RIE apparatus N ₂ flow rate 20 SCCM CF ₄ flow rate 30 SCCM CHF ₃ flow rate 20 SCCM pressure 80 Pa RF power 800 W (13.56 MHz) At this time, the bottom surface of the contact hole 6 a opened without causing misalignment. Is flat, and the first-layer antireflection film 4 is exposed on the entire surface, but the bottom surface of the contact hole 6b formed due to misalignment has a width of 0.0 mm.
A depression 9 having a thickness of 8 μm and a depth of about 0.08 μm was formed.

Next, the above-mentioned substrate is carried into a heat treatment furnace, and, for example, at 400 ° C. and 30 ° C. in a forming gas atmosphere.
Minutes of sintering. As a result, as shown in FIG. 3, the hillocks of Al 3 h extend from the side wall surface of the lower wiring 5 facing the recess 9, more precisely, from the side wall surface of the first metal film 3.
Grew and buried the recess 9 almost flat. At this time, since the upper surface of the lower wiring 5 was covered with the first-layer antireflection film 4, hillock growth in the vertical direction was not observed. As a result, the bottom surface of the contact hole 6b in which misalignment has occurred has become substantially flat as a whole. On the other hand, contact holes 6 with no misalignment
Since there was no exposed surface of the first-layer metal film 3 on the bottom surface of a, no hillock growth inside the hole was observed. As described above, it is an excellent advantage of the present invention that the bottom surface can be flattened in a self-aligned manner only in a contact hole having a misalignment.

Next, as shown in FIG. 4, the entire surface of the substrate was covered with a second adhesion film 10 (Ti / TiN). In forming the second adhesive film 10, continuous sputtering of a Ti film and a TiN film may be performed according to a conventional method. Although the present invention employs a borderless contact process, all contact
Since the bottom surface of the hole is flattened, the second-layer adhesion film 1
The coverage with 0 was good.

Next, the entire surface of the substrate was covered with a blanket W film 11 as shown in FIG. 5 by a normal CVD method. The coverage of the blanket W film 11 was extremely good, and no cavity was left at the corner of the contact hole as in the prior art. Next, this blanket W
Etchback or CMP is performed to remove a portion of the film 11 and the second-layer adhesion film 10 extending on the interlayer insulating film 6, and the remaining film of the second-layer adhesion film is formed inside the contact holes 6 a and 6 b. 10p and the remaining film 11p of the blanket W film were left. These two residual films 10p and 11p become plugs 12. On the surface of the substrate thus flattened, the third-layer adhesion film 13 (Ti / Ti
N) A second-layer metal film 14 (Al) and a second-layer antireflection film (TiN) 15 were formed by sputtering, and an upper wiring 16 composed of these three layers was formed through patterning. By the process of the present invention as described above, the ohmic contact between the upper wiring 16 and the lower wiring 5 via the plug 12 was successfully achieved.

Example 2 In this example, sintering and sputter deposition of the second adhesive film 10 were performed continuously while the substrate was placed in the same sputtering apparatus. That is, as shown in FIG. 2 described above, the substrate in a state where the opening of the contact hole was completed was carried into the sputtering apparatus, and sintering was performed at 500 ° C. for 3 minutes under a high vacuum of about 0.3 Pa. .
Here, the reason why the sintering temperature was increased as compared with the first embodiment is to give priority to the consistency with the film forming temperatures of the subsequent Ti film and TiN film and to take into consideration that the temperature control of the base can be performed quickly. . As a result of shortening the processing time instead of increasing the temperature, hillocks 3h were generated as in Example 1, and the bottom surface of the contact hole could be substantially flattened. Thereafter, an Ar gas was introduced into the apparatus to form a Ti film by sputtering, and a N ₂ gas was further introduced to form a TiN film. According to the method as described above, sintering is
Since a series of processes up to the formation of the layer adhesion film can be performed without transporting the substrate to the atmosphere, contamination can be reduced and throughput can be improved.

Although the present invention has been described based on two embodiments, the present invention is not limited to these embodiments. For example, details such as the structure of the base used as the processing sample, the thickness and dimensions of the constituents of the base, and process conditions such as dry etching and sintering can be appropriately changed and selected.

[0029]

As is clear from the above description, according to the present invention, even when a borderless contact process, which is an effective means for reducing the area of a device chip, is adopted, a highly reliable upper layer wiring can be obtained. A contact can be formed. Therefore, the present invention is extremely valuable in promoting miniaturization, high integration, and high performance of a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a state in which resist patterning is performed on an interlayer insulating film covering a lower wiring in a process example in which the present invention is applied to borderless contact formation.

FIG. 2 is a schematic cross-sectional view showing a state in which a recess is formed in a part of a contact hole opened by dry-etching the interlayer insulating film of FIG. 1;

FIG. 3 is a schematic cross-sectional view showing a state in which sintering is performed, and a recessed portion in FIG. 2 is buried with a hillock grown from a lower wiring.

FIG. 4 is a schematic cross-sectional view showing a state where the entire surface of the substrate of FIG. 3 is covered with a second-layer adhesion film.

FIG. 5 is a schematic cross-sectional view showing a state where the entire surface of the substrate of FIG. 4 is covered with a blanket W film.

FIG. 6 is a schematic cross-sectional view showing a state in which a plug is formed by etching back the blanket W film of FIG. 5 and an upper layer wiring is further formed.

FIGS. 7A and 7B are views for explaining the structure of a typical aligned contact, wherein FIG. 7A is a top view and FIG. 7B is a cross-sectional view taken along line AA.

FIGS. 8A and 8B are diagrams illustrating the structure of a typical borderless contact, wherein FIG. 8A is a top view and FIG.
It is a line sectional view.

FIG. 9 is a schematic cross-sectional view showing a state in which a coverage failure of an adhesion film has occurred inside a recess due to misalignment of a contact hole in a conventional borderless contact.

FIG. 10 shows a blanket W in the contact hole of FIG.
FIG. 4 is a schematic cross-sectional view showing a state in which a cavity is formed in a recess when a film is embedded.

[Explanation of symbols]

1. Insulating film (SiOx) 2. First-layer adhesion film (Ti / T)
iN) 3 ... First-layer metal film (Al) 3h ... Hillock 4 ...
First layer antireflection film (TiN) 5 ... Lower wiring 6a ... Contact hole (no alignment deviation) 6 ... Interlayer insulating film (SiOx) 6b ... Contact hole (with alignment deviation)
9: Depressed portion 10: Second layer adhesion film 11: Blanket W film 12: Plug 16: Upper layer wiring

Claims (4)

[Claims] 1. A first step of forming a lower wiring including an Al-based metal film on a substrate, and a connection hole having an opening diameter equal to a line width of the lower wiring in an insulating film covering the lower wiring. A second step of exposing the upper surface of the lower wiring, or a part of the upper surface and at least a part of the side wall surface, to the bottom of the connection hole; and performing sintering on the base to overlap the lower wiring. A third step of substantially flattening the bottom by growing hillocks from the surface of the Al-based metal film so as to fill a recess formed in the bottom of the connection hole due to misalignment; And a fourth step of embedding with a material film. 2. The method according to claim 1, further comprising: forming a lower layer wiring in which an antireflection film capable of suppressing hillock growth is laminated on the Al-based metal film in the first step. 2. The method according to claim 1, wherein the growth is performed only from the side wall surface of the Al-based metal film exposed at the bottom. 3. The method according to claim 1, wherein the conductive material film includes an adhesion film and a high-melting metal film laminated thereon. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the film formation of the adhesion film in the fourth step is performed in the same sputtering apparatus after the sintering in the third step. .