JP2018139290A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device.SOLUTION: A semiconductor device comprises: coils CL1 formed on a semiconductor substrate SB via a first insulation film; a second insulation film formed so as to cover the first insulation film and the coils CL1; a pad PD1 formed on the second insulation film; a laminated film LF which is formed on the second insulation film and has an opening OP1 for exposing a part of the pad PD1; and coils CL2 formed on the laminated insulation film. The coils CL2 are arranged above the coils CL1 and the coils CL2 and the coils CL1 are magnetically coupled with each other. The laminated film LF is composed of a silicon oxide film LF1, a silicon nitride film LF2 on the silicon oxide film F1 and a resin film LF3 on the silicon nitride film LF2.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and can be suitably used for, for example, a semiconductor device including a coil and a manufacturing method thereof.

  As a technique for transmitting an electric signal between two circuits having different electric signal potentials, there is a technique using a photocoupler. The photocoupler has a light emitting element such as a light emitting diode and a light receiving element such as a phototransistor, and converts an inputted electric signal into light by the light emitting element, and returns this light to an electric signal by the light receiving element. An electrical signal is transmitted.

  In addition, a technique for transmitting an electrical signal by magnetically coupling (inductively coupling) two inductors has been developed.

  Japanese Unexamined Patent Application Publication No. 2008-270465 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2008-277564 (Patent Document 2) disclose techniques related to microtransformers.

JP 2008-270465 A JP 2008-277564 A

  As a technique for transmitting an electric signal between two circuits having different electric signal potentials, there is a technique using a photocoupler. Since a photocoupler has a light emitting element and a light receiving element, Miniaturization is difficult. In addition, there is a limit to its adoption, such as failure to follow the electrical signal when the frequency of the electrical signal is high.

  On the other hand, in a semiconductor device that transmits an electrical signal using a magnetically coupled inductor, the inductor can be formed by using a microfabrication technique of the semiconductor device, so that the size of the device can be reduced. The characteristics are also good. For this reason, it is desirable to proceed with its development.

  For this reason, it is desirable to improve the reliability as much as possible even in a semiconductor device including such an inductor.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device includes a first coil and a first pad disposed above a semiconductor substrate, a second coil disposed above the first coil, a first coil, and a second coil. And a laminated insulating film interposed between the coils. The laminated insulating film includes a silicon oxide film, a silicon nitride film on the silicon oxide film, and a resin film on the silicon nitride film, and a part of the first pad is covered with the laminated insulating film. It has been broken.

  According to one embodiment, a method of manufacturing a semiconductor device includes a step of forming a first insulating film on a semiconductor substrate, a step of forming a first coil on the first insulating film, and the first Forming a second insulating film on the insulating film so as to cover the first coil; and forming a first pad on the second insulating film. And forming a laminated insulating film having a first opening exposing the first pad on the first insulating film; and forming a second coil and a first wiring on the laminated insulating film. And have. The second coil is disposed above the first coil, and the laminated insulating film includes a silicon oxide film, a silicon nitride film on the silicon oxide film, and a resin film on the silicon nitride film.

  According to one embodiment, the reliability of a semiconductor device can be improved.

FIG. 11 is a circuit diagram illustrating an example of an electronic device using the semiconductor device of one embodiment. It is explanatory drawing which shows the example of signal transmission. It is principal part sectional drawing of the semiconductor device of one embodiment. It is principal part sectional drawing of the semiconductor device of one embodiment. It is a top view of a pad. It is a top view which shows the lower layer of a pad. It is principal part sectional drawing in the manufacturing process of the semiconductor device of one Embodiment. FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; FIG. 23 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 22; FIG. 24 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 23; FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 24; FIG. 26 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25; FIG. 27 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 26; FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27; FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29; FIG. 31 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 30; 1 is a circuit diagram illustrating a circuit configuration of a transformer formed in a semiconductor device according to an embodiment. FIG. It is a principal part top view of the semiconductor device of one embodiment. It is a principal part top view of the semiconductor device of one embodiment. It is principal part sectional drawing of the semiconductor device of one embodiment. It is principal part sectional drawing of the semiconductor device of one embodiment. It is a principal part top view of the semiconductor device of a modification. It is a principal part top view of the semiconductor device of a modification. It is a principal part top view of the semiconductor device of another modification. It is a principal part top view of the semiconductor device of another modification. It is a top view which shows the semiconductor package of one Embodiment. It is sectional drawing which shows the semiconductor package of one embodiment. It is principal part sectional drawing of the semiconductor device of other embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
<About circuit configuration>
FIG. 1 is a circuit diagram illustrating an example of an electronic device (semiconductor device) using a semiconductor device (semiconductor chip) according to an embodiment. In FIG. 1, a portion surrounded by a dotted line is formed in the semiconductor chip CP1, a portion surrounded by a one-dot chain line is formed in the semiconductor chip CP2, and a portion surrounded by a two-dot chain line is a semiconductor package PKG. Is formed inside.

  The electronic device shown in FIG. 1 includes a semiconductor package PKG that includes semiconductor chips CP1 and CP2. A transmission circuit TX1, a reception circuit RX2, and a control circuit CC are formed in the semiconductor chip CP1, and a reception circuit RX1, a transmission circuit TX2, and a drive circuit DR are formed in the semiconductor chip CP2.

  The transmission circuit TX1 and the reception circuit RX1 are circuits for transmitting a control signal from the control circuit CC to the drive circuit DR. The transmission circuit TX2 and the reception circuit RX2 are circuits for transmitting a signal from the drive circuit DR to the control circuit CC. The control circuit CC controls or drives the drive circuit DR, and the drive circuit DR drives the load LOD. The semiconductor chips CP1 and CP2 are built in the semiconductor package PKG, and the load LOD is provided outside the semiconductor package PKG.

  A transformer (transformer, converter, magnetic coupling element, electromagnetic coupling element) TR1 including coils (inductors) CL1a and CL2a magnetically coupled (inductively coupled) is interposed between the transmission circuit TX1 and the reception circuit RX1. Thus, a signal can be transmitted from the transmission circuit TX1 to the reception circuit RX1 via the transformer TR1 (that is, via the magnetically coupled coils CL1a and CL2a). Thereby, the reception circuit RX1 in the semiconductor chip CP2 can receive the signal transmitted by the transmission circuit TX1 in the semiconductor chip CP1. Therefore, the control circuit CC can transmit a signal (control signal) to the drive circuit DR via the transmission circuit TX1, the transformer TR1, and the reception circuit RX1. The transformer TR1 (coils CL1a, CL2a) is formed in the semiconductor chip CP1. Coil CL1a and coil CL2a can each be regarded as an inductor. The transformer TR1 can also be regarded as a magnetic coupling element.

  In addition, a transformer (transformer, converter, magnetic coupling element, electromagnetic coupling element) TR2 including coils (inductors) CL1b and CL2b that are magnetically coupled (inductively coupled) is interposed between the transmitting circuit TX2 and the receiving circuit RX2. Thus, a signal can be transmitted from the transmission circuit TX2 to the reception circuit RX2 via the transformer TR2 (that is, via the magnetically coupled coils CL1b and CL2b). Thereby, the reception circuit RX2 in the semiconductor chip CP1 can receive the signal transmitted by the transmission circuit TX2 in the semiconductor chip CP2. Therefore, the drive circuit DR can transmit a signal to the control circuit CC via the transmission circuit TX2, the transformer TR2, and the reception circuit RX2. The transformer TR2 (coils CL1b, CL2b) is formed in the semiconductor chip CP2. The coil CL1b and the coil CL2b can also be regarded as inductors. The transformer TR2 can also be regarded as a magnetic coupling element.

  The transformer TR1 is formed by coils CL1a and CL2a formed in the semiconductor chip CP1, but the coil CL1a and the coil CL2a are not connected by a conductor but are magnetically coupled. For this reason, when a current flows through the coil CL1a, an induced electromotive force is generated in the coil CL2a in accordance with the change in the current, and the induced current flows. The coil CL1a is a primary coil, and the coil CL2a is a secondary coil. Using this, a signal is sent from the transmission circuit TX1 to the coil CL1a (primary coil) of the transformer TR1 to cause a current to flow, and an induced current (or induced induction) generated in the coil CL2a (secondary coil) of the transformer TR1 accordingly. By detecting (receiving) the power) by the receiving circuit RX1, the signal corresponding to the signal transmitted by the transmitting circuit TX1 can be received by the receiving circuit RX1.

  The transformer TR2 is formed by coils CL1b and CL2b formed in the semiconductor chip CP2, but the coil CL1b and the coil CL2b are not connected by a conductor but are magnetically coupled. For this reason, when a current flows through the coil CL1b, an induced electromotive force is generated in the coil CL2b according to the change in the current, and the induced current flows. The coil CL1b is a primary coil, and the coil CL2b is a secondary coil. Using this, a signal is sent from the transmission circuit TX2 to the coil CL1b (primary coil) of the transformer TR2 to cause a current to flow, and the induced current (or induced induction) generated in the coil CL2b (secondary coil) of the transformer TR2 accordingly. By detecting (receiving) the power) by the reception circuit RX2, the reception circuit RX2 can receive a signal corresponding to the signal transmitted by the transmission circuit TX2.

  A path from the control circuit CC to the drive circuit DR via the transmission circuit TX1, the transformer TR1 and the reception circuit RX1, and a path from the drive circuit DR to the control circuit CC via the transmission circuit TX2, the transformer TR2 and the reception circuit RX2. Thus, signal transmission / reception is performed between the semiconductor chip CP1 and the semiconductor chip CP2. That is, the signal transmitted by the transmission circuit TX1 is received by the reception circuit RX1, and the signal transmitted by the transmission circuit TX2 is received by the reception circuit RX2, thereby transmitting and receiving signals between the semiconductor chip CP1 and the semiconductor chip CP2. be able to. As described above, the transmission of the signal from the transmission circuit TX1 to the reception circuit RX1 includes the transformer TR1 (that is, the magnetically coupled coils CL1a and CL2a), and the transmission of the signal from the transmission circuit TX2 to the reception circuit RX2. Transformer TR2 (that is, magnetically coupled coils CL1b and CL2b) intervenes. The drive circuit DR can drive the load LOD in accordance with a signal transmitted from the semiconductor chip CP1 to the semiconductor chip CP2 (that is, a signal transmitted from the transmission circuit TX1 to the reception circuit RX1 via the transformer TR1). As the load LOD, there are various loads depending on the application. For example, a motor or the like can be exemplified.

  The semiconductor chip CP1 and the semiconductor chip CP2 have different voltage levels (reference potentials). For example, the semiconductor chip CP1 is connected to a low voltage region having a circuit operated or driven at a low voltage (for example, several V to several tens V) via a bonding wire BW and a lead LD described later. Further, the semiconductor chip CP2 has a bonding wire BW (described later) in a high voltage region having a circuit (for example, a load LOD or a switch for the load LOD) that is operated or driven at a voltage (for example, 100 V or more) higher than the low voltage. And connected via a lead LD or the like. However, since signal transmission between the semiconductor chips CP1 and CP2 is performed via the transformers TR1 and TR2, it is possible to transmit signals between different voltage circuits.

  In the transformers TR1 and TR2, a large potential difference may occur between the primary coil and the secondary coil. In other words, since a large potential difference may occur, a primary coil and a secondary coil that are magnetically coupled without being connected by a conductor are used for signal transmission. For this reason, when forming the transformer TR1 in the semiconductor chip CP1, it is necessary to increase the insulation breakdown voltage between the coil CL1a and the coil CL2a as much as possible. The semiconductor chip CP1, the semiconductor package PKG incorporating the semiconductor chip CP1, or This is important in improving the reliability of electronic devices using the same. Further, when forming the transformer TR2 in the semiconductor chip CP2, it is preferable to make the insulation breakdown voltage between the coil CL1b and the coil CL2b as high as possible, the semiconductor chip CP2, the semiconductor package PKG incorporating the semiconductor chip CP2, or This is important in improving the reliability of electronic devices using the above. For this reason, in this embodiment, the configuration of the insulating film (laminated film LF described later) interposed between the primary coil and the secondary coil in the semiconductor chip (CP1, CP2) is devised. This will be described in detail later.

  Although FIG. 1 shows a case where the control circuit CC is built in the semiconductor chip CP1, as another form, the control circuit CC can be built in a semiconductor chip other than the semiconductor chips CP1 and CP2. 1 shows the case where the drive circuit DR is built in the semiconductor chip CP2, the drive circuit DR can be built in a semiconductor chip other than the semiconductor chips CP1 and CP2 as another form.

<About signal transmission examples>
FIG. 2 is an explanatory diagram illustrating an example of signal transmission.

  The transmission circuit TX1 modulates the square wave signal SG1 input to the transmission circuit TX1 into a differential wave signal SG2, and sends it to the coil CL1a (primary coil) of the transformer TR1. When the current of the differential wave signal SG2 flows through the coil CL1a (primary coil) of the transformer TR1, a signal SG3 corresponding to the current flows through the coil CL2a (secondary coil) of the transformer TR1 due to the induced electromotive force. The signal SG3 is amplified by the receiving circuit RX2 and further modulated into a square wave, whereby a square wave signal SG4 is output from the receiving circuit RX2. Accordingly, the signal SG4 corresponding to the signal SG1 input to the transmission circuit TX1 can be output from the reception circuit RX2. In this way, a signal is transmitted from the transmission circuit TX1 to the reception circuit RX1. Signal transmission from the transmission circuit TX2 to the reception circuit RX2 can be similarly performed.

  In FIG. 2, an example of signal transmission from the transmission circuit to the reception circuit has been described. However, the present invention is not limited to this, and various modifications can be made. Any method that transmits signals can be used.

<About the structure of the semiconductor chip>
FIG. 3 is a principal part sectional view showing a sectional structure of the semiconductor device of the present embodiment. The semiconductor device shown in FIG. 3 is a semiconductor device (semiconductor chip) corresponding to the semiconductor chip CP1 or the semiconductor chip CP2. FIG. 4 is a cross-sectional view of the main part of the semiconductor device according to the present embodiment. FIG. 4 is a cross-sectional view showing the structure above the interlayer insulating film IL2 in the peripheral circuit formation region 1A. FIG. 5 is a plan view of the pad PD1, but for the sake of easy understanding, the position of the opening OP1a of the silicon oxide film LF1 is indicated by a one-dot chain line, and the position of the opening OP1b of the silicon nitride film LF2 is illustrated. It is indicated by a dotted line, and the position of the opening OP1c of the resin film LF3 is indicated by a two-dot chain line. FIG. 6 is a plan view showing the lower layer of the pad PD1, and the outer peripheral position of the pad PD1 is indicated by a dotted line for easy understanding.

  The semiconductor device of the present embodiment is a semiconductor device (semiconductor chip) formed using a semiconductor substrate SB made of single crystal silicon or the like, and has a peripheral circuit formation region 1A and a transformer formation region 1B. . The peripheral circuit formation region 1A and the transformer formation region 1B correspond to different planar regions of the main surface of the same semiconductor substrate SB.

  As shown in FIG. 3, a semiconductor element such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on a semiconductor substrate SB made of single crystal silicon or the like constituting the semiconductor device (semiconductor chip) of the present embodiment. Yes. This semiconductor element is formed in the peripheral circuit formation region 1A.

  For example, the p-type well PW and the n-type well NW are formed on the semiconductor substrate SB1 in the peripheral circuit formation region 1A, and the gate electrode G1 for the n-channel type MISFET is formed on the p-type well PW via the gate insulating film GF. A gate electrode G2 for a p-channel type MISFET is formed on the n-type well NW via a gate insulating film GF. The gate insulating film GF is made of, for example, a silicon oxide film, and the gate electrodes G1, G2 are made of, for example, a polycrystalline silicon film (doped polysilicon film) into which impurities are introduced.

  An n-type semiconductor region NS for the source / drain of the n-channel type MISFET is formed in the p-type well PW of the semiconductor substrate SB, and the source / drain of the p-channel type MISFET is formed in the n-type well NW of the semiconductor substrate SB. A p-type semiconductor region PS for drain is formed. An n-channel MISFET is formed by the gate electrode G1, the gate insulating film GF below the gate electrode G1, and the n-type semiconductor regions NS (source / drain regions) on both sides of the gate electrode G1. Also, a p-channel MISFET is formed by the gate electrode G2, the gate insulating film GF below the gate electrode G2, and the p-type semiconductor regions PS (source / drain regions) on both sides of the gate electrode G2. The n-type semiconductor region NS can also have an LDD (Lightly doped Drain) structure. In this case, a sidewall insulating film, also referred to as a sidewall spacer, is formed on the sidewall of the gate electrode G1. Similarly, the p-type semiconductor region PS may have an LDD structure. In this case, a sidewall insulating film, also referred to as a sidewall spacer, is formed on the sidewall of the gate electrode G1.

  Here, the MISFET is described as an example of the semiconductor element formed in the peripheral circuit formation region 1A. However, in addition to this, a capacitor element, a resistance element, a memory element, or a transistor having another configuration may be used as the peripheral circuit. It may be formed in the formation region 1A. In the case of the semiconductor chip CP1, the control circuit CC, the transmission circuit TX1, and the reception circuit RX2 are formed by the semiconductor elements formed in the peripheral circuit formation region 1A. In the case of the semiconductor chip CP2, the peripheral circuit formation region 1A The drive circuit DR, the reception circuit RX1, and the transmission circuit TX2 are formed by the semiconductor elements formed in the above.

  Although a single crystal silicon substrate is described as an example of the semiconductor substrate SB here, an SOI (Silicon On Insulator) substrate or the like can be used as the semiconductor substrate SB as another embodiment.

  On the semiconductor substrate SB, a multilayer wiring structure is formed by a plurality of interlayer insulating films and a plurality of wiring layers.

  That is, a plurality of interlayer insulating films IL1, IL2, and IL3 are formed on the semiconductor substrate SB, and plugs V1, via portions V2, V3 and wirings M1, M2, M3 are formed on the plurality of interlayer insulating films IL1, IL2, IL3. Is formed.

  Specifically, an interlayer insulating film IL1 is formed as an insulating film on the semiconductor substrate SB so as to cover the MISFET, and a wiring M1 is formed on the interlayer insulating film IL1. The wiring M1 is a wiring of the first wiring layer (lowermost wiring layer). An interlayer insulating film IL2 is formed as an insulating film on the interlayer insulating film IL1 so as to cover the wiring M1, and the wiring M2 is formed on the interlayer insulating film IL2. The wiring M2 is a wiring of a second wiring layer that is a wiring layer one layer higher than the first wiring layer. An interlayer insulating film IL3 is formed as an insulating film on the interlayer insulating film IL2 so as to cover the wiring M2, and the wiring M3 is formed on the interlayer insulating film IL3. The wiring M3 is a wiring of a third wiring layer that is a wiring layer one layer higher than the second wiring layer.

  The plug V1 is made of a conductor and is formed below the wiring M1, that is, is formed so as to penetrate the interlayer insulating film IL1 in the interlayer insulating film IL1, and the upper surface of the plug V1 is in contact with the lower surface of the wiring M1. It is electrically connected to the wiring M1. The bottom of the plug V1 is connected to various semiconductor regions (for example, the n-type semiconductor region NS or the p-type semiconductor region PS) formed in the semiconductor substrate SB, the gate electrodes G1, G2, and the like. Thereby, the wiring M1 is electrically connected to various semiconductor regions, gate electrodes G1, G2, and the like formed in the semiconductor substrate SB via the plug V1.

  The via portion V2 is made of a conductor and is formed between the wiring M2 and the wiring M1, that is, is formed in the interlayer insulating film IL2, and connects the wiring M2 and the wiring M1. The via portion V2 can also be formed integrally with the wiring M2. The via portion V3 is made of a conductor and is formed between the wiring M3 and the wiring M2, that is, is formed in the interlayer insulating film IL3, and connects the wiring M3 and the wiring M2. The via part V3 can also be formed integrally with the wiring M3.

  In the semiconductor device of the present embodiment, the third wiring layer, that is, the wiring M3 is the uppermost layer wiring. In other words, the first wiring layer (wiring M1), the second wiring layer (wiring M2), and the third wiring layer (wiring M3) provide a desired connection of the semiconductor element (for example, the MISFET) formed on the semiconductor substrate SB. And can perform a desired operation.

  A pad (pad region, pad electrode) PD1 is formed by the third wiring layer which is the uppermost layer wiring. That is, the pad PD1 is formed in the same layer as the wiring M3. That is, the wiring M3 and the pad PD1 are formed in the same process by the same conductive layer. For this reason, the pad PD1 is formed on the interlayer insulating film IL3. The pad PD1 can be regarded as a part of the wiring M3, but the wiring M3 is covered with the laminated film LF, whereas at least a part of the pad PD1 is exposed from the opening OP1 of the laminated film LF. ing. However, a part of the pad PD1 is covered with the laminated film LF. That is, the pad PD1 is exposed from the opening OP1, but the portion of the pad PD1 that does not overlap the opening OP1 in plan view is covered with the laminated film LF. Specifically, the center portion of the pad PD1 is not covered with the laminated film LF, and the outer peripheral portion of the pad PD1 is covered with the laminated film LF. Before the rewiring RW is formed, it is possible to perform a test (test process, corresponding to a probe test described later) as to whether or not the semiconductor device performs a desired operation using the pad PD1. The pad PD1 is preferably made of a conductive material (a conductive material exhibiting metal conduction) containing aluminum as a main component (main component). Examples of suitable materials for the pad PD1 include a compound or alloy of Al (aluminum) and Si (silicon), a compound or alloy of Al (aluminum) and Cu (copper), or Al (aluminum) and There is a compound or alloy of Si (silicon) and Cu (copper), and the composition ratio of Al (aluminum) is preferably larger than 50 atomic% (that is, Al-rich). FIG. 3 shows one pad PD1, but actually, one or more pads PD1 are formed, and preferably a plurality of pads PD1 are formed.

  Also, as shown in FIGS. 4 to 6, a via portion V3 can be provided immediately below the pad PD1, and the pad PD1 can be electrically connected to the wiring M2 via the via portion V3. As another form, a wiring M3 formed integrally with the pad PD1 is provided, and the wiring M3 formed integrally with the pad PD1 is connected via a via portion V3 provided immediately below the wiring M3. By being connected to the wiring M2, the pad PD1 can be electrically connected to the wiring M2.

  FIG. 3 shows a case where the number of wiring layers formed on the semiconductor substrate SB1 (not including the rewiring RW) is three (a total of three layers of wirings M1, M2, and M3). The number of wiring layers is not limited to three and can be variously changed, but two or more are preferable. Further, if the number of wiring layers (not including rewiring RW) is three or more, the coil CL1 formed in the same layer as the second wiring layer can be drawn out by the wiring (leading wiring) of the first wiring layer. This makes it easier to lay out the wiring.

  As shown in FIGS. 3 and 4, a laminated film (laminated insulating film) LF is formed on the interlayer insulating film IL3 so as to cover the wiring M3, and a rewiring RW is formed on the laminated film LF. Has been. The laminated film LF includes a silicon oxide film LF1, a silicon nitride film LF2 on the silicon oxide film LF1, and a resin film LF3 on the silicon nitride film LF2. Since the silicon oxide film LF1, the silicon nitride film LF2, and the resin film LF3 are respectively insulating films, the stacked film LF includes a plurality of insulating films (specifically, the silicon oxide film LF1, the silicon nitride film LF2, and the resin film LF3). These three insulating films) can be regarded as a laminated insulating film.

  The pad PD1 is exposed from the opening OP1 of the laminated film LF, and the rewiring RW is also formed on the pad PD1 exposed from the opening OP1. That is, the rewiring RW is formed on the stacked film LF including the pad PD1 exposed from the opening OP1, and is electrically connected to the pad PD1. The rewiring RW is a wiring that draws out the pad PD1 which is a part of the uppermost wiring (here, the third wiring layer) to a desired region (pad PD2) of the semiconductor chip. That is, the rewiring RW is formed so as to extend on the stacked film LF from the pad PD1 exposed from the opening OP1 of the stacked film LF to the pad PD2 on the stacked film LF.

  The pad (pad region, pad electrode, bonding pad) PD2 is formed of the same conductive layer as the rewiring RW and is formed integrally with the rewiring RW. For this reason, the pad PD2 is also formed on the laminated film LF (that is, on the resin film LF3 of the laminated film LF), and the pad PD2 is electrically connected to the rewiring RW. Accordingly, the pad PD2 is electrically connected to the pad PD1 through the rewiring RW. FIG. 3 shows one pad PD2, but actually, one or more pads PD2 are formed, and preferably a plurality of pads PD2 are formed.

  In plan view, the region in which the pad PD2, the rewiring RW, and the pad PD1 are arranged is different from the region in which the coil CL1, the coil CL2, and the pad PD3 are arranged. That is, the pad PD2, the rewiring RW, and the pad PD1 are disposed at positions that do not overlap with the coil CL1, the coil CL2, and the pad PD3 in plan view.

  The laminated film LF has an opening OP1 that exposes at least part of the pad PD1, but the laminated film LF is a laminated film of the silicon oxide film LF1, the silicon nitride film LF2, and the resin film LF3. The opening OP1 of the laminated film LF is formed by the opening OP1c of the resin film LF3, the opening OP1b of the silicon nitride film LF2, and the opening OP1a of the silicon oxide film LF1 (see FIGS. 4 and 5). The relationship among the opening OP1a, the opening OP1b, and the opening OP1c is as shown in FIGS. 4 and 5, which will be described later.

  In FIG. 4, for easy understanding of the drawing, the rewiring RW and the pad PD2 are shown in an integrated manner without separating a later-described copper film CF and seed film SE.

  As shown in FIG. 3, a transformer having a coil (inductor) CL1 and a coil (inductor) CL2 is formed in the transformer forming region 1B. That is, in the transformer forming region 1B, the coil CL1 that is the primary coil of the transformer and the coil CL2 that is the secondary coil of the transformer are formed on the semiconductor substrate SB1. In the case of the semiconductor chip CP1, the coil CL1 corresponds to the coil CL1a, the coil CL2 corresponds to the coil CL2a, and the transformer formed by the coil CL1 and the coil CL2 corresponds to the transformer TR1. In the case of the semiconductor chip CP2, the coil CL1 corresponds to the coil CL1b, the coil CL2 corresponds to the coil CL2b, and the transformer formed by the coil CL1 and the coil CL2 corresponds to the transformer TR2.

  The coil CL1 and the coil CL2 are not formed in the same layer, but are formed in different layers, and an insulating layer is interposed between the coil CL1 and the coil CL2. The lower coil CL1 is not formed in contact with the semiconductor substrate SB but is formed on the semiconductor substrate SB via an insulating layer. Specifically, the coil CL1 is formed on the interlayer insulating film (here, the interlayer insulating film IL1) formed on the semiconductor substrate SB1.

  The coil CL1 is formed in a lower layer than the coil CL2, and the coil CL2 is formed in an upper layer than the coil CL1. In the present embodiment, the upper coil CL2 of the coils CL1 and CL2 is formed on the laminated film LF. That is, the coil CL2 is formed on the laminated film LF and is disposed above the coil CL1. That is, the coil CL2 is formed on the resin film LF3 of the laminated film LF. For this reason, the coil CL2 is in contact with the resin film LF3.

  The coil CL2 is formed in the same process by the same conductive layer as the rewiring RW. That is, the coil CL2 is formed in the same layer as the rewiring RW. For this reason, the coil CL2 and the rewiring RW are made of the same material.

  In the transformer forming region 1B, a coil CL2 is formed on the laminated film LF, and a pad (pad region, pad electrode, bonding pad) PD3 is also formed. The pad PD3 is formed of the same conductive layer as the coil CL2, and is formed integrally with the coil CL2. For this reason, the pad PD3 is also formed on the laminated film LF (that is, on the resin film LF3 of the laminated film LF), and the pad PD3 is electrically connected to the coil CL2.

  Therefore, the pad PD2, the rewiring RW, the pad PD3, and the coil CL2 are formed in the same layer by the same conductive layer, and the pad PD2 is formed integrally with the rewiring RW and electrically connected thereto. The pad PD3 is formed integrally with the coil CL2 and is electrically connected. However, the rewiring RW and the coil CL2 are separated and are not connected by a conductor. The pad PD2 and the pad PD3 are separated and are not connected by a conductor. The pad PD2 and the coil CL2 are separated and are not connected by a conductor. The pad PD3 and the rewiring RW are separated and are not connected by a conductor. The pad PD2 is electrically connected to the pad PD1 via the rewiring RW, but the pad PD3 is not connected to the pad PD1 by a conductor. In the transformer forming region 1B, the coil CL1, the coil CL2, and the pad PD3 are formed, but the pad PD1, the rewiring RW, and the pad PD2 are not formed.

  The coil CL1 on the lower layer side of the coils CL1 and CL2 is formed of a lower wiring layer than the uppermost layer wiring (here, the third wiring layer) in the multilayer wiring structure excluding the rewiring RW. Here, the coil CL1 is formed by the second wiring layer below the third wiring layer which is the uppermost layer wiring. That is, the coil CL1 is formed in the same layer as the wiring M2.

  Since the coil CL1 is formed of the second wiring layer, the coil CL1 can be formed of the same layer as the wiring M2 in the same process. For example, when the wiring M2 is formed by patterning a conductive film formed over the interlayer insulating film IL2, not only the wiring M2 but also the coil CL1 can be formed when the conductive film is patterned. For example, when the wiring M2 is formed using the damascene method, the coil CL1 can also be formed using the damascene method in the same process as the wiring M2. In this case, the wiring M2 and the coil CL1 are formed of the interlayer insulating film IL2. It is formed of a conductive film embedded in the groove (for example, a conductive film mainly composed of copper).

  A plurality of insulating layers are interposed between the coil CL2 and the coil CL1, but specifically, an interlayer insulating film IL3 and a laminated film LF are interposed. That is, the interlayer insulating film IL3, the silicon oxide film LF1, the silicon nitride film LF2, and the resin film LF3 are interposed between the coil CL2 and the coil CL1 in this order from the bottom. For this reason, the coil CL2 and the coil CL1 are not connected by a conductor and are electrically insulated. However, the coil CL2 and the coil CL1 are magnetically coupled.

  Accordingly, the lower-layer coil CL1 is formed in the same layer as the wiring M2, which is the second wiring layer, and the interlayer insulating film IL3, the silicon oxide film LF1, the silicon nitride film LF2, and the resin film LF3 are disposed on the coil CL1. Thus, the coil CL2 is formed.

  The resin film LF3 is preferably a polyimide film. A polyimide film is a polymer containing an imide bond in a repeating unit, and is a kind of organic insulating film. As the resin film LF3, in addition to the polyimide film, other organic insulating films such as epoxy-based, PBO-based, acrylic-based, and WRP-based resins can also be used. Polyimide resin is an organic resin that is suitably used for devices that require high heat resistance of 200 ° C. or higher, but can be properly used according to the mechanical strength such as the thermal expansion coefficient and ductility of the material, the curing temperature, and the like. .

  An insulating protective film (surface protective film, insulating film, protective insulating film) PA is formed on the laminated film LF, that is, on the resin film LF3 so as to cover the rewiring RW and the coil CL2. Since the protective film PA is an insulating film, it can also be regarded as a protective insulating film. The rewiring RW and the coil CL2 are covered and protected by the protective film PA. As the protective film PA, a resin film is preferable, and for example, a polyimide film can be suitably used. The protective film PA is the outermost film of the semiconductor chip (semiconductor device).

  The pads PD2 and PD3 are exposed from the openings OP2 and OP3 of the protective film PA, respectively. That is, by providing the opening OP2 on the pad PD2, the pad PD2 is exposed from the opening OP2 of the protective film PA, and by providing the opening OP3 on the pad PD3, the pad PD3 is protected by the protective film PA. It is exposed from the opening OP3. Therefore, conductive connection members such as bonding wires BW described later can be connected to the pads PD2 and PD3 exposed from the openings OP2 and OP3 of the protective film PA, respectively.

  Further, it is preferable to form a base metal film UM on each of the pads PD2 and PD3. That is, the base metal film UM is formed on the pad PD2, and the base metal film UM on the pad PD2 is exposed from the opening OP2 of the protective film PA. Further, a base metal film UM is formed on the pad PD3, and the base metal film UM on the pad PD3 is exposed from the opening OP3 of the protective film PA. As a result, a conductive connecting member such as a bonding wire BW described later is connected to the underlying metal film UM exposed from the openings OP2 and OP3 of the protective film PA, so that the connecting member (bonding wire BW) is connected. Easy to connect. The base metal film UM is made of, for example, a laminated film of a nickel (Ni) film and a gold (Au) film on the nickel (Ni) film.

  The protective film PA is preferably formed, but can be omitted. However, when the protective film PA is formed, the rewiring RW and the coil CL2 can be covered and protected by the protective film PA, so that advantages such as further improvement in reliability and ease of handling of the semiconductor chip can be obtained.

  When the semiconductor device of FIG. 3 is applied to the semiconductor chip CP1, the transmission circuit TX1 and the coils CL1 and CL2 (which correspond to the coils CL1a and CL2a) are formed in the semiconductor chip CP1, and the semiconductor chip CP1 The transmission circuit TX1 formed in is electrically connected to the coil CL1 through an internal wiring in the semiconductor chip CP1. When the semiconductor device of FIG. 3 is applied to the semiconductor chip CP2, the transmission circuit TX2 and the coils CL1 and CL2 (which correspond to the coils CL1b and CL2b) are formed in the semiconductor chip CP2, and the semiconductor chip The transmission circuit TX2 formed in the CP2 is electrically connected to the coil CL1 via an internal wiring in the semiconductor chip CP2.

  In this case, a transmission signal can be transmitted from the transmission circuit TX1 in the semiconductor chip CP1 to the coil CL1 in the semiconductor chip CP1 via the internal wiring in the semiconductor chip CP1. The pad PD3 connected to the coil CL2 in the semiconductor chip CP1 is electrically connected to the pad PD2 (pad PD2 connected to the rewiring RW) of the semiconductor chip CP2 through a conductive connecting member such as a bonding wire BW described later. And is further electrically connected to the receiving circuit RX1 in the semiconductor chip CP2 via the internal wiring of the semiconductor chip CP2. Thus, in the semiconductor chip CP1, a signal (received signal) received by the coil CL2 from the coil CL1 by electromagnetic induction is transmitted to the semiconductor chip CP2 via the bonding wire BW (connection member) and the internal wiring of the semiconductor chip CP2 described later. Can be transmitted to the receiving circuit RX1.

  Similarly, a transmission signal can be transmitted from the transmission circuit TX2 in the semiconductor chip CP2 to the coil CL1 in the semiconductor chip CP2 via the internal wiring in the semiconductor chip CP2. The pad PD3 connected to the coil CL2 in the semiconductor chip CP2 is electrically connected to the pad PD2 (pad PD2 connected to the rewiring RW) of the semiconductor chip CP1 through a conductive connecting member such as a bonding wire BW described later. And is further electrically connected to the receiving circuit RX2 in the semiconductor chip CP1 via the internal wiring of the semiconductor chip CP1. As a result, in the semiconductor chip CP2, a signal (received signal) received by the coil CL2 from the coil CL1 by electromagnetic induction is sent to the semiconductor chip CP1 via the bonding wire BW (connection member) and the internal wiring of the semiconductor chip CP1 described later. Can be transmitted to the receiving circuit RX2.

<About the manufacturing process>
Next, the manufacturing process of the semiconductor device of this embodiment will be described. The semiconductor device shown in FIG. 3 is manufactured by the following manufacturing process.

  7 to 31 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment. 7 to 31 are cross-sectional views of the cross-sectional area corresponding to FIG. 3 described above.

  First, as shown in FIG. 7, a semiconductor substrate (semiconductor wafer) SB made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is prepared (prepared).

  The semiconductor substrate SB has a peripheral circuit formation region 1A, which is a region where peripheral circuits are to be formed, and a transformer formation region 1B, which is a region where transformers are to be formed. The peripheral circuit formation region 1A and the transformer formation region 1B correspond to different planar regions of the main surface of the same semiconductor substrate SB.

  The peripheral circuits formed in the peripheral circuit formation region 1A are the control circuit CC, the transmission circuit TX1, the reception circuit RX2, and the like in the case of the semiconductor chip CP1, and the drive circuit in the case of the semiconductor chip CP2. DR, receiving circuit RX1, transmitting circuit TX2, and the like. The transformer formed in the transformer forming region 1B is the transformer TR1 in the case of the semiconductor chip CP1, and the transformer TR2 in the case of the semiconductor chip CP2. Accordingly, the coil CL1 and the coil CL2 formed in the transformer forming region 1B are the coil CL1a and the coil CL2a in the case of the semiconductor chip CP1, respectively, and the coil CL1b and the coil CL2b in the case of the semiconductor chip CP2, respectively. It is.

  Next, the element isolation region ST is formed on the main surface of the semiconductor substrate SB by, for example, an STI (Shallow Trench Isolation) method. The element isolation region ST is formed by forming a groove in the semiconductor substrate SB and embedding an insulating film in the groove. In the semiconductor substrate SB, a MISFET is formed in the active region defined (defined) by the element isolation region ST as described later.

  Next, a semiconductor element such as a MISFET is formed on the semiconductor substrate SB (active region thereof) in the peripheral circuit formation region 1A. Below, the process of forming the MISFET will be described.

  First, as shown in FIG. 8, a p-type well PW and an n-type well NW are formed in a semiconductor substrate SB. The p-type well PW and the n-type well NW are each formed by ion implantation, and are formed over a predetermined depth from the main surface of the semiconductor substrate SB.

  Then, gate electrodes G1 and G2 are formed on the main surface of the semiconductor substrate SB via the gate insulating film GF. The gate electrode G1 is formed on the p-type well PW via the gate insulating film GF, and the gate electrode G2 is formed on the n-type well NW via the gate insulating film GF.

  Specifically, the gate electrodes G1 and G2 can be formed through the gate insulating film GF as follows. That is, first, the main surface of the semiconductor substrate SB is cleaned by a cleaning process or the like, and then an insulating film for the gate insulating film GF is formed on the main surface of the semiconductor substrate SB, and then the gate electrodes G1, G1 are formed on the insulating film. A polycrystalline silicon film for G2 is formed. The insulating film for the gate insulating film GF is made of, for example, a silicon oxide film or a silicon oxynitride film and can be formed by, for example, a thermal oxidation method. The polycrystalline silicon film for the gate electrodes G1 and G2 can be formed by, for example, a CVD (Chemical Vapor Deposition) method. This polycrystalline silicon film is made into a doped polysilicon film by doping impurities at the time of film formation or by introducing impurities by ion implantation after film formation, and a low resistance semiconductor film (conductive material film) Has been. In addition, this polycrystalline silicon film can be changed from an amorphous silicon film at the time of film formation to a polycrystalline silicon film by heat treatment after the film formation. Then, by patterning the polycrystalline silicon film using a photolithography technique and an etching technique, gate electrodes G1 and G2 made of the patterned polycrystalline silicon film can be formed. The insulating film for the gate insulating film GF remaining under the gate electrodes G1 and G2 becomes the gate insulating film GF.

  Next, an n-type semiconductor region NS for the source / drain of the n-channel type MISFET is formed in the p-type well PW of the semiconductor substrate SB, and the source of the p-channel type MISFET is formed in the n-type well NW of the semiconductor substrate SB. A p-type semiconductor region PS for drain is formed. The n-type semiconductor region NS and the p-type semiconductor region PS can each be formed by ion implantation. Since ion implantation is prevented in the region immediately below the gate electrodes G1 and G2, the n-type semiconductor region NS is formed in the regions on both sides of the gate electrode G1 in the p-type well PW, and the p-type semiconductor region PS is n It is formed in regions on both sides of the gate electrode G1 in the mold well NW.

When each of the n-type semiconductor region NS and the p-type semiconductor region PS has an LDD structure, the n ⁻ type semiconductor region and the p ⁻ type semiconductor region having low impurity concentration are formed by ion implantation, and then the gate electrodes G1 and G2 are formed. A side wall insulating film (side wall spacer) is formed on the side wall, and then a high impurity concentration n ⁺ type semiconductor region and a p ⁺ type semiconductor region are formed by ion implantation. Thereby, the n-type semiconductor region NS can be an n-type semiconductor region having an LDD structure composed of an n ⁻ type semiconductor region having a low impurity concentration and an n ⁺ type semiconductor region having a high impurity concentration, and a p-type semiconductor. The region PS can be a p-type semiconductor region having an LDD structure including a low impurity concentration p ⁻ type semiconductor region and a high impurity concentration p ⁺ type semiconductor region.

  Next, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed.

  In this manner, an n-channel MISFET and a p-channel MISFET are formed on the semiconductor substrate SB in the peripheral circuit formation region 1A. The gate electrode G1, the gate insulating film GF below the gate electrode G1, and the n-type semiconductor region NS function as a gate electrode, a gate insulating film, and a source / drain region of the n-channel MISFET. The gate electrode G2 and the gate insulating film GF and the p-type semiconductor region PS below the gate electrode G2 function as a gate electrode, a gate insulating film, and a source / drain region of the p-channel MISFET.

  Next, a low-resistance metal silicide layer (not shown) is formed on the n-type semiconductor region NS, the p-type semiconductor region PS, and the upper portions (surface layer portions) of the gate electrodes G1 and G2 by using a salicide (Salicide: Self Aligned Silicide) technique. Can also be formed. For example, by forming a metal film for forming a metal silicide layer on the semiconductor substrate SB and then performing a heat treatment, the metal film is formed in each of the n-type semiconductor region NS, the p-type semiconductor region PS, and the gate electrodes G1, G2. After reacting with the upper layer portion, the unreacted portion of the metal film is removed. Thereby, a metal silicide layer (not shown) can be formed in each upper part (surface layer part) of n type semiconductor region NS, p type semiconductor region PS, and gate electrodes G1, G2. By forming this metal silicide layer, the contact resistance and diffusion resistance of the n-type semiconductor region NS, the p-type semiconductor region PS, and the gate electrodes G1 and G2 can be reduced. In addition, the metal silicide layer may not be formed, or the n-type semiconductor region NS, the p-type semiconductor region PS, and the gate electrodes G1 and G2 are provided with and without the metal silicide layer. You can also.

  Next, as shown in FIG. 9, an interlayer insulating film IL1 is formed on the main surface (entire main surface) of the semiconductor substrate SB. The interlayer insulating film IL1 is formed so as to cover the MISFET formed on the semiconductor substrate SB. That is, the interlayer insulating film IL1 is formed on the main surface of the semiconductor substrate SB so as to cover the n-type semiconductor region NS, the p-type semiconductor region PS, and the gate electrodes G1, G2. Since the interlayer insulating film IL1 is formed over the entire main surface of the semiconductor substrate SB, it is formed in both the peripheral circuit formation region 1A and the transformer formation region 1B. The interlayer insulating film IL1 is, for example, a single film of a silicon oxide film or a laminated film of a silicon nitride film and a silicon oxide film thicker than the silicon nitride film (the silicon nitride film is the lower layer side and the silicon oxide film is the upper layer side) ) Etc.

  After the formation of the interlayer insulating film IL1, the upper surface of the interlayer insulating film IL1 is polished as necessary by polishing the surface (upper surface) of the interlayer insulating film IL1 by a CMP (Chemical Mechanical Polishing) method. To flatten. Even if an uneven shape is formed on the surface of the interlayer insulating film IL1 due to the underlying step, the surface of the interlayer insulating film IL1 is polished by CMP to obtain an interlayer insulating film IL1 whose surface is planarized. be able to.

  Next, the interlayer insulating film IL1 is dry-etched using a photoresist layer (not shown) formed on the interlayer insulating film IL1 by using a photolithography technique as an etching mask, so that a contact hole is formed in the interlayer insulating film IL1. (Through hole, hole) is formed. Then, a conductive plug (connection conductor portion) V1 is formed by embedding a conductive film in this contact hole, as shown in FIG.

  In order to form the plug V1, for example, a barrier conductor film (for example, a titanium film, a titanium nitride film, or the like is formed on the interlayer insulating film IL1 including the inside (on the bottom and side walls) of the contact hole by a sputtering method or a plasma CVD method. These laminated films) are formed. Then, a main conductor film made of a tungsten film or the like is formed so as to fill the contact hole on the barrier conductor film by a CVD method or the like. Thereafter, unnecessary main conductor films and barrier conductor films outside the contact holes (on the interlayer insulating film IL1) are removed by a CMP method or an etch back method. As a result, the upper surface of the interlayer insulating film IL1 is exposed, and the plug V1 is formed by the barrier conductor film and the main conductor film that remain buried in the contact hole of the interlayer insulating film IL1. In FIG. 10, for simplification of the drawing, the plug V1 is shown by integrating the main conductor film and the barrier conductor film. The plug V1 is electrically connected to the n-type semiconductor region NS, the p-type semiconductor region PS, the gate electrode G1, the gate electrode G2, or the like at the bottom thereof.

  Next, as shown in FIG. 11, the wiring M1 of the first wiring layer, which is the lowermost wiring layer, is formed on the interlayer insulating film IL1 in which the plug V1 is embedded. In order to form the wiring M1, first, a conductive film for the first wiring layer is formed on the interlayer insulating film IL1 in which the plug V1 is embedded. For example, the conductive film includes, in order from the bottom, a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof), an aluminum film, and a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof). ) And can be formed using a sputtering method or the like. The aluminum film in this conductive film can be regarded as an aluminum film for forming the wiring M1. Then, the wiring M1 can be formed by patterning the conductive film using a photolithography technique and an etching technique. The upper surface of the plug V1 is in contact with the wiring M1, so that the plug V1 is electrically connected to the wiring M1.

  The aluminum film for forming the wiring M1 is not limited to a pure aluminum film, and a conductive material film containing aluminum as a main component (a conductive material film exhibiting metal conduction) can be used. For example, a compound film or alloy film of Al (aluminum) and Si (silicon), a compound film or alloy film of Al (aluminum) and Cu (copper), or Al (aluminum) and Si (silicon) A compound film or alloy film with Cu (copper) can be suitably used as an aluminum film for forming the wiring M1. The composition ratio of Al (aluminum) in the aluminum film is preferably larger than 50 atomic% (that is, Al-rich). This is not only the aluminum film for forming the wiring M1, but also the aluminum film for forming the wiring M2 (that is, the aluminum film constituting the conductive film CD1 described later), and the aluminum for forming the wiring M3. The same applies to the film (that is, the aluminum film constituting the conductive film CD2 described later).

  Further, the wiring M1 of the first wiring layer can be formed not only in the peripheral circuit formation region 1A but also in the transformer formation region 1B. As the wiring M1 formed in the transformer forming region 1B, for example, wiring (corresponding to lead wirings HW1 and HW2, which will be described later) that electrically connects the coil CL1 and peripheral circuits (such as the transmission circuit TX1 or the transmission circuit TX2). )and so on.

  Here, the case where the wiring M1 is formed by a method of patterning the conductive film has been described. As another form, the wiring M1 can also be formed by a damascene method. In this case, an insulating film is formed on the interlayer insulating film IL1 in which the plug V1 is embedded, then a wiring groove is formed in the insulating film, and a conductive film is embedded in the wiring groove, so that an embedded wiring (for example, embedded wiring) is formed. A wiring M1 as a buried copper wiring) can be formed.

  Next, as shown in FIG. 12, an interlayer insulating film IL2 is formed on the main surface (entire main surface) of the semiconductor substrate SB, that is, on the interlayer insulating film IL1, so as to cover the wiring M1. The interlayer insulating film IL2 is made of a silicon oxide film or the like and can be formed using a CVD method or the like. After the formation of the interlayer insulating film IL2, if necessary, the surface (upper surface) of the interlayer insulating film IL2 may be polished by a CMP method to improve the flatness of the upper surface of the interlayer insulating film IL2.

  Next, the interlayer insulating film IL2 is dry-etched using a photoresist layer (not shown) formed on the interlayer insulating film IL2 by using a photolithography technique as an etching mask, so that a through hole is formed in the interlayer insulating film IL2. (Through hole, hole) is formed. Then, a conductive via portion (connecting conductor portion) V2 is formed by embedding a conductive film in the through hole. The via part V2 can also be regarded as a conductive plug. The via portion V2 can be formed by a method similar to that of the plug V1, but the via portion V2 can be made of a material different from that of the plug V1 and the conductive film. For example, the plug V1 can be mainly composed of a tungsten film, and the via portion V2 can be mainly composed of an aluminum film.

  Next, the wiring M2 of the second wiring layer is formed on the interlayer insulating film IL2 in which the via portion V2 is embedded. In order to form the wiring M2, first, as shown in FIG. 13, a conductive film CD1 for the second wiring layer is formed on the interlayer insulating film IL2 in which the via portion V2 is embedded. For example, the conductive film CD1 includes, in order from the bottom, a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof), an aluminum film, and a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof). Film) and can be formed by sputtering or the like. The conductive film CD1 is a conductive film for the second wiring layer, but also serves as a conductive film for forming the coil CL1. Then, by patterning the conductive film CD1 using a photolithography technique and an etching technique, the wiring M2 and the coil CL1 can be formed as shown in FIG. The wiring M2 and the coil CL1 are each made of a patterned conductive film CD1. The via portion V2 is electrically connected to the wiring M1 when its lower surface is in contact with the wiring M1, and is electrically connected to the wiring M2 when its upper surface is in contact with the wiring M2. That is, the via part V2 electrically connects the wiring M1 and the wiring M2.

  Here, in the transformer forming region 1B, the coil CL1 is formed in the same step as the wiring M2 of the second wiring layer in the same process. That is, when patterning the conductive film CD1 for the second wiring layer, the coil CL1 is formed in the transformer forming region 1B. That is, the conductive film CD1 for the second wiring layer also serves as the conductive film for forming the coil CL1, and after the conductive film CD1 is formed, the conductive film CD1 is patterned using a photolithography technique and an etching technique. As a result, the wiring M2 and the coil CL1 of the second wiring layer are formed.

  Here, the case where the via portion V2 and the wiring M2 are formed in separate steps has been described. As another form, the via portion V2 and the wiring M2 can be formed in the same process. In this case, the via portion V2 is formed integrally with the wiring M2 or the coil CL1. In this case, after forming a through hole for the via portion V2 in the interlayer insulating film IL2, a conductive film CD1 is formed on the interlayer insulating film IL2 so as to fill the through hole, and then the conductive film CD1 is formed by a photolithography technique. Then, the wiring M2 and the coil CL1 are formed by patterning using an etching technique. Thereby, the wiring M2 and the coil CL1 are formed, and the via portion V2 formed integrally with the wiring M2 or the coil CL1 is also formed.

  Here, the case where the wiring M2 and the coil CL1 are formed by a method of patterning the conductive film has been described. As another form, the wiring M2 and the coil CL1 can be formed by a damascene method. In this case, after forming an insulating film on the interlayer insulating film IL2, a wiring groove is formed in the insulating film, and a conductive film is embedded in the wiring groove, thereby providing an embedded wiring (for example, embedded copper wiring). The wiring M2 and the coil CL1 can be formed. Alternatively, the wiring M2 as the embedded wiring (for example, embedded copper wiring) and the coil CL1 can be formed by forming a wiring groove in the interlayer insulating film IL2 and embedding a conductive film in the wiring groove.

  Next, as shown in FIG. 15, an interlayer insulating film IL3 is formed on the main surface (entire main surface) of the semiconductor substrate SB, that is, on the interlayer insulating film IL2, so as to cover the wiring M2. The interlayer insulating film IL3 is made of a silicon oxide film or the like and can be formed using a CVD method or the like. After the formation of the interlayer insulating film IL3, the flatness of the upper surface of the interlayer insulating film IL3 can be improved by polishing the surface (upper surface) of the interlayer insulating film IL3 by a CMP method, if necessary.

  Next, the interlayer insulating film IL3 is dry-etched using a photoresist layer (not shown) formed on the interlayer insulating film IL3 by using a photolithography technique as an etching mask, so that a through hole is formed in the interlayer insulating film IL3. (Through hole, hole) is formed. Then, a conductive via portion (connecting conductor portion) V3 is formed by embedding a conductive film in the through hole. The via part V3 can also be regarded as a conductive plug. The via portion V3 can be formed by the same method using the same conductive material as the via V2.

  Next, the wiring M3 of the third wiring layer is formed on the interlayer insulating film IL3 in which the via part V3 is embedded. In order to form the wiring M3, first, as shown in FIG. 16, a conductive film CD2 for the third wiring layer is formed on the interlayer insulating film IL3 in which the via portion V3 is embedded. For example, the conductive film CD2 includes, in order from the bottom, a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof), an aluminum film, and a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof). Film) and can be formed by sputtering or the like. The conductive film CD2 is a conductive film for the third wiring layer, but also serves as a conductive film for forming the pad PD1. Then, by patterning the conductive film CD2 using a photolithography technique and an etching technique, the wiring M3 and the pad PD1 can be formed as shown in FIG. The wiring M3 and the pad PD1 are each made of a patterned conductive film CD2. The via portion V3 is electrically connected to the wiring M2 when its lower surface is in contact with the wiring M2, and is electrically connected to the wiring M3 or pad PD1 when its upper surface is in contact with the wiring M3 or the pad PD1. That is, the via portion V3 electrically connects the wiring M2 and the wiring M3, or electrically connects the wiring M2 and the pad PD1.

  Here, the case where the via portion V3 and the wiring M3 are formed in separate steps has been described. As another form, the via portion V3, the wiring M3, and the pad PD1 can be formed in the same process. In this case, the via portion V3 is formed integrally with the wiring M3 or the pad PD1. In this case, after forming a through hole for the via portion V3 in the interlayer insulating film IL3, a conductive film CD2 is formed on the interlayer insulating film IL3 so as to fill the through hole, and then the conductive film CD2 is formed by a photolithography technique. Then, the wiring M3 and the pad PD1 are formed by patterning using an etching technique. Thereby, the wiring M3 and the pad PD1 are formed, and the via portion V3 formed integrally with the wiring M3 or the pad PD1 is also formed.

  The planar shape of the pad PD1 can be a substantially rectangular planar shape having sides larger than the wiring width of the wiring M3, for example. The pad PD1 is preferably an aluminum pad mainly composed of aluminum, and the wiring M3 is preferably an aluminum wiring mainly composed of aluminum.

  In addition, as an aluminum film used for an aluminum pad and aluminum wiring, a compound film or alloy film of Al (aluminum) and Si (silicon), or a compound film or alloy of Al (aluminum) and Cu (copper) A film, a compound film or an alloy film of Al (aluminum), Si (silicon), and Cu (copper) can be preferably used. The composition ratio of Al (aluminum) is preferably larger than 50 atomic% (that is, Al-rich).

  Next, as shown in FIG. 18, a silicon oxide film LF1 is formed on the main surface (entire main surface) of the semiconductor substrate SB, that is, on the interlayer insulating film IL3 so as to cover the wiring M3 and the pad PD1. . The silicon oxide film LF1 can be formed by a CVD method or the like. As a method for forming the silicon oxide film LF1, HDP (High Density Plasma) -CVD method is particularly suitable. The thickness (formed film thickness) of the silicon oxide film LF1 can be set to, for example, about 1 to 6 μm.

  In the stage before forming the silicon oxide film LF1, the wiring M3 and the pad PD1 were exposed. However, when the silicon oxide film LF1 is formed, the wiring M3 and the pad PD1 are covered with the silicon oxide film LF1. It is not exposed.

  Next, as shown in FIG. 19, an opening OP1a is formed in the silicon oxide film LF1. The opening OP1a is formed by selectively removing the silicon oxide film LF1 on the pad PD1, and is formed so that the opening OP1a is included in the pad PD1 in plan view. For example, after the silicon oxide film LF1 is formed, a photoresist pattern (not shown) is formed on the silicon oxide film LF1 using a photolithography technique, and this photoresist pattern is used as an etching mask to form a silicon oxide film. By dry-etching LF1, the opening OP1a can be formed in the silicon oxide film LF1. The opening OP1a is formed so as to penetrate the silicon oxide film LF1, and at least a part of the pad PD1 is exposed from the opening OP1a.

  When the opening OP1a is formed in the silicon oxide film LF1, the pad PD1 is exposed from the opening OP1a of the silicon oxide film LF1. At this time, at least a part of the upper surface of the pad PD1 is exposed from the opening OP1a of the silicon oxide film LF1. On the other hand, it is preferable that the side surface (side wall) of the pad PD1 is not exposed from the opening OP1a of the silicon oxide film LF1, but is covered with the silicon oxide film LF1. That is, in plan view, the opening OP1a of the silicon oxide film LF1 overlaps the pad PD1, but the opening OP1a of the silicon oxide film LF1 is preferably included in the pad PD1, that is, the silicon oxide film LF1. The outer periphery of the opening OP1a is preferably on the inner side of the outer periphery of the pad PD1. Further, when the opening OP1a is formed in the silicon oxide film LF1, the pad PD1 is exposed from the opening OP1a of the silicon oxide film LF1, but the wiring M3 other than the pad PD1 is kept covered with the silicon oxide film LF1. Is not exposed. Since the wiring M3 other than the pad PD1 is still covered with the silicon oxide film LF1, it is not exposed.

  Note that the “plan view” refers to a case of viewing in a plane parallel to the main surface of the semiconductor substrate SB.

  Next, as shown in FIG. 20, a silicon nitride film LF2 is formed over the main surface (entire main surface) of the semiconductor substrate SB, that is, over the silicon oxide film LF1. The silicon nitride film LF2 can be formed by a CVD method or the like. As a method for forming the silicon nitride film LF2, the plasma CVD method is particularly suitable. The thickness (formed film thickness) of the silicon nitride film LF2 can be set to, for example, about 0.5 to 3 μm.

  Since the silicon nitride film LF2 is formed on the entire main surface of the semiconductor substrate SB, it is formed on the silicon oxide film LF1 and on the pad PD1 exposed from the opening OP1a of the silicon oxide film LF1. Before the silicon nitride film LF2 is formed, the pad PD1 is exposed from the opening OP1a of the silicon oxide film LF1, but when the silicon nitride film LF2 is formed, the pad PD1 is exposed from the opening OP1a of the silicon oxide film LF1. Since the pad PD1 that has been formed is covered with the silicon nitride film LF2, the pad PD1 is not exposed.

  Next, as shown in FIG. 21, an opening OP1b is formed in the silicon nitride film LF2. The opening OP1b is formed by selectively removing the silicon nitride film LF2 on the pad PD1, and is formed so that the opening OP1b is included in the pad PD1 in plan view. For example, after forming the silicon nitride film LF2, a photoresist pattern (not shown) is formed on the silicon nitride film LF2 using a photolithography technique, and the photoresist pattern is used as an etching mask to form a silicon nitride film. By dry-etching LF2, the opening OP1b can be formed in the silicon nitride film LF2. The opening OP1b is formed so as to penetrate the silicon nitride film LF2, and at least a part of the pad PD1 is exposed from the opening OP1b.

  As can be seen from FIG. 21 and FIGS. 4 and 5, the opening OP1b is formed so as to be included in the opening OP1a in plan view. That is, the planar dimension (planar area) of the opening OP1b of the silicon nitride film LF2 is smaller than the planar dimension (planar area) of the opening OP1a of the silicon oxide film LF1, and the opening OP1b of the silicon nitride film LF2 in plan view. Is enclosed in the opening OP1a of the silicon oxide film LF1. In other words, the planar dimension (planar area) of the opening OP1a of the silicon oxide film LF1 is larger than the planar dimension (planar area) of the opening OP1b of the silicon nitride film LF2, and the opening of the silicon oxide film LF1 in plan view. The part OP1a includes the opening OP1b of the silicon nitride film LF2. That is, in plan view, the opening OP1b of the silicon nitride film LF2 overlaps the opening OP1a of the silicon oxide film LF1, and the outer periphery of the opening OP1b of the silicon nitride film LF2 is the opening OP1a of the silicon oxide film LF1. It is inside the outer periphery.

  Therefore, at the stage of forming the silicon nitride film LF2, the inner wall of the opening OP1a of the silicon oxide film LF1 is covered with the silicon nitride film LF2, and then the opening OP1b is formed in the silicon nitride film LF2. Even so, the inner wall of the opening OP1a of the silicon oxide film LF1 remains covered with the silicon nitride film LF2.

  That is, when the opening OP1b of the silicon nitride film LF2 protrudes from the opening OP1a of the silicon oxide film LF1 in plan view, the opening OP1a of the silicon oxide film LF1 is formed when the opening OP1b is formed in the silicon nitride film LF2. Are exposed without being covered with the silicon nitride film LF2. On the other hand, when the opening OP1b of the silicon nitride film LF2 is included in the opening OP1a of the silicon oxide film LF1 in plan view as in the present embodiment, the opening OP1b is formed in the silicon nitride film LF2. Even if formed, the inner wall of the opening OP1a of the silicon oxide film LF1 is covered with the silicon nitride film LF2. Therefore, in the planar region where the pad PD1 is formed, the silicon oxide film LF1 is not exposed because it is covered with the silicon nitride film LF2, and this state is maintained during and after the opening OP1b is formed. Is done. That is, after the silicon nitride film LF2 is formed, the silicon oxide film LF1 is not exposed.

  The inner wall of the opening OP1b of the silicon nitride film LF2 is preferably tapered. This makes it easier to form the rewiring RW later on the inner wall of the opening OP1b of the silicon nitride film LF2.

  Further, a step portion DS caused by the inner wall of the opening OP1a of the silicon oxide film LF1 is formed on the upper surface of the silicon nitride film LF2. The step portion DS is more preferably covered with the resin film LF3 when the resin film LF3 is formed later and the opening OP1c is formed in the resin film LF3. As a result, when the rewiring RW is formed later, the level difference is reduced in the base, so that the rewiring RW can be easily formed.

  Next, as shown in FIG. 22, a resin film LF3 is formed on the main surface (entire main surface) of the semiconductor substrate SB, that is, on the silicon nitride film LF2. Since the resin film LF3 is formed over the entire main surface of the semiconductor substrate SB, the resin film LF3 is formed over the silicon nitride film LF2 and the pad PD1 exposed from the opening OP1b of the silicon nitride film LF2.

  As the resin film LF3, a polyimide film or the like can be suitably used. The resin film LF3 can be formed by, for example, a coating method. Specifically, a polyimide precursor liquid is applied to the main surface of the semiconductor substrate SB while rotating the semiconductor substrate SB using a so-called spin coating (rotary coating) method, and then dried to form the resin film LF3. The polyimide film can be formed. The thickness (formed film thickness) of the resin film LF3 can be set to, for example, about 1 to 20 μm.

  Since the resin film LF3 is formed over the entire main surface of the semiconductor substrate SB, the resin film LF3 is formed over the silicon nitride film LF2 and the pad PD1 exposed from the opening OP1b of the silicon nitride film LF2. Before the resin film LF3 is formed, the pad PD1 is exposed from the opening OP1b of the silicon nitride film LF2. However, when the resin film LF3 is formed, the pad PD1 is exposed from the opening OP1b of the silicon nitride film LF2. Since the pad PD1 is covered with the resin film LF3, it is not exposed.

  Next, as shown in FIG. 23, an opening OP1c is formed in the resin film LF3. The opening OP1c can be formed, for example, as follows. That is, the resin film LF3 is formed as a photosensitive resin film, and the resin film LF3 made of the photosensitive resin is exposed and developed to selectively remove the portion of the resin film LF3 that becomes the opening OP1c. Thus, the opening OP1c is formed in the resin film LF3. Thereafter, heat treatment is performed to cure the resin film LF3. The opening OP1c is formed so as to penetrate the resin film LF3, and at least a part of the pad PD1 is exposed from the opening OP1c.

  As another form, the opening OP1c is formed in the resin film LF3 by dry etching the resin film LF3 using a photoresist layer formed on the resin film LF3 by photolithography as an etching mask. In this case, the resin film LF3 may not be a photosensitive resin film.

  As can be seen from FIG. 23 and FIGS. 4 and 5, the opening OP1c is formed so as to include the opening OP1b in a plan view. That is, the planar dimension (planar area) of the opening OP1c of the resin film LF3 is larger than the planar dimension (planar area) of the opening OP1b of the silicon nitride film LF2, and the opening OP1c of the resin film LF3 is, in plan view, The opening OP1b of the silicon nitride film LF2 is included. In other words, the planar dimension (planar area) of the opening OP1b of the silicon nitride film LF2 is smaller than the planar dimension (planar area) of the opening OP1c of the resin film LF3, and the opening of the silicon nitride film LF2 in plan view. OP1b is included in the opening OP1c of the resin film LF3. That is, in plan view, the opening OP1c of the resin film LF3 overlaps the opening OP1b of the silicon nitride film LF2, and the outer periphery of the opening OP1c of the resin film LF3 is outside the opening OP1b of the silicon nitride film LF2. is there.

  For this reason, at the stage of forming the resin film LF3, the inner wall of the opening OP1b of the silicon nitride film LF2 is covered with the resin film LF3. However, when the opening OP1c is formed in the resin film LF3 after that, The inner wall of the opening OP1b of the silicon nitride film LF2 is exposed without being covered with the resin film LF3.

  That is, in plan view, when the opening OP1c of the resin film LF3 is included in the opening OP1b of the silicon nitride film LF2, the opening of the silicon nitride film LF2 is formed even if the opening OP1c is formed in the resin film LF3. The inner wall of OP1b remains covered with the resin film LF3. On the other hand, when the opening OP1c of the resin film LF3 encloses the opening OP1b of the silicon nitride film LF2 in plan view as in the present embodiment, the opening OP1c is formed in the resin film LF3. The inner wall of the opening OP1b is exposed in the silicon nitride film LF2 without being covered with the resin film LF3.

  The inner wall of the opening OP1c of the resin film LF3 is preferably tapered. This makes it easier to form the rewiring RW later on the inner wall of the opening OP1c of the resin film LF3.

  In this manner, a laminated film (laminated insulating film) LF having an opening OP1 exposing at least a part of the pad PD1 is formed. The surface of the pad PD1 is exposed from the opening OP1 of the multilayer film LF, but a part of the pad PD1, that is, a portion that does not overlap the opening OP1 in plan view in the pad PD1 is covered with the multilayer film LF. It has become. Specifically, the center portion of the pad PD1 is not covered with the laminated film LF, and the outer peripheral portion of the pad PD1 is covered with the laminated film LF. This state is maintained in subsequent steps.

  The laminated film LF includes a silicon oxide film LF1, a silicon nitride film LF2, and a resin film LF3. The laminated film LF has an opening OP1 that exposes at least a part of the pad PD1, and the opening OP1 has an opening OP1c of the resin film LF3, an opening OP1b of the silicon nitride film LF2, and an oxide. It is formed by the opening OP1a of the silicon film LF1.

  However, since the inner wall of the opening OP1a of the silicon oxide film LF1 is covered with the silicon nitride film LF2, the inner wall of the opening OP1 of the stacked film LF is the inner wall of the opening OP1c of the resin film LF3 and the silicon nitride film LF2. And the upper surface of the silicon nitride film LF2 located between the inner wall of the opening OP1c and the inner wall of the opening OP1b and not covered with the resin film LF3.

  As described above, the wafer process is performed on the semiconductor substrate SB as shown in FIGS. The wafer process is also called a pre-process. Here, the wafer process generally includes various elements (here, MISFETs), wiring layers (here, wirings M1, M2, M3) and pad electrodes (here) on the main surface of the semiconductor wafer (semiconductor substrate SB). Then, after forming the pad PD1) and forming the surface protective film (here, the laminated film LF), the process until the electrical test of each of the plurality of chip regions formed on the semiconductor wafer can be performed with a probe or the like. Say. Each chip area of the semiconductor wafer corresponds to an area from which one semiconductor chip is obtained.

  For this reason, the laminated film LF is the uppermost layer and a surface protective film in the semiconductor wafer subjected to the wafer process. Further, the wiring M3 of the third wiring layer is the uppermost wiring, and the pad PD1 is formed by this third wiring layer.

  An electrical test of each chip region of the semiconductor wafer (semiconductor substrate SB) can be performed by performing a probe test (wafer test) using the pad PD1 exposed from the opening OP1 of the laminated film LF. Specifically, in each chip region of the semiconductor wafer (semiconductor substrate SB), a test probe (probe needle, probe) is applied to the pad PD1 exposed from the opening OP1 of the stacked film LF. Conduct electrical tests. Based on the result of the probe test, whether each chip area of the semiconductor wafer (semiconductor substrate SB) is a non-defective product or a defective product is selected, or data of the measurement result of the probe test is fed back to each manufacturing process. Therefore, it can be used to improve yield and reliability. For this reason, the probe test can be omitted, but it is more preferable to perform it.

  After the structure of FIG. 23 is obtained by the wafer process (pretreatment) process as described above, a probe test is performed as necessary, and then, as shown in FIG. 24, the main surface of the semiconductor substrate SB ( A seed film (seed layer) SE is formed on the entire main surface), that is, on the laminated film LF including the pad PD1 exposed from the opening OP1 of the laminated film LF. The seed film SE is a film that functions later as a seed layer (feeding layer) for electrolytic plating.

  The seed film SE includes, for example, a laminated film of a chromium (Cr) film and a copper (Cu) film on the chromium (Cr) film, and can be formed by, for example, a sputtering method. Thus, the seed film SE is formed on the stacked film LF including the pad PD1 exposed at the bottom of the opening OP1 and the inner wall of the opening OP1. Except for the opening OP1, since the surface of the laminated film LF is the resin film LF3, the seed film SE is formed on the resin film LF3 so as to be in contact with the resin film LF3.

  The film thickness of the seed film SE can be, for example, about 75 nm for a chromium (Cr) film and about 250 nm for a copper (Cu) film. In addition, the lower chromium (Cr) film of the seed film SE can function as a barrier conductor film, and has, for example, a copper diffusion prevention function and a function of improving adhesion to the resin film LF3. However, it is not limited to the chromium (Cr) film, and for example, a titanium (Ti) film, a titanium tungsten (TiW) film, a titanium nitride (TiN) film, or a tungsten (W) film can be used. .

  Next, after a resist film (photoresist film) is formed on the seed film SE, this resist film is patterned by using a photolithography method (specifically, exposure and development are performed). As shown in FIG. 2, a resist pattern (photoresist pattern) PR1 made of a patterned resist film is formed on the seed film SE.

  The resist pattern PR1 is formed in a region other than the region where the rewiring RW, the pad PD2, the coil CL2, and the pad PD3 are to be formed, and the region where the rewiring RW is to be formed, and the region where the pad PD2 is to be formed. The seed film SE is exposed in the region where the coil CL2 is to be formed and the region where the pad PD3 is to be formed. That is, the resist pattern PR1 has openings in the region where the rewiring RW is to be formed, the region where the pad PD2 is to be formed, the region where the coil CL2 is to be formed, and the region where the pad PD3 is to be formed. (Groove).

  Next, as shown in FIG. 26, a copper (Cu) film CF is formed by electrolytic plating on the seed film SE exposed from the opening (groove) of the resist pattern PR1. Thereby, the copper film CF is selectively formed on the seed film SE in the region not covered with the resist pattern PR1. The film thickness of the copper film CF can be about 4 to 10 μm, for example. The copper film CF is formed in a region where the rewiring RW is to be formed, a region where the pad PD2 is to be formed, a region where the coil CL2 is to be formed, and a region where the pad PD3 is to be formed.

  Next, after forming another resist film (photoresist film) on the resist pattern PR1 including the copper film CF, this resist film is used by photolithography (specifically, exposure and development). As shown in FIG. 27, a resist pattern (photoresist pattern) PR2 made of a patterned resist film is formed.

  The resist pattern PR2 is formed in a region other than the region where the base metal film UM is to be formed in the pad PD2, and the copper film CF is exposed in a region where the base metal film UM is to be formed. That is, the resist pattern PR2 has an opening in a region where the base metal film UM is to be formed.

  Next, as shown in FIG. 27, a base metal film UM is formed on the copper film CF exposed from the opening of the resist pattern PR2 by electrolytic plating. Thereby, the base metal film UM is formed on the copper film CF in a region not covered with the resist pattern PR2. The base metal film UM is formed on a portion of the copper film CF to be the pad PD2 and a portion of the copper film CF to be the pad PD3. The base metal film UM is made of, for example, a laminated film of a nickel (Ni) film and a gold (Au) film on the nickel (Ni) film. At this time, the film thickness of the nickel (Ni) film can be about 1.5 μm, for example, and the film thickness of the gold (Au) film can be about 2 μm, for example.

  Next, as shown in FIG. 28, the resist pattern PR2 and the resist pattern PR1 are removed. As a result, the copper film CF is exposed, and the seed film SE in a region where the copper film CF is not formed (that is, the portion of the seed film SE not covered with the copper film CF) is also exposed.

  In the present embodiment, after forming the copper film CF, the resist pattern PR2 is formed without removing the resist pattern PR1, and then the base metal film UM is formed, and then the resist patterns PR2 and PR1 are removed. Explained when to do. As another form, after forming the copper film CF, the resist pattern PR2 is formed after removing the resist pattern PR1, and then the resist pattern PR2 can be removed after forming the base metal film UM.

  Next, as shown in FIG. 29, a portion of the seed film SE not covered with the copper film CF is removed by etching. At this time, a portion of the seed film SE not covered with the copper film CF, that is, the seed film SE located under the copper film CF remains without being removed. In this case, the portion of the seed film SE not covered with the copper film CF is removed, but the copper film CF and the base metal film UM are preferably etched so as not to be excessively etched.

  In this manner, the rewiring RW, the pad PD2, the coil CL2, and the pad PD3 made of the seed film SE and the copper film CF are formed. That is, the rewiring RW, the pad PD2, the coil CL2, and the pad PD3 are each composed of a laminated film of the seed film SE and the copper film CF on the seed film SE.

  The rewiring RW, the pad PD2, the coil CL2, and the pad PD3 are formed on the resin film LF3 of the laminated film LF. However, the rewiring RW is formed on the stacked film LF including the pad PD1 exposed from the opening OP1, and is electrically connected to the pad PD1. The rewiring RW is also connected to the pad PD2, and specifically, the pad PD2 is formed integrally with the rewiring RW. For this reason, the pad PD1 and the pad PD2 are electrically connected via the rewiring RW. The coil CL2 is connected to the pad PD3. Specifically, the pad PD3 is formed integrally with the coil CL2.

  A base metal film UM is formed on the copper film CF constituting the pad PD2 and on the copper film CF constituting the pad PD3. The underlying metal film UM on the pad PD2 can also be regarded as a part of the pad PD2, and the underlying metal film UM on the pad PD3 can also be regarded as a part of the pad PD3.

  In the present embodiment, the case where copper (Cu) is used as the main material of the rewiring RW (that is, the case where the copper film CF is used as the main conductor film of the rewiring RW) has been described. As another form, gold (Au) can also be used as the main material of the rewiring RW (that is, a gold film can be used instead of the copper film CF as the main conductor film of the rewiring RW). Since the pad PD2, the coil CL2, and the pad PD3 are formed of a conductive film in the same layer as the rewiring RW, when copper (Cu) is used as the main material of the rewiring RW, the pad PD2, the coil CL2, and the pad PD3 are used. The main material is copper (Cu), and when gold (Au) is used as the main material of the rewiring RW, the main material of the pad PD2, the coil CL2, and the pad PD3 is also gold (Au). When gold (Au) is used as the main material of the rewiring RW, since the gold (Au) is excellent in corrosion resistance, the corrosion resistance can be improved. On the other hand, when copper (Cu) is used as the main material of the rewiring RW as in the present embodiment, the copper (Cu) has low resistance and is inexpensive, so that the performance is improved and the manufacturing cost is reduced. be able to.

  Next, as shown in FIG. 30, insulation is performed on the main surface (entire main surface) of the semiconductor substrate SB, that is, on the stacked film LF so as to cover the rewiring RW, the pad PD2, the coil CL2, and the pad PD3. Protective film (surface protective film, insulating film, protective insulating film) PA is formed. As the protective film PA, a resin film is preferable, and for example, a polyimide film can be suitably used.

  The protective film PA can be formed by, for example, a coating method. Specifically, a polyimide precursor solution is applied to the main surface of the semiconductor substrate SB while rotating the semiconductor substrate SB using a so-called spin coating (rotary coating) method, and then dried to form the protective film PA. The polyimide film can be formed.

  Next, as shown in FIG. 31, openings OP2 and OP3 are formed in the protective film PA. The openings OP2 and OP3 can be formed as follows, for example. That is, the protective film PA is formed as a photosensitive resin film, and the protective film PA made of the photosensitive resin is exposed and developed to selectively remove the protective film PA in the portions to be the openings OP2 and OP3. Thus, the opening OP2 and the opening OP3 are formed in the protective film PA. Thereafter, heat treatment is performed to cure the protective film PA. The opening OP2 and the opening OP3 are formed so as to penetrate the protective film PA, and at least a part of the pad PD2 is exposed from the opening OP2, and at least a part of the pad PD3 is exposed from the opening OP3. When the base metal film UM is formed on the pads PD2 and PD3, the base metal film UM on the pad PD2 is exposed from the opening OP2, and the base metal film UM on the pad PD3 is exposed from the opening OP3.

  When wire bonding is performed on the pads PD2 and PD3 when manufacturing the semiconductor package, bonding wires BW described later are connected to the underlying metal film UM exposed from the openings OP2 and OP3, respectively. By providing the base metal film UM, it is possible to easily and accurately connect a conductive connecting member such as a bonding wire (BW) to the pads PD2 and PD3.

  As another form, the opening OP2 is formed in the protective film PA by dry etching the protective film PA using a photoresist layer formed on the protective film PA by using a photolithography technique as an etching mask. In this case, the protective film PA may not be a photosensitive resin film.

  The pads PD2 and PD3 (or the underlying metal film UM on the pads PD2 and PD3) are exposed from the openings OP2 and OP3 of the protective film PA, but the rewiring RW and the coil CL2 are covered and protected by the protective film PA. The By using a resin film (organic insulating film) such as polyimide resin as the uppermost protective film PA, the semiconductor film can be easily handled with a relatively soft resin film (organic insulating film) as the uppermost layer. Can do.

  Thereafter, the semiconductor substrate SB is cut (diced) and divided into a plurality of semiconductor chips (divided into individual pieces). Thereby, a semiconductor chip is acquired from each chip region of the semiconductor substrate SB (semiconductor wafer). Note that before the dicing, the semiconductor substrate SB may be ground to make the semiconductor substrate SB thin.

<Main features and effects of semiconductor devices (semiconductor chips)>
In the present embodiment, the semiconductor device (semiconductor chip) includes a coil CL1 formed on a semiconductor substrate SB via a first insulating film (here, interlayer insulating films IL1, IL2), and a first on the semiconductor substrate SB. A second insulating film (interlayer insulating film IL3 here) formed so as to cover the insulating film and coil CL1, and a pad formed on the second insulating film and disposed so as not to overlap with coil CL1 in plan view PD1. Furthermore, a laminated film LF formed on the second insulating film, which has an opening OP1 exposing the pad PD1, and a coil formed on the laminated film LF and disposed above the coil CL1 CL2 and a rewiring RW (first wiring) formed on the laminated film LF including the pad PD1 exposed from the opening OP1 and electrically connected to the pad PD1. The coil CL1 and the coil CL2 are magnetically coupled without being connected by a conductor.

  One of the main features of the present embodiment is that the laminated film LF includes a silicon oxide film LF1, a silicon nitride film LF2 over the silicon oxide film LF1, and a resin film LF3 over the silicon nitride film LF2. The silicon oxide film LF1, the silicon nitride film LF2, and the resin film LF3 are also interposed between the coil CL1 and the coil CL2.

  The laminated film LF is an insulating film formed after the formation of the pad PD1 and before the formation of the rewiring RW and the coil CL2. Therefore, a part of the pad PD1 is covered with the laminated film LF, and the coil CL2 and the rewiring RW are formed on the laminated film LF. Therefore, when the test process (probe test) is performed using the pad PD1, the laminated film LF can function as the uppermost film (surface protective film). A part of the pad PD1 is covered with the laminated film LF because the part of the pad PD1 that does not overlap with the opening OP1 in plan view is covered with the laminated film LF. The central portion of the pad PD1 is not covered with the laminated film LF, and the outer peripheral portion of the pad PD1 is covered with the laminated film LF.

  In the present embodiment, it is important that the laminated film LF is a laminated film in which the silicon oxide film LF1, the silicon nitride film LF2, and the resin film LF3 are laminated in this order. Since the laminated film LF is interposed between the coil CL1 and the coil CL2, the silicon oxide film LF1, the silicon nitride film LF2, and the resin film LF3 are interposed between the coil CL1 and the coil CL2.

  When the dielectric breakdown voltage is compared between a silicon oxide film, a silicon nitride film, and a resin film (for example, a polyimide film), the silicon oxide film has the highest dielectric breakdown voltage, and then the resin film (for example, a polyimide film) has the highest dielectric breakdown voltage. It's easy to do. That is, when a silicon oxide film, a silicon nitride film, and a resin film (for example, a polyimide film) are compared with each other in terms of withstand voltage per unit thickness, the silicon oxide film is the highest, followed by the resin film (for example, a polyimide film). Since a large potential difference may occur between the coil CL1 and the coil CL2, the reliability of the semiconductor chip having the coils CL1 and CL2, the reliability of the semiconductor package including the semiconductor chip, or the semiconductor package In order to improve the reliability of the used electronic device, it is desirable that the dielectric strength between the coil CL1 and the coil CL2 be as high as possible. For this reason, when the laminated film LF interposed between the coil CL1 and the coil CL2 includes the silicon oxide film LF1, the withstand voltage between the coil CL1 and the coil CL2 can be improved. That is, by interposing the silicon oxide film LF1 having a relatively high withstand voltage per unit thickness between the coil CL1 and the coil CL2, the withstand voltage between the coil CL1 and the coil CL2 can be improved.

  However, since the silicon oxide film is hygroscopic, the silicon oxide film does not want to be the uppermost film (surface film). The surface of the laminated film LF becomes the outermost surface when a test process (probe test) is performed using the pad PD1. If the silicon oxide film absorbs moisture, the reliability of the semiconductor device may be reduced. Further, when a resin film (for example, a polyimide film) is directly formed on the silicon oxide film, moisture in the resin film (for example, a polyimide film) may diffuse into the silicon oxide film and the silicon oxide film may absorb moisture.

  Therefore, in this embodiment, the silicon oxide film LF1 is not the uppermost layer of the laminated film LF, and the resin film is not formed directly on the silicon oxide film LF1. That is, in this embodiment, the silicon nitride film LF2 is formed on the silicon oxide film LF1 so as to be in contact with the silicon oxide film LF1. By forming the silicon nitride film LF2 over the silicon oxide film LF1, moisture absorption of the silicon oxide film can be suppressed or prevented.

  In order to increase the withstand voltage between the coils CL1 and CL2, with respect to the insulating film interposed between the coils CL1 and CL2, the viewpoint of increasing the withstand voltage per unit thickness and the thickness of the insulating film are increased. There is a viewpoint to do. Since the silicon oxide film LF1 has a high withstand voltage per unit thickness, it is desired to make it as thick as possible from the viewpoint of improving the withstand voltage. However, it is not easy to increase the thickness in film formation. Further, if the silicon oxide film LF1 is too thick, there is a concern that the semiconductor substrate SB (semiconductor wafer) is likely to warp during manufacture. In addition, since the silicon nitride film does not have a high withstand voltage per unit thickness, it is disadvantageous to improve the withstand voltage with the silicon nitride film from the viewpoint of improving the withstand voltage. For this reason, in this embodiment, the laminated film LF also includes the resin film LF3, so that the withstand voltage between the coil CL1 and the coil CL2 is increased. That is, if an attempt is made to obtain a dielectric breakdown voltage using only the silicon oxide film LF1, there are concerns about manufacturing difficulty in forming a thick silicon oxide film and warping of the semiconductor substrate SB (semiconductor wafer). Such a concern can be solved by increasing the pressure resistance. However, since there is a concern about moisture absorption of the silicon oxide film, the silicon nitride film LF2 is interposed between the silicon oxide film LF1 and the resin film LF3 instead of directly forming the resin film LF3 on the silicon oxide film LF1. Thus, the silicon oxide film LF1 can be prevented from absorbing moisture.

  Thus, in the present embodiment, the withstand voltage is improved because the laminated film LF includes the silicon oxide film LF1. Further, since the laminated film LF also includes the resin film LF3, the withstand voltage is further improved, the manufacturing difficulty is eliminated, and the problem that the semiconductor substrate SB (semiconductor wafer) is warped during the manufacturing does not occur. I have to. Further, by interposing the silicon nitride film LF2 between the silicon oxide film LF1 and the resin film LF3, a problem that the silicon oxide film LF1 absorbs moisture does not occur. For this reason, it is important that the laminated film LF is a laminated film in which the silicon oxide film LF1, the silicon nitride film LF2, and the resin film LF3 are laminated in this order. Thereby, the reliability of the semiconductor device (semiconductor chip) having the coils CL1 and CL2 can be improved. In addition, the reliability of a semiconductor package (semiconductor device) including a semiconductor chip having the coils CL1 and CL2 or the reliability of an electronic device using the semiconductor package can be improved.

  Further, the fact that the uppermost layer of the laminated film LF is the resin film LF3 has an advantage that when the test process (probe test) is performed using the pad PD1, the test process is easily performed and handling is facilitated. . That is, in the test process (probe test), the outermost surface is the resin film LF3, but the softer outermost surface is easier to handle. From this viewpoint, a polyimide film is suitable as the resin film LF3, and the polyimide film is soft (flexible). Therefore, in the test process (probe test), the outermost surface is a polyimide film. Easy to handle and easy to handle.

  Further, when the silicon oxide film and the polyimide film are formed on a semiconductor substrate (semiconductor wafer), the directions of stress are opposite, and therefore, the warp directions of the semiconductor substrate (semiconductor wafer) are opposite. For this reason, when a polyimide film is used as the resin film LF3, warping of the semiconductor substrate SB (semiconductor wafer) due to the stress of the silicon oxide film LF1 can be offset by the stress of the polyimide film. In addition, it is possible to suppress or prevent the semiconductor substrate SB (semiconductor wafer) from warping.

  Further, the silicon nitride film LF2 serves to prevent the silicon oxide film LF1 from absorbing moisture. For this reason, the thickness of the silicon nitride film LF2 is more preferably 0.5 μm or more. Thereby, the silicon oxide film LF1 can be accurately prevented from absorbing moisture.

  In addition, since the silicon nitride film LF2 has a lower withstand voltage per unit thickness than the silicon oxide film LF1, it is better to increase the withstand voltage in the silicon oxide film LF1 than in the silicon nitride film LF2 in terms of improving the withstand voltage. It is advantageous. Further, when the silicon nitride film and the silicon oxide film are compared, it is the silicon nitride film that is likely to warp the semiconductor substrate (semiconductor wafer) when formed on the semiconductor substrate (semiconductor wafer). For this reason, if the silicon nitride film LF2 is too thick, there is a concern that the semiconductor substrate SB (semiconductor wafer) may be warped.

  For this reason, it is more preferable that the thickness of the silicon oxide film LF1 is thicker (larger) than the thickness of the silicon nitride film LF2. That is, the thickness of the silicon nitride film LF2 is more preferably smaller (smaller) than the thickness of the silicon oxide film LF1. Thereby, the withstand voltage between the coil CL1 and the coil CL2 can be improved, and the warpage of the semiconductor substrate SB (semiconductor wafer) can be suppressed or prevented. In this respect, the silicon nitride film LF2 is more preferably 3 μm or less. Here, the thickness of the silicon oxide film LF1 and the thickness of the silicon nitride film LF2 correspond to the thickness of the silicon oxide film LF1 and the thickness of the silicon nitride film LF2 between the coils CL1 and CL2.

  FIG. 35 shows a thickness T1 that is the thickness of the silicon oxide film LF1, a thickness T2 that is the thickness of the silicon nitride film LF2, and a thickness T3 that is the thickness of the resin film LF3. As described above, the thickness T1 of the silicon oxide film LF1 is preferably thicker (larger) than the thickness T2 of the silicon nitride film LF2 (that is, T1> T2).

  The laminated film LF has an opening OP1 that exposes the pad PD1, and the central portion of the pad PD1 is not covered with the laminated film LF, but the outer peripheral portion of the pad PD1 is covered with the laminated film LF. Yes. The opening OP1 of the laminated film LF is formed by the opening OP1a of the silicon oxide film LF1, the opening OP1b of the silicon nitride film LF2, and the opening OP1c of the resin film LF3.

  In the present embodiment, as shown in FIGS. 4 and 5, the opening OP1b of the silicon nitride film LF2 is included in the opening OP1a of the silicon oxide film LF1 in plan view, and the opening of the silicon oxide film LF1. It is more preferable that the inner wall of OP1a is covered with the silicon nitride film LF2. As a result, the surface of the silicon oxide film LF1 is also covered with the silicon nitride film LF2 even on the inner wall of the opening OP1a of the silicon oxide film LF1, so that the silicon oxide film LF1 is more accurately prevented from absorbing moisture. be able to. That is, unlike the embodiment, when the inner wall of the opening OP1a of the silicon oxide film LF1 is not covered with the silicon nitride film LF2, the silicon oxide film LF1 may absorb moisture from the inner wall of the opening OP1a of the silicon oxide film LF1. There is. On the other hand, if the inner wall of the opening OP1a of the silicon oxide film LF1 is covered with the silicon nitride film LF2, it is possible to prevent the silicon oxide film LF1 from absorbing moisture from the inner wall of the opening OP1a of the silicon oxide film LF1. Moisture absorption of the silicon oxide film LF1 can be prevented more accurately.

  In the present embodiment, as shown in FIGS. 4 and 5, the opening OP1b of the silicon nitride film LF2 is included in the opening OP1c of the resin film LF3 in plan view, and the opening of the silicon nitride film LF2 is formed. More preferably, the inner wall of the portion OP1b is not covered with the resin film LF3. By doing so, the exposed area of the pad PD1 (the area of the part exposed from the opening OP1 of the stacked film LF in the pad PD1) is defined by the opening OP1b of the silicon nitride film LF2. Thereby, the fluctuation | variation of the exposed area of pad PD1 can be suppressed. That is, a resin film (for example, a polyimide film) has a larger amount of shrinkage after film formation than a silicon nitride film, so that the opening OP1c of the resin film LF3 has a planar dimension compared to the opening OP1b of the silicon nitride film LF2. (Flat area) is likely to fluctuate. However, if the inner wall of the opening OP1b of the silicon nitride film LF2 is not covered with the resin film LF3, the exposed area of the pad PD1 is defined by the opening OP1b of the silicon nitride film LF2. Even if the amount of contraction of fluctuates, it does not affect the exposed area of the pad PD1. For this reason, fluctuations in the exposed area of the pad PD1 can be suppressed. Therefore, the test process (probe test) using the pad PD1 can be performed more easily and accurately.

  In the present embodiment, it is more preferable that the step portion DS on the upper surface of the silicon nitride film LF2 formed due to the inner wall of the opening OP1a of the silicon oxide film LF1 is covered with the resin film LF3. . As a result, the level difference is reduced in the base on which the rewiring RW is formed, so that the rewiring RW can be easily formed and the rewiring RW can be formed more accurately. For this reason, the rewiring RW can be formed more accurately by using a plating method. In addition, since the plating film is difficult to be disconnected, the reliability of the rewiring RW can be improved.

  In the present embodiment, it is preferable that the inner wall of the opening OP1b of the silicon nitride film LF2 has a taper and the inner wall of the opening OP1c of the resin film LF3 has a taper. Thereby, it becomes easy to form the rewiring RW extending from the pad PD1 onto the laminated film, and the rewiring RW can be formed more accurately. For example, when a seed layer (for power supply) (corresponding to the seed film SE) for forming the rewiring RW by electrolytic plating is formed by a sputtering method or the like, the seed layer can be accurately formed. Layer formation defects can be prevented. For this reason, the disconnection failure of the seed layer can be prevented, and the plating layer for the rewiring RW can be accurately formed.

  Here, if the inner wall of the opening OP1b of the silicon nitride film LF2 has a taper, the inner wall of the opening OP1b is inclined from the direction perpendicular to the main surface of the semiconductor substrate SB, and the opening OP1b is formed from the bottom side. In the upper side, the dimension (planar dimension) becomes larger. If the inner wall of the opening OP1c of the resin film LF3 has a taper, the inner wall of the opening OP1c is inclined from the direction perpendicular to the main surface of the semiconductor substrate SB, and the opening OP1c is higher than the bottom side. The side is larger in dimension (planar dimension).

The silicon oxide film LF1 is preferably formed by HDP (High Density Plasma) -CVD. Since the silicon oxide film LF1 is the lowermost film in the stacked film LF, the silicon oxide film LF1 is formed to be in contact with the wiring (here, the wiring M3) in the same layer as the pad PD1 and to cover the wiring (here, the wiring M3). become. The silicon oxide film LF1 is preferably thick in order to increase the withstand voltage, but even when the thickness is increased, the space between adjacent wirings in the same layer as the pad PD1 (here, the wiring M3) can be embedded. As described above, it is preferable to apply a film forming method with good embeddability. A silicon oxide film formed by the HDP-CVD method has good embeddability. For this reason, if the silicon oxide film LF1 is formed by the HDP-CVD method, the thickness of the silicon oxide film LF1 is increased while preventing a filling failure between the wirings in the same layer as the pad PD1 (here, the wiring M3). can do. For this reason, the reliability of the semiconductor device can be further improved. Note that a silicon oxide film formed by the HDP-CVD method is referred to as an HDP-CVD oxide film. In the case where the silicon oxide film LF1 is formed by the HDP-CVD method, the plasma density during the film formation is preferably about 1 × 10 ¹¹ to 1 × 10 ¹² / cm ³ . In normal plasma CVD instead of high-density plasma CVD, the plasma density is generally about 1 × 10 ⁹ to 1 × 10 ¹⁰ / cm ³ .

  Further, as described above, by devising the laminated structure of the insulating film between the coil CL2 and the coil CL1 disposed above and below, the dielectric breakdown voltage of the coil CL2 and the coil CL1 is improved, and so on. Improves reliability. The coil CL2 and the rewiring RW are formed in the same layer. However, in a plan view, the shortest distance between the coil CL2 and the rewiring RW is the distance between the coil CL2 and the coil CL1 (the vertical distance). ) Is preferably larger. Thereby, the withstand voltage between the coil CL2 and the rewiring RW can be secured. The shortest distance between the coil CL2 and the rewiring RW in a plan view can be set to 100 μm or more, for example.

  The resin film LF3 is most preferably a polyimide film. The polyimide film has high solvent resistance, heat resistance and mechanical strength. As the resin film LF3, in addition to the polyimide film, other organic insulating films such as epoxy-based, PBO-based, acrylic-based, and WRP-based resins can also be used.

<About the coil configuration>
Next, the configuration of the coil that constitutes the transformer TR1 formed in the semiconductor chip CP1 will be described.

  FIG. 32 is a circuit diagram showing a circuit configuration of the transformer TR1 formed in the semiconductor chip CP1. FIG. 33 and FIG. 34 are main part plan views of the semiconductor chip CP1 of the present embodiment, showing a plan view of a coil formed in the transformer forming region 1B. FIG. 35 and FIG. 36 are main part cross-sectional views of the semiconductor chip CP1 of the present embodiment, and a cross-sectional view of the transformer forming region 1B is shown.

  33 and 34 show the same planar region in the semiconductor chip CP1, but the layers are different, and FIG. 34 shows a lower layer than FIG. Specifically, FIG. 33 shows secondary coils (coils CL5 and CL6) of the transformer TR1 formed on the semiconductor chip CP1, and FIG. 34 shows the transformer TR1 formed on the semiconductor chip CP1. Primary coils (coils CL7, CL8) are shown. In addition, in FIG. 34, the lead wires HW1 and HW2 are indicated by dotted lines so that the relative positional relationship between the primary coils (CL7 and CL8) and the lead wires (lead wires HW1 and HW2) can be easily understood. is there. 33 and FIG. 34 corresponds to FIG. 35, and the sectional view taken along line A2-A2 of FIG. 33 and FIG. 34 corresponds to FIG.

  As described above, the primary coil and the secondary coil for the transformer TR1 are formed in the semiconductor chip CP1, and among the primary coil and the secondary coil, the primary coil is formed on the lower side and the secondary coil is formed on the upper side. Yes. That is, the secondary coil is disposed above the primary coil, and the primary coil is disposed below the secondary coil.

  Here, when each of the primary coil and the secondary coil is configured by two coils, that is, when the transformer TR1 is configured by two transformers and these two transformers are operated in a differential manner, noise resistance increases.

  Therefore, in the present embodiment, as shown in FIG. 32, the primary coil of the transformer TR1 (corresponding to the coil CL1a) is formed by the coil CL7 and the coil CL8 connected in series, and the transformer TR1 A configuration is adopted in which a secondary coil (corresponding to the coil CL2a) is formed by a coil CL5 and a coil CL6 connected in series between the pad PD5 and the pad PD6. In this case, the coil CL7 and the coil CL5 are magnetically coupled (inductive coupling), and the coil CL8 and the coil CL6 are magnetically coupled (inductive coupling). The coils CL7 and CL8 connected in series are connected to the transmission circuit TX1. A pad PD7 is electrically connected between the coil CL5 and the coil CL6. The coils CL5, CL6, CL7, CL8, the pads PD5, PD6, PD7, and the transmission circuit TX1 are formed in the semiconductor chip CP1. The pads PD5, PD6, and PD7 of the semiconductor chip CP1 are connected to the receiving circuit RX1 in the semiconductor chip CP2 through a conductive connecting member such as a bonding wire BW described later and the internal wiring of the semiconductor chip CP2.

  For this reason, in the semiconductor chip CP1, when a transmission signal is sent from the transmission circuit TX1 to the coils CL7 and CL8, which are primary coils, and a current flows, the secondary current is changed according to changes in the current flowing through the coils CL7 and CL8. An induced electromotive force is generated in the coils CL5 and CL6, which are coils, and an induced current flows. The induced electromotive force or induced current generated in the coils CL5 and CL6 is generated in the semiconductor chip CP2 from the pads PD5, PD6, and PD7 through a conductive connecting member such as a bonding wire BW described later and the internal wiring of the semiconductor chip CP2. Can be detected by the receiving circuit RX1. Thereby, the signal from the transmission circuit TX1 of the semiconductor chip CP1 can be transmitted to the reception circuit RX1 of the semiconductor chip CP2 via the coils CL7, CL8, CL5, and CL6 by electromagnetic induction. Since a fixed potential (a ground potential, a GND potential, a power supply potential, etc.) is supplied to the pad PD7 from the semiconductor chip CP2, the induced electromotive force or induced current of the coil CL5 and the induced electromotive force or induced current of the coil CL6 are It can be detected and differentially controlled (operated).

  Hereinafter, specific configurations of the coils CL5, CL6, CL7, and CL8 and the pads PD5, PD6, and PD7 will be described with reference to FIGS.

  The coil CL7 and the coil CL8 correspond to the coil CL1, the coil CL5 and the coil CL6 correspond to the coil CL2, and the pads PD5, PD6, and PD7 correspond to the pad PD3. Is. That is, when the transformer of FIGS. 33 to 36 is applied to the structure of FIG. 3 and the manufacturing process of FIGS. 7 to 31, the coil CL1 in FIG. 3 and FIGS. The coils CL7 and CL8 in FIG. 36 are replaced, the coil CL2 is replaced with the coils CL5 and CL6 in FIGS. 33 to 36, and the pad PD3 is replaced with the pads PD5, PD6 and PD7 in FIGS.

  First, specific configurations of the coils CL5 and CL6, which are secondary coils, and pads (pad electrodes, bonding pads) PD5, PD6, and PD7 connected thereto will be described.

  As shown in FIGS. 32 to 36, two coils (inductors) CL5 and CL6 are connected in series between the pad PD5 and the pad PD6. And pad PD7 is electrically connected between coil CL5 and coil CL6.

  The coil CL5 and the coil CL6 are formed in the same layer in the semiconductor chip CP1, the coil CL5 is formed by a coil wiring CW5 that circulates in a spiral shape (coil shape, loop shape), and the coil CL6 is a spiral shape. It is formed by coil wiring CW6 which circulates in a shape (coil shape, loop shape). Moreover, the coil CL5 and the coil CL6 are each formed in a plane. Coil CL5 and coil CL6 can each be regarded as an inductor. Since the coils CL5 and CL6 correspond to the coil CL1, the coils CL1 and CL6 are formed on the layer where the coil CL1 is formed according to the method of forming the coil CL1 described above. Further, since the pads PD5, PD6, and PD7 correspond to the pad PD3, the pads PD5, PD6, and PD7 are formed on the layer in which the pad PD3 is formed according to the method for forming the pad PD3 described above.

  Also, as shown in FIGS. 32 to 36, two coils (inductors) CL7 and CL8 are connected in series. The coil CL7 and the coil CL8 are formed in the same layer in the semiconductor chip CP1, the coil CL7 is formed by a coil wiring CW7 that circulates in a spiral shape (coil shape, loop shape), and the coil CL8 is a spiral shape. It is formed by coil wiring CW8 which circulates in a shape (coil shape, loop shape). Further, the coil CL7 and the coil CL8 are each formed in a planar manner. Coil CL7 and coil CL8 can each be regarded as an inductor. Since the coils CL7 and CL8 correspond to the coil CL2, the coils CL2 and CL8 are formed on the layer where the coil CL2 is formed according to the method for forming the coil CL2.

  As can be seen from FIGS. 35 and 36, in the semiconductor chip CP1, the coils CL7 and CL8 are formed below the coils CL5 and CL6. That is, in the semiconductor chip CP1, the coil CL5 and the coil CL6 are formed in the same layer, and the coil CL7 and the coil CL8 are formed in the same layer, but the coils CL7 and CL8 are formed of the coils CL5 and CL5. Arranged in a lower layer than CL6, the coils CL5 and CL6 are arranged in an upper layer than the coils CL7 and CL8.

  The coil CL7 is disposed immediately below the coil CL5, and the coil CL8 is disposed directly below the coil CL6. That is, the coil CL7 is disposed so as to overlap with the coil CL5 in a plan view, and the coil CL8 is disposed so as to overlap with the coil CL6 in a plan view. In other words, the coil CL5 is disposed immediately above the coil CL7, and the coil CL6 is disposed immediately above the coil CL8. That is, the coil CL5 is disposed so as to overlap with the coil CL7 in a plan view, and the coil CL6 is disposed so as to overlap with the coil CL8 in a plan view.

  Coil CL5 and coil CL7 are magnetically coupled, and coil CL6 and coil CL8 are magnetically coupled. That is, the coil CL5 and the coil CL7 are not connected by a conductor but are magnetically coupled, and the coil CL6 and the coil CL8 are not connected by a conductor but are magnetically coupled. On the other hand, the coil CL5 and the coil CL6 are connected by a conductor, and the coil CL7 and the coil CL8 are connected by a conductor.

  Since the pads PD5, PD6, and PD7 correspond to the pad PD3, and the coils CL5 and CL6 (coil wirings CW5 and CW6) correspond to the coil CL2, the pads PD5, PD6, and PD7 and the coils CL5 and CL6 (coil wirings CW5 and CW6) are formed in the same layer, and the rewiring RW and the pad PD2 are also formed in the same layer. Specifically, the coils CL5 and CL6 (coil wirings CW5 and CW6) and the pads PD5, PD6 and PD7 are all formed of a laminated film of the seed film SE and the copper film CF on the seed film SE, and the resin film The underlying metal film UM is formed on the surfaces of the pads PD5, PD6, and PD7, which are formed on the LF3. The coils CL5 and CL6 (coil wirings CW5 and CW6) are covered with the uppermost protective film PA of the semiconductor chip CP1, but the pads PD5, PD6 and PD7 are opened from the opening OP3 provided in the protective film PA. Exposed. In FIG. 33, the opening OP3 is indicated by a dotted line.

  As shown in FIGS. 33 and 35, the pad PD5 is arranged inside the spiral of the coil CL5, and one end of the coil CL5 is connected to the pad PD5. That is, the coil wiring CW5 connected to the pad PD5 circulates around the pad PD5 a plurality of times, thereby forming the coil CL5. In the case of FIG. 33, the coil wiring CW5 connected to the pad PD5 circulates clockwise around the pad PD5 to form the coil CL5. Since the coil wirings CW5 do not intersect with each other, the coil wiring CW5 connected to the pad PD5 gradually shifts to the far side from the pad PD5 each time it goes around the pad PD5 clockwise (clockwise).

  The pad PD6 is disposed inside the spiral of the coil CL6, and one end of the coil CL6 is connected to the pad PD6. That is, the coil wiring CW6 connected to the pad PD6 circulates around the pad PD6 a plurality of times, thereby forming the coil CL6. In the case of FIG. 33, the coil wiring CW6 connected to the pad PD6 circulates around the pad PD6 counterclockwise (counterclockwise) to form the coil CL6. Since the coil wirings CW6 do not intersect each other, the coil wiring CW6 connected to the pad PD6 gradually shifts to the far side from the pad PD6 every time it circulates around the pad PD6 counterclockwise (counterclockwise).

  Here, “clockwise” is synonymous with “clockwise”, and “counterclockwise” is synonymous with “counterclockwise”. Also, when referring to the winding direction (coil direction) of a coil or coil wiring, when the coil or coil wiring is viewed from above, it refers to the winding direction when going from the inside to the outside of the vortex, and from above When viewed from the inside to the outside of the vortex, what looks clockwise is called “right-handed”, and what looks counterclockwise when going from the inside to the outside of the vortex is called “left-handed”. For example, when referring to the winding direction of the coil CL5 of the semiconductor chip CP1, when the surface side of the semiconductor chip CP1 (the side where the pads are formed is the surface side) is viewed from above the semiconductor chip CP1 (FIGS. 33 and 34). Corresponds to this), what looks clockwise when moving from the inside to the outside of the vortex of the coil CL5 is called “right-handed”, and what looks counterclockwise is called “left-handed”.

  The number of turns (turns) of the coil CL5 (coil wiring CW5) and the number of turns (turns) of the coil CL6 (coil wiring CW6) can be changed as necessary. However, the number of turns of the coil CL5 (coil wiring CW5) and the number of turns of the coil CL6 (coil wiring CW6) are preferably the same. Further, the size (diameter) of the coil CL5 and the size (diameter) of the coil CL6 are preferably the same. The self-inductance of the coil CL5 and the self-inductance of the coil CL6 are preferably the same.

  In FIG. 33, the coil CL5 is clockwise and the coil CL6 is counterclockwise, but as another form, the coil CL5 can be counterclockwise and the coil CL6 can be clockwise. In FIG. 33, the pad PD7 is arranged between the coil CL5 and the coil CL6. As another form, the pad PD7 can be arranged in a region other than between the coil CL5 and the coil CL6.

  The other end of coil CL5 (coil wiring CW5) (the end opposite to the side connected to pad PD5) and the other end of coil CL6 (coil wiring CW6) (the side opposite to the side connected to pad PD6) End) is connected to the pad PD7. For this reason, the other end of the coil CL5 (coil wiring CW5) and the other end of the coil CL6 (coil wiring CW6) are electrically connected via the pad PD7.

  Here, the other end of the coil CL5 (coil wiring CW5) corresponds to an outer end (outside of the spiral) of the coil CL5 (coil wiring CW5), and the other end of the coil CL6 (coil wiring CW6). Corresponds to the outer end (outside of the spiral) of the coil CL6 (coil wiring CW6). That is, the coil CL5 (coil wiring CW5) has an inner end (inner side of the spiral) and an outer end (outer side of the spiral), which are opposite ends, and an inner end thereof. The part is connected to the pad PD5, and the outer end is connected to the pad PD7. In addition, the coil CL6 (coil wiring CW6) has an end portion on the inner side (inside of the spiral) and an end portion on the outer side (outside of the spiral), which are ends opposite to each other. The part is connected to the pad PD6, and the outer end is connected to the pad PD7. For this reason, the pad PD7 is disposed between the coil CL5 and the coil CL6 in plan view, and is disposed between the pad PD5 and the pad PD6. The sizes (side lengths) of the pads PD5, PD6, and PD7 can be substantially the same.

  Further, since the coils CL5 and CL6 are formed on the resin film LF3, as shown in FIG. 33, the angle of the coils CL5 and CL6 (coil wirings CW5 and CW6) is set to an obtuse angle (from 90 °) as shown in FIG. It is preferable to use a large corner. This is because a resin film, particularly a polyimide film, is weak at a right angle or an acute angle of the metal pattern. By making the corners of the coils CL5 and CL6 (coil wirings CW5 and CW6) an obtuse angle (angle larger than 90 °), the resin film LF3 underlying the coils CL5 and CL6 and the protective film PA covering the coils CL5 and CL6 Reliability can be improved. This is particularly effective when the resin film LF3 underlying the coils CL5 and CL6 or the protective film PA covering the coils CL5 and CL6 is a polyimide film. In the case of FIG. 33, since the planar shape of the coils CL5 and CL6 (coil wirings CW5 and CW6) is substantially octagonal, the angle of the coils CL5 and CL6 (coil wirings CW5 and CW6) is about 135 °. Yes.

  Next, the coils CL7 and CL8 will be further described with reference to FIGS.

  As can be seen from FIG. 34, no pad is arranged inside the spiral of the coil CL7. The inner end (the inner side of the spiral) of the coil CL7 (coil wiring CW7) is electrically connected to the lead-out wiring HW1 disposed below the coil wiring CW7 via the via portion. The via portion is located between the coil wiring CW7 and the lead wiring HW1, and connects the coil wiring CW7 and the lead wiring HW1. When the coil wiring CW7 is formed in the same layer as the second wiring layer, the lead wiring HW1 is formed in the same layer as the first wiring layer one layer lower than the coil wiring CW7, that is, formed by the wiring M1, and the coil The via portion connecting the wiring CW7 and the lead wiring HW1 corresponds to the via portion V2. The lead wire HW1 is connected to a wire in the same layer as the lead wire HW1 or a wire in a different layer, and is connected to a wire corresponding to the transmission circuit TX1 formed in the semiconductor chip CP1 via the internal wire of the semiconductor chip CP1. Is done.

  The coil CL7 is formed by the coil wiring CW7 connected to the lead-out wiring HW1 through the via portion being rotated a plurality of times. It is preferable that the coil wiring CW7 does not circulate in the region (position) immediately below the pad PD5, and the coil wiring CW7 circulates so as to surround the region (position) immediately below the pad PD5.

  In the case of FIG. 34, the coil wiring CW7 connected to the lead-out wiring HW1 through the via portion circulates around the area (position) immediately below the pad PD5 clockwise (clockwise), and the coil CL7 Is formed. Since the coil wirings CW7 do not intersect with each other, the coil wiring CW7 connected to the lead-out wiring HW1 through the via portion is rotated clockwise (clockwise) around the area (position) immediately below the pad PD5. , Gradually shift away from the center of the spiral.

  Moreover, the pad is not arrange | positioned inside the spiral of coil CL8. The inner end (the inner side of the spiral) of the coil CL8 (coil wiring CW8) is electrically connected to the lead-out wiring HW2 disposed below the coil wiring CW8 through the via portion. The via portion is located between the coil wiring CW8 and the lead-out wiring HW2, and connects the coil wiring CW8 and the lead-out wiring HW8. When the coil wiring CW8 is formed in the same layer as the second wiring layer, the lead wiring HW2 is formed in the same layer as the first wiring layer one layer lower than the coil wiring CW8, that is, formed by the wiring M1, and the coil The via portion connecting the wiring CW8 and the lead wiring HW2 corresponds to the via portion V2. The lead wiring HW2 is connected to a wiring in the same layer as the lead wiring HW2 or a wiring in a different layer, and is connected to the one corresponding to the transmission circuit TX1 formed in the semiconductor chip CP1 via the internal wiring of the semiconductor chip CP1. Is done.

  The coil CL8 is formed by the coil wiring CW8 connected to the lead-out wiring HW2 through the via portion being rotated a plurality of times. It is preferable that the coil wiring CW8 does not circulate in the region (position) immediately below the pad PD6, and the coil wiring CW8 circulates so as to surround the region (position) immediately below the pad PD6.

  In the case of FIG. 34, the coil wiring CW8 connected to the lead-out wiring HW2 through the via portion circulates counterclockwise (counterclockwise) around the area (position) immediately below the pad PD6, and the coil CL8 Is formed. Since the coil wirings CW8 do not intersect with each other, the coil wiring CW8 connected to the lead-out wiring HW2 through the via portion circulates counterclockwise (counterclockwise) around the area (position) immediately below the pad PD6. In addition, it gradually shifts away from the center of the spiral.

  The number of turns (turns) of the coil CL7 (coil wiring CW7) and the number of turns (turns) of the coil CL8 (coil wiring CW8) can be changed as necessary. However, the number of turns of the coil CL7 (coil wiring CW7) and the number of turns of the coil CL8 (coil wiring CW8) are preferably the same. Further, the size (diameter) of the coil CL7 and the size (diameter) of the coil CL8 are preferably the same. Further, the self-inductance of the coil CL7 and the self-inductance of the coil CL8 are preferably the same. The mutual inductance of the magnetically coupled coils CL5 and CL7 and the mutual inductance of the magnetically coupled coils CL6 and CL8 are preferably the same. In FIG. 34, the coil CL7 is right-handed and the coil CL8 is left-handed. However, as another form, the coil CL7 can be left-handed and the coil CL8 can be right-handed.

  The outer end of the coil CL7 (coil wiring CW7) and the outer end of the coil CL8 (coil wiring CW8) are connected to a connection wiring HW3 provided between the coil CL7 and the coil CL8. It is electrically connected via the wiring HW3. That is, the inner end of the coil CL7 (coil wiring CW7) on the inner side (the inner side of the spiral) and the outer side (the outer side of the spiral) are lower than the coil wiring CW7 via the via portion. Connected to the lead wiring HW1, the outer end is connected to the connection wiring HW3 in the same layer as the coil wiring CW7. In addition, the inner end of the coil CL8 (coil wiring CW8) on the inner side (the inner side of the spiral) and the outer end (the outer side of the spiral) are lower than the coil wiring CW8 via the via portion. Connected to the lead wiring HW2, the outer end is connected to the connection wiring HW3 in the same layer as the coil wiring CW8. Therefore, one end (outer end) of the coil CL7 (coil wiring CW7) and one end (outer end) of the coil CL8 (coil wiring CW8) are electrically connected via the connection wiring HW3. Connected.

  Note that in the coil CL7 or the coil wiring CW7, the inner end (inside of the spiral) and the outer end (outside of the spiral) are opposite ends, and the coil CL8 or the coil wiring CW8 The inner (inner side of the spiral) end and the outer (outer side of the spiral) end are opposite ends.

  The connection wiring HW3 is formed in the same layer as the coil CL7 (coil wiring CW8) and the coil CL8 (coil wiring CW8), and the outer end of the coil CL7 (coil wiring CW7) and the coil CL8 (coil wiring CW8). Wiring for electrically connecting the outer end. Since the connection wiring HW3 is disposed between the coils CL7 and CL8, when the pad PD7 is disposed between the coils CL5 and CL6, the connection wiring HW3 is disposed immediately below the pad PD7. become. The connection wiring HW3 can have a planar shape (planar dimension) substantially the same as that of the pad PD7, but does not function as a pad (thus, a connection member such as a bonding wire is not connected). Different planar shapes (planar dimensions) can also be used. For example, the outer end of the coil CL7 (coil wiring CW7) and the outer end of the coil CL8 (coil wiring CW8) may be connected by a connection wiring HW3 having a width comparable to that of the coil wirings CW7 and CW8. Is possible. However, if the connection wiring HW3 having a wiring width larger than the wiring widths of the coil wirings CW7 and CW8 is provided between the coil CL7 and the coil CL8 in plan view, the wiring resistance can be reduced.

  The coil CL7 and the coil CL8 connected in series correspond to the coil CL1a on the primary side of the transformer TR1 (and thus the coil CL1), and the coil CL5 and the coil CL6 connected in series are connected to the secondary side of the transformer TR1. This corresponds to the coil CL2a (and thus the coil CL2). The lead-out wirings HW1 and HW2 are connected to the transmission circuit TX1 formed in the semiconductor chip CP1 via the internal wirings (M1 to M3) of the semiconductor chip CP1. The pads PD5, PD6, and PD7 are formed in the semiconductor chip CP2 through conductive connection members such as bonding wires BW described later connected to the pads PD5, PD6, and PD7 and the internal wiring of the semiconductor chip CP2. It is connected to the formed receiving circuit RX1.

  For this reason, when a transmission signal is sent from the transmission circuit TX1 to the lead wires HW1 and HW2, a current flows through the coils CL7 and CL8 connected in series between the lead wire HW1 and the lead wire HW2. At this time, since the coil CL7 and the coil CL8 are connected in series, the current flowing through the coil CL7 and the current flowing through the coil CL8 have substantially the same magnitude. The coil CL5 and the coil CL7 are not connected by a conductor but are magnetically coupled, and the coil CL6 and the coil CL8 are not coupled by a conductor but are magnetically coupled. For this reason, when a current flows through the primary side coil CL7 and the coil CL8, an induced electromotive force is generated in the secondary side coil CL5 and the coil CL6 according to the change in the current, and the induced current flows. Yes.

  Also, the transformer TR2 of the semiconductor chip CP2 can be formed in the same manner as the transformer TR1 of the semiconductor chip CP1. Therefore, also in the semiconductor chip CP2, the coils CL7 and CL8 are formed as the coil CL1b, the coils CL5 and CL6 are formed as the coil CL2b, and the pads PD5, PD6 and PD7 connected to the coils CL5 and CL6 are formed. Can be formed.

  The pad PD5 is arranged inside the coil CL5 (coil wiring CW5) (inside the spiral), and the pad PD6 is arranged inside the coil CL6 (coil wiring CW6) (inside the spiral).

  By arranging the pad PD5 inside the coil CL5 (coil wiring CW5), the inner end of the coil CL5 is padded without forming a lead wiring (lead wiring for connecting the pad PD5 and the coil CL5). It can be connected to PD5. For this reason, it is not necessary to form a lead wiring for the pad PD5 in the lower layer of the coil CL5 (coil wiring CW5). Therefore, the withstand voltage between the coil CL5 and the coil CL7 becomes dominant as the withstand voltage of the transformer. Can be further improved. Further, since it is not necessary to form the lead wiring for the pad PD5, it is not necessary to form a via portion for connecting to the lead wiring, so that the manufacturing cost and the manufacturing time can be suppressed. The same applies to the pad PD6 and the coil CL6.

  The inner end of the coil CL7 (coil wiring CW7) is connected to the lead-out wiring HW1 below the coil wiring CW7 via the via, and the inner end of the coil CL8 (coil wiring CW8) is connected to the via. It is connected to the lead-out wiring HW2 below the coil wiring CW8 through the section. As another form, one or both of the lead wirings HW1 and HW2 can be provided in an upper layer than the coils CL7 and CL8 and in a lower layer than the coils CL5 and CL6. Lead wires HW1 and HW2 are formed. However, in terms of improving the breakdown voltage, it is more advantageous that both the lead-out wirings HW1 and HW2 are formed below the coils CL7 and CL8, so that the withstand voltage between the coils CL5 and CL7 is increased. In addition, the withstand voltage between the coil CL6 and the coil CL8 becomes dominant as the withstand voltage of the transformer, and the withstand voltage of the transformer can be further improved.

  In addition, slits (openings) can be provided in the lead wirings HW1 and HW2. The slits can be slits having long sides along the extending direction in the lead lines HW1 and HW2, and one or a plurality of slits can be provided in each of the lead lines HW1 and HW2. When a current is passed through the primary side coils CL7, CL8 or an induced current is passed through the secondary side coils CL5, CL6, a magnetic flux is generated so as to penetrate the coils CL5, CL6, CL7, CL8, but the lead wiring HW1. If a slit is provided in HW2, it is possible to suppress or prevent the generation of eddy currents in the lead-out wirings HW1 and HW2 due to the influence of magnetic flux.

  In the present embodiment, the coil CL5 and the coil CL6 are formed in the same layer, and the coil CL7 and the coil CL8 are formed in the same layer. The coils CL7 and CL8 are formed below the coils CL5 and CL6. Of the coils CL5 and CL6 and the coils CL7 and CL8, the coils CL5 and CL6 to be connected to the pads PD5, PD6 and PD7 are arranged on the upper layer side, so that the coils CL5 and CL6 are connected to the pads PD5, PD6 and PD7. It becomes easy. Further, by forming the coil CL5 and the coil CL6 in the same layer and forming the coil CL7 and the coil CL8 in the same layer, the mutual inductance of the coils CL5 and CL7 and the mutual inductance of the coils CL6 and CL8 can be easily matched. Become. For this reason, it becomes easy to accurately transmit signals through the coils CL5, CL6, CL7, and CL8. Further, the number of layers necessary to form the coils CL5, CL6, CL7, and CL8 can be suppressed. This makes it easier to design a semiconductor chip. Further, it is advantageous for miniaturization of the semiconductor chip.

  As shown in FIG. 33, the inner end of the coil CL5 (coil wiring CW5) is connected to the pad PD5, and the inner end of the coil CL6 (coil wiring CW6) is connected to the pad PD6. The outer end of (coil wiring CW5) and the outer end of coil CL6 (coil wiring CW6) are connected to pad PD7. The connection positions of the pads PD5, PD6, and PD7 and the coils CL5 and CL6 (coil wirings CW5 and CW6) are not the center of the sides of the pads PD5, PD6, and PD7, but near the corners of the pads PD5, PD6, and PD7. It is preferable to do. The connection positions of the pads PD5, PD6, and PD7 and the coils CL5 and CL6 (coil wirings CW5 and CW6) tend to be locations where disconnections are likely to occur. However, the connection positions are defined as the corners of the pads PD5, PD6, and PD7. It is possible to suppress or prevent the occurrence of disconnection at the connection point. There are two reasons for this.

  First, the first reason will be explained. The disconnection at the connection position between the pad and the coil tends to occur when a bonding wire is connected to the pad later. For this reason, in each of the pads PD5, PD6, and PD7, disconnection is less likely to occur when the connection position between the pad and the coil is as far as possible from the wire bond position (position where the bonding wire is connected). In each pad PD5, PD6, PD7, the wire bond position is approximately the center of the pad. For this reason, the connection position between the pad and the coil is not the center of the side of each pad PD5, PD6, PD7, but near the corner of each pad PD5, PD6, PD7. The distance between the bond positions can be increased. Thereby, the disconnection in the connection position of pad PD5, PD6, PD7 and coil CL5, CL6 (coil wiring CW5, CW6) can be suppressed or prevented.

  Next, the second reason will be described. When wire bonding is performed on the pad, ultrasonic vibration is applied, and the vibration direction of the ultrasonic vibration is a direction parallel to the side of the pad (vertical direction or horizontal direction). For this reason, when the connection position between the pad and the coil is set to the center of the side of each pad PD5, PD6, PD7, the ultrasonic vibration is applied to the connection position between the pad and the coil. . On the other hand, the connection position between the pad and the coil is not the center of the side of each pad PD5, PD6, PD7, but near the corner of each pad PD5, PD6, PD7. Vibration is less likely to be applied to the connection position between the pad and the coil. For this reason, the disconnection at the connection position of the pads PD5, PD6, PD7 and the coils CL5, CL6 (coil wirings CW5, CW6) can be suppressed or prevented.

  For this reason, the connection positions of the pads PD5, PD6, PD7 and the coils CL5, CL6 (coil wirings CW5, CW6) are not the center of the sides of the pads PD5, PD6, PD7, but the corners of the pads PD5, PD6, PD7. It is preferable to be in the vicinity of the part. Here, the planar shape of each pad PD5, PD6, PD7 is a substantially rectangular shape, a shape with the corners of the rectangle dropped, or a shape with rounded corners of the rectangles. FIG. 33 shows a case where the planar shape of each pad PD5, PD6, PD7 is a planar shape with a rectangular corner dropped. When the planar shape of each of the pads PD5, PD6, and PD7 is rectangular, the coils CL5 and CL6 (coil wirings CW5 and CW6) are connected not to the center of the rectangular side but to a position shifted toward the corner of the rectangle. That's fine. When the planar shape of each pad PD5, PD6, PD7 is a shape with a rectangular corner dropped or a shape with a rounded corner, the corner of the base rectangle is not the center of the base side of the rectangle. Coils CL5 and CL6 (coil wirings CW5 and CW6) may be connected to positions shifted to the part side.

<Variation of Coil Configuration>
Next, a modified example of the configuration of the coil constituting the transformer formed in the semiconductor chip will be described. FIG. 37 and FIG. 38 are main part plan views of modifications of the semiconductor chip CP1 (or semiconductor chip CP2), showing a plan view of the coil formed in the transformer forming region 1B. FIG. 37 is a view corresponding to FIG. 33, showing the coils (coils CL5, CL6) on the secondary side of the transformer formed in the semiconductor chip CP1 (or the semiconductor chip CP2), and FIG. The primary coil (coil CL7, CL8) of the transformer is shown. In addition, in FIG. 38, the lead wires HW1 and HW2 are indicated by dotted lines so that the relative positional relationship between the primary side coils (CL7 and CL8) and the lead wires (lead wires HW1 and HW2) can be easily understood. is there.

  In the case of FIG. 33 and FIG. 34 described above, the winding direction of the coils CL7 and CL8 on the primary side is the opposite direction between the coils CL7 and CL8, and the winding of the coils on the secondary coils CL5 and CL6 is reversed. The direction was opposite between the coil CL5 and the coil CL6. That is, one of the coils CL7 and CL8 is right-handed and the other is left-handed, and one of the coils CL5 and CL6 is right-handed and the other is left-handed.

  On the other hand, in the case of FIGS. 37 and 38, the winding direction of the coils CL7 and CL8 on the primary side is the same between the coils CL7 and CL8, and the coils on the coils CL5 and CL6 on the secondary side are the same. Is the same in the coil CL5 and the coil CL6. That is, both the coil CL7 and the coil CL8 are right-handed or both are left-handed, and the coil CL5 and the coil CL6 are both right-handed or both are left-handed. In the case of FIG. 38, the coils CL7 and CL8 are both right-handed, but as another form, both the coils CL7 and CL8 can be left-handed. In the case of FIG. Although both are right-handed, as another form, both the coils CL5 and CL6 can be left-handed.

  Other configurations of the coils CL5, CL6, CL7, CL8, the pads PD5, PD6, PD7 and the lead wires HW1, HW2 in FIGS. 37 and 38 are the same as those described with reference to FIGS. Therefore, the repeated explanation is omitted here.

  In the case of FIG. 33 and FIG. 34 described above, since the winding direction is opposite between the coil CL7 and the coil CL8, when a current flows through the coil CL7 and the coil CL8 connected in series, the current flows between the coil CL7 and the coil CL8. The flowing directions are the same, and accordingly, magnetic fluxes in the same direction are generated in the coils CL7 and CL8. For this reason, when the induced current flows through the secondary coils CL5 and CL6, the direction of the current flowing through the coil CL5 is the same as the direction of the current flowing through the coil CL6, and accordingly the induced current flowing through the coil CL5. The direction of the magnetic flux generated so as to pass through the coil CL5 is the same as the direction of the magnetic flux generated so as to pass through the coil CL6 due to the induced current flowing through the coil CL6. Accordingly, when a signal is transmitted from the transmission circuit to the reception circuit via the transformer, the direction of the magnetic flux generated so as to penetrate the magnetically coupled coil CL5 and coil CL7, and the magnetically coupled coil CL6 and coil CL8 penetrate. The directions of the generated magnetic fluxes are the same as each other.

  Here, the direction of the current of the coil (or the direction of current flow) means that when the coil (or coil wiring) is viewed from above, the current flows clockwise (clockwise) or counterclockwise (counterclockwise). Indicates whether current flows clockwise. For this reason, when the direction of the current of the coil is the same (or the direction of current flow) is the same for the two coils, the two coils are both clockwise when viewed from above. Corresponding to a current flowing clockwise), or both of the two coils flowing counterclockwise (counterclockwise). Also, when the direction of the coil current is opposite (or the direction of current flow is opposite) for the two coils, one of the two coils is on the right when viewed from above. The current flows in the clockwise direction (clockwise), and the other coil corresponds to the current flowing in the counterclockwise direction (counterclockwise).

  On the other hand, in the case of FIG. 37 and FIG. 38, since the winding direction is the same in the coil CL7 and the coil CL8, when a current flows through the coil CL7 and the coil CL8 connected in series, the coil CL7 and the coil CL8. The directions of current flow are opposite to each other, and accordingly, magnetic fluxes in opposite directions are generated in the coils CL7 and CL8. For this reason, when an induced current flows through the coils CL5 and CL6 on the secondary side, the direction of the current flowing through the coil CL5 is opposite to the direction of the current flowing through the coil CL6, and accordingly, the induced current flowing through the coil CL5. The direction of the magnetic flux generated through the coil CL5 is opposite to the direction of the magnetic flux generated through the coil CL6 by the induced current flowing through the coil CL6. Accordingly, when a signal is transmitted from the transmission circuit to the reception circuit via the transformer, the direction of the magnetic flux generated so as to penetrate the magnetically coupled coil CL5 and coil CL7, and the magnetically coupled coil CL6 and coil CL8 penetrate. The directions of the generated magnetic fluxes are opposite to each other.

  If the magnetic flux (magnetic field) that passes through the coils CL5 and CL7 and the magnetic flux (magnetic field) that passes through the coils CL6 and CL8 are in opposite directions, the magnetic flux that passes through the coil CL5 (magnetic field) and the magnetic flux that passes through the coil CL6 (magnetic field) (I.e., it can be closed in a loop). Therefore, in the case of FIG. 37 and FIG. 38 described above, it is possible to suppress or prevent the coils CL5 and CL6 from acting so as to cancel each other out of the magnetic flux (magnetic field). It is possible to suppress or prevent the magnetic field from acting so as to cancel each other. Accordingly, when signals are transmitted from the primary coils (CL7, CL8) to the secondary coils (CL5, CL6) using the induced current, the signal strength (reception signal strength) detected by the secondary coils (CL5, CL6) is determined. Can be improved. Therefore, the performance of the semiconductor chip can be further improved, and as a result, the performance of the semiconductor device including the semiconductor chip can be further improved.

  Next, another modified example of the configuration of the coil constituting the transformer formed in the semiconductor chip will be described. 39 and 40 are main part plan views of another modification of the semiconductor chip CP1 (or the semiconductor chip CP2), showing a plan view of a coil formed in the transformer forming region 1B. FIG. 39 is a view corresponding to FIG. 33, showing a secondary coil (coil CL5) of the transformer formed in the semiconductor chip CP1 (or semiconductor chip CP2), and FIG. 40 corresponds to FIG. A coil (coil CL7) on the primary side of the transformer is shown. In addition, in FIG. 40, the lead wires HW1 and HW3a are indicated by dotted lines so that the relative positional relationship between the primary coil (CL7) and the lead wires (lead wires HW1 and HW3a) can be easily understood.

  39 and 40, the primary coil is composed of one coil CL5, the coil CL6 and the pad PD6 are not formed, and the secondary coil is one coil CL7. The coil CL8 and the lead wiring HW1 are not formed. The outer end of the coil CL7 is connected not to the connection wiring HW3 but to the extraction wiring HW3a, but this extraction wiring HW3a can be formed in the same layer as or different from the coil CL7. In the case of FIG. 40, the case where the outer end portion of the coil CL7 is connected to the lead wire HW3a provided in the same layer as the lead wire HW1 through the via portion is shown, but the lead wire HW3a is connected to the coil CL7. You may form in the same layer.

  The other configurations of the coils CL5 and CL7, the pads PD5 and PD7 and the lead wires HW1 and HW3a in FIGS. 39 and 40 are the same as those described with reference to FIGS. Description of is omitted. The circuit configuration of the transformer is the same as in FIG. For example, when the transformers of FIGS. 39 and 40 are applied to the transformer TR1 of FIG. 1, the coil CL5 is the coil CL1a and the coil CL7 is the coil CL2a.

  In the case of FIGS. 32 to 36 and FIGS. 37 and 38, the primary coil and the secondary coil are each composed of two coils, that is, the transformer TR1 is composed of two transformers. Since two transformers can be operated differentially, noise tolerance can be improved. On the other hand, in the case of FIG. 39 and FIG. 40, each of the primary coil and the secondary coil is constituted by one coil, that is, the transformer TR1 is constituted by one transformer. ).

<Configuration example of semiconductor package>
Next, a configuration example of the semiconductor package of this embodiment will be described. The semiconductor package can also be regarded as a semiconductor device.

  41 is a plan view showing a semiconductor package (semiconductor device) PKG of the present embodiment, and FIG. 42 is a cross-sectional view of the semiconductor package PKG. However, in FIG. 41, the sealing resin portion MR is seen through, and the outer shape (outer periphery) of the sealing resin portion MR is indicated by a two-dot chain line. A cross-sectional view taken along line B1-B1 of FIG. 41 substantially corresponds to FIG.

  The semiconductor package PKG shown in FIGS. 41 and 42 is a semiconductor package including semiconductor chips CP1 and CP2. Hereinafter, the configuration of the semiconductor package PKG will be specifically described.

  The semiconductor package PKG shown in FIGS. 41 and 42 includes semiconductor chips CP1 and CP2, die pads DP1 and DP2 for mounting the semiconductor chips CP1 and CP2, respectively, a plurality of leads LD made of a conductor, and semiconductor chips CP1 and CP2. And a plurality of bonding wires BW for connecting the semiconductor chips CP1 and CP2 and the plurality of leads LD, and a sealing resin portion MR for sealing them.

  The sealing resin portion (sealing portion, sealing resin, sealing body) MR is made of, for example, a resin material such as a thermosetting resin material, and can include a filler. The semiconductor chips CP1 and CP2, die pads DP1 and DP2, the plurality of leads LD, and the plurality of bonding wires BW are sealed and electrically and mechanically protected by the sealing resin portion MR. The planar shape (outer shape) intersecting the thickness of the sealing resin portion MR can be, for example, a rectangle (quadrangle).

  A plurality of pads (pad electrodes, bonding pads) PD10 are formed on the surface of the semiconductor chip CP1, which is the main surface on the element formation side of the semiconductor chip CP1. Each pad PD10 of the semiconductor chip CP1 is electrically connected to a semiconductor integrated circuit (for example, the control circuit CC) formed inside the semiconductor chip CP1. The pad PD10 corresponds to the pad PD2 connected to the rewiring RW in the semiconductor chip CP1.

  Further, pads (pad electrodes, bonding pads) PD5a, PD6a, and PD7a corresponding to the pads PD5, PD6, and PD7 are formed on the surface of the semiconductor chip CP1.

  That is, the semiconductor chip CP1 includes the transmission circuit TX1, the coils CL7 and CL8 (primary coils) connected to the transmission circuit TX1, and the coils CL5 and CL6 (magnetic coils coupled to the coils CL7 and CL8, respectively). Secondary coil) and the pads PD5, PD6, PD7 connected to the coils CL5, CL6. The pad PD5 included in the semiconductor chip CP1 corresponds to the pad PD5a, the pad PD6 included in the semiconductor chip CP1 corresponds to the pad PD6a, and the pad PD7 included in the semiconductor chip CP1 corresponds to the pad PD7a.

  The semiconductor chip CP1 further includes the receiving circuit RX2 and a plurality of pads (pad electrodes, bonding pads) PD9 connected to the receiving circuit RX2. Therefore, pads PD5a, PD6a, PD7a, PD9, and PD10 are formed on the surface of the semiconductor chip CP1. Of the plurality of pads PD9 of the semiconductor chip CP1, the pad PD9 connected to the pad PD7b of the semiconductor chip CP2 via the bonding wire BW supplies a fixed potential (ground potential, GND potential, power supply potential, etc.). It is.

  A plurality of pads PD11 are formed on the surface of the semiconductor chip CP2, which is the main surface on the element forming side of the semiconductor chip CP2. Each pad PD11 of the semiconductor chip CP2 is electrically connected to a semiconductor integrated circuit (for example, the drive circuit DR) formed inside the semiconductor chip CP2. The pad PD11 corresponds to the pad PD2 connected to the rewiring RW in the semiconductor chip CP2.

  Further, pads (pad electrodes, bonding pads) PD5b, PD6b, and PD7b corresponding to the pads PD5, PD6, and PD7 are formed on the surface of the semiconductor chip CP2.

  That is, the semiconductor chip CP2 includes the transmission circuit TX2, the coils CL7 and CL8 (primary coils) connected to the transmission circuit TX2, and the coils CL5 and CL6 (magnetic coils coupled to the coils CL7 and CL8, respectively). Secondary coil) and the pads PD5, PD6, PD7 connected to the coils CL5, CL6. The pad PD5 included in the semiconductor chip CP2 corresponds to the pad PD5b, the pad PD6 included in the semiconductor chip CP2 corresponds to the pad PD6b, and the pad PD7 included in the semiconductor chip CP2 corresponds to the pad PD7b.

  The semiconductor chip CP2 further includes the receiving circuit RX1 and a plurality of pads (pad electrodes, bonding pads) PD8 connected to the receiving circuit RX1. For this reason, pads PD5b, PD6b, PD7b, PD8, and PD11 are formed on the surface of the semiconductor chip CP2. Of the plurality of pads PD8 of the semiconductor chip CP2, the pad PD8 connected to the pad PD7a of the semiconductor chip CP1 via the bonding wire BW supplies a fixed potential (ground potential, GND potential, power supply potential, etc.). It is.

  In the semiconductor chip CP1, the main surface on which the pads PD5a, PD6a, PD7a, PD9, and PD10 are formed is referred to as the front surface of the semiconductor chip CP1, and the main surface on the opposite side is referred to as the back surface of the semiconductor chip CP1. Shall. In the semiconductor chip CP2, the main surface on the side where the pads PD, PD5b, PD6b, PD7b, PD8, and PD11 are formed is called the surface of the semiconductor chip CP2, and the main surface on the opposite side is the back surface of the semiconductor chip CP2. Shall be called.

  The semiconductor chip CP1 is mounted (arranged) on the upper surface of the die pad DP1, which is a chip mounting portion, so that the surface of the semiconductor chip CP1 faces upward, and the back surface of the semiconductor chip CP1 is bonded to the upper surface of the die pad DP1 by a die bond material (adhesive) ) It is bonded and fixed via DB.

  The semiconductor chip CP2 is mounted (arranged) on the upper surface of the die pad DP2, which is a chip mounting portion, so that the surface of the semiconductor chip CP2 faces upward, and the back surface of the semiconductor chip CP2 is bonded to the upper surface of the die pad DP2. ) It is bonded and fixed via DB.

  The die pad DP1 and the die pad DP2 are separated from each other with a material constituting the sealing resin portion MR interposed therebetween, and are electrically insulated from each other.

  The lead LD is formed of a conductor and is preferably made of a metal material such as copper (Cu) or a copper alloy. Each lead LD is composed of an inner lead portion which is a portion located in the sealing resin portion MR of the lead LD and an outer lead portion which is a portion located outside the sealing resin portion MR in the lead LD. The outer lead portion of the lead LD protrudes from the side surface of the sealing resin portion MR to the outside of the sealing resin portion MR. The space between the inner lead portions of adjacent leads LD is filled with the material constituting the sealing resin portion MR. The outer lead portion of each lead LD can function as an external connection terminal portion (external terminal) of the semiconductor package PKG. The outer lead portion of each lead LD is bent so that the lower surface near the end of the outer lead portion is positioned slightly below the lower surface of the sealing resin portion MR.

  The pads PD10 on the surface of the semiconductor chip CP1 and the pads PD11 on the surface of the semiconductor chip CP2 are electrically connected to the inner lead portions of the leads LD via bonding wires BW that are conductive connection members, respectively. Yes. That is, the other end of the bonding wire BW whose one end is connected to each pad PD10 on the surface of the semiconductor chip CP1 is connected to the upper surface of the inner lead portion of each lead LD. Further, the other end of the bonding wire BW having one end connected to each pad PD11 on the surface of the semiconductor chip CP2 is connected to the upper surface of the inner lead portion of each lead LD. The lead LD to which the pad PD10 of the semiconductor chip CP1 is connected via the bonding wire BW and the lead LD to which the pad PD11 of the semiconductor chip CP2 is connected via the bonding wire BW are different leads LD. . For this reason, the pad PD10 of the semiconductor chip CP1 and the pad PD11 of the semiconductor chip CP2 are not connected via a conductor.

  Further, the pads PD5a, PD6a, PD7a on the surface of the semiconductor chip CP1 are electrically connected to the pads PD8 on the surface of the semiconductor chip CP2 via bonding wires BW, respectively. Further, the pads PD5b, PD6b, PD7b on the surface of the semiconductor chip CP2 are electrically connected to the pads PD9 on the surface of the semiconductor chip CP1 through bonding wires BW, respectively.

  The bonding wire BW is a conductive connecting member (connecting member), but more specifically is a conductive wire, and is made of a fine metal wire such as a gold (Au) wire or a copper (Cu) wire. The bonding wire BW is sealed in the sealing resin portion MR and is not exposed from the sealing resin portion MR.

  Here, the bonding wire BW connecting the pads PD5a, PD6a, PD7a of the semiconductor chip CP1 and the pad PD8 of the semiconductor chip CP2 is hereinafter referred to as a bonding wire BW8 with reference sign BW8. Further, hereinafter, the bonding wire BW connecting the pads PD5b, PD6b, PD7b of the semiconductor chip CP2 and the pad PD9 of the semiconductor chip CP1 will be referred to as a bonding wire BW9 with reference sign BW9.

  The semiconductor chip CP1 and the semiconductor chip CP2 are connected by bonding wires BW8 and BW9, but are not connected by other bonding wires BW (conductive connecting members). For this reason, electrical signals are transmitted between the semiconductor chip CP1 and the semiconductor chip CP2 from the pads PD5a, PD6a, PD7a of the semiconductor chip CP1 to the pads PD8 of the semiconductor chip CP2 via the bonding wires BW8, and the semiconductor. Only the path from the pads PD5b, PD6b, PD7b of the chip CP2 to the pad PD9 of the semiconductor chip CP2 via the bonding wire BW9.

  The pads PD5a, PD6a and PD7a of the semiconductor chip CP1 are connected to the coils CL5 and CL6 (secondary coils) formed in the semiconductor chip CP1. The coils CL5 and CL6 are connected to the semiconductor chip CP1. The formed circuit is not connected via a conductor (internal wiring) but is magnetically coupled to the coils CL7 and CL8 (primary coils) in the semiconductor chip CP1. Therefore, an electromagnetic wave is generated from a circuit (such as the transmission circuit TX1) formed in the semiconductor chip CP1 via the coils CL7 and CL8 (primary coils) and the coils CL5 and CL6 (secondary coils) in the semiconductor chip CP1. Only the signal transmitted by induction is input from the pads PD5a, PD6a, and PD7a to the semiconductor chip CP2 (the receiving circuit RX1) via the bonding wire BW8.

  The pads PD5b, PD6b, and PD7b of the semiconductor chip CP2 are connected to the coils CL5 and CL6 (secondary coils) formed in the semiconductor chip CP2. The coils CL5 and CL6 are connected to the semiconductor chip CP2. The formed circuit is not connected via a conductor (internal wiring) but is magnetically coupled to the coils CL7 and CL8 (primary coils) in the semiconductor chip CP2. Therefore, an electromagnetic wave is generated from a circuit (such as the transmission circuit TX2) formed in the semiconductor chip CP2 via the coils CL7 and CL8 (primary coils) and the coils CL5 and CL6 (secondary coils) in the semiconductor chip CP2. Only the signal transmitted by induction is input from the pads PD5b, PD6b, PD7b to the semiconductor chip CP1 (the receiving circuit RX2) via the bonding wire BW9.

  The semiconductor chip CP1 and the semiconductor chip CP2 have different voltage levels (reference potentials). For example, the drive circuit DR drives a load LOD such as a motor. Specifically, the drive circuit DR drives or controls a switch (switching element) of the load LOD such as a motor, and switches the switch. For this reason, when the switch to be driven is turned on, the reference potential (voltage level) of the semiconductor chip CP2 may rise to a voltage that substantially matches the power supply voltage (operating voltage) of the switch to be driven. The voltage is a considerably high voltage (for example, about several hundred V to several thousand V). For this reason, a large difference occurs in the voltage level (reference potential) between the semiconductor chip CP1 and the semiconductor chip CP2. That is, when the switch to be driven is turned on, the semiconductor chip CP2 has a voltage (for example, about several hundred V to several thousand V) higher than a power supply voltage (for example, about several V to several tens V) supplied to the semiconductor chip CP1. ) Will be supplied.

  However, as described above, the electrical transmission between the semiconductor chip CP1 and the semiconductor chip CP2 is electromagnetic via the primary coils (CL7, CL8) and secondary coils (CL5, CL6) in the semiconductor chip CP1. It is only a signal transmitted by induction or a signal transmitted by electromagnetic induction via the primary coils (CL7, CL8) and secondary coils (CL5, CL6) in the semiconductor chip CP2. Therefore, even if the voltage level (reference potential) of the semiconductor chip CP1 and the voltage level (reference potential) of the semiconductor chip CP2 are different, the voltage level (reference potential) of the semiconductor chip CP2 is input to the semiconductor chip CP1, Alternatively, it is possible to accurately prevent the voltage level (reference potential) of the semiconductor chip CP1 from being input to the semiconductor chip CP2. That is, it is assumed that the switch to be driven is turned on and the reference potential (voltage level) of the semiconductor chip CP2 has risen to a voltage that substantially matches the power supply voltage (for example, about several hundred V to several thousand V) of the drive target In addition, it is possible to accurately prevent the reference potential of the semiconductor chip CP2 from being input to the semiconductor chip CP1. For this reason, electrical signals can be accurately transmitted between the semiconductor chips CP1 and CP2 having different voltage levels (reference potentials). Further, the reliability of the semiconductor chip CP1 and the semiconductor chip CP2 can be improved. In addition, the reliability of the semiconductor package PKG can be improved. In addition, the reliability of the electronic device using the semiconductor package PKG can be improved.

  In addition, since signals are transmitted between semiconductor chips using magnetically coupled coils, the semiconductor package PKG can be reduced in size and reliability can be improved.

  The semiconductor package PKG can be manufactured as follows, for example. That is, first, a lead frame in which die pads DP1 and DP2 and a plurality of leads LD are coupled to a frame frame is prepared, a die bonding process is performed, and a die bond material (adhesive) is formed on the die pads DP1 and DP2 of the lead frame. The semiconductor chips CP1 and CP2 are mounted and bonded via DB. Then, a wire bonding process is performed. Thereby, the plurality of pads PD10 of the semiconductor chip CP1 are electrically connected to the plurality of leads LD via the plurality of bonding wires BW. In addition, the plurality of pads PD11 of the semiconductor chip CP2 are electrically connected to another plurality of leads LD via another plurality of bonding wires BW. Further, the plurality of pads PD5a, PD6a, PD7a of the semiconductor chip CP1 are electrically connected to the plurality of pads PD8 of the semiconductor chip CP2 through the plurality of bonding wires BW8. Further, the plurality of pads PD5b, PD6b, PD7b of the semiconductor chip CP2 are electrically connected to the plurality of pads PD9 of the semiconductor chip CP1 through the plurality of bonding wires BW9. Then, a sealing resin portion MR for sealing the semiconductor chips CP1 and CP2, die pads DP1 and DP2, a plurality of leads LD, and a plurality of bonding wires BW (including bonding wires BW8 and BW9) is performed by performing a resin sealing process. Form. Then, after the plurality of leads LD whose inner lead portions are sealed by the sealing resin portion MR are cut and separated from the frame frame of the lead frame, the outer lead portions of the plurality of leads LD are bent. In this way, the semiconductor package PKG can be manufactured.

  Here, a product application example in which the semiconductor package PKG is mounted will be described. For example, there are motor control units for household appliances such as automobiles and washing machines, switching power supplies, lighting controllers, solar power generation controllers, cellular phones, and mobile communication devices.

  For example, for automobile use, the semiconductor chip CP1 is a low-voltage chip to which a low-voltage power supply voltage is supplied, and the supply power supply voltage at that time is, for example, about 5V. On the other hand, the power supply voltage of the switch to be driven by the drive circuit DR is, for example, a high voltage of 600 V to 1000 V or more, and this high voltage can be supplied to the semiconductor chip CP2 when the switch is on.

  Here, the case of SOP (Small Outline Package) has been described as an example of the package form of the semiconductor package PKG. However, the present invention can be applied to other than SOP.

(Embodiment 2)
43 is a main-portion cross-sectional view showing the cross-sectional structure of the semiconductor device of the second embodiment, and corresponds to FIG. 3 of the first embodiment.

  In the first embodiment, as shown in FIG. 3, the coil CL1, which is the primary coil of the transformer, is formed in a lower layer than the pad PD1. In the case of FIG. 3, the coil CL1 is formed in the second wiring layer that is one layer lower than the third wiring layer in which the pad PD1 is formed (that is, in the same layer as the wiring M2).

  On the other hand, in the second embodiment, as shown in FIG. 43, the coil CL1, which is the primary coil of the transformer, is formed in the same layer as the pad PD1. That is, the coil CL1 is formed in the third wiring layer where the pad PD1 is formed (that is, in the same layer as the wiring M3). For this reason, in the second embodiment, the interlayer insulating film IL3 is not interposed between the coil CL1 and the coil CL2, and only the laminated film LF is interposed, and the silicon oxide film LF1 of the laminated film LF. Is formed in contact with the coil CL1 so as to cover the coil CL1.

  Since the other configuration is basically the same as that of the second embodiment, the description thereof will not be repeated here.

  Also in the second embodiment, substantially the same effects as described in the first embodiment can be obtained. However, the first embodiment has the following advantages over the second embodiment.

  That is, in the second embodiment, the laminated film LF is interposed between the coil CL1 and the coil CL2, and the dielectric strength between the coil CL1 and the coil CL2 is secured by the laminated film LF. On the other hand, in the first embodiment, not only the laminated film LF but also an interlayer insulating film (in the case of FIG. 3, the interlayer insulating film IL3) is interposed between the coil CL1 and the coil CL2. The dielectric breakdown voltage between the coil CL1 and the coil CL2 is secured by the LF and the interlayer insulating film. Therefore, since the interlayer insulating film (interlayer insulating film IL3 in the case of FIG. 3) is also interposed between the coil CL1 and the coil CL2, the first embodiment has a higher coil CL1 than the second embodiment. And the coil CL2 can be further increased in withstand voltage.

  Further, when the coil CL1 and the pad PD1 are formed in the same layer as in the second embodiment, the thickness of the coil CL1 is increased. This is because the thickness of the pad PD1 is thicker (larger) than the thickness of the lower layer wiring (here, the wiring M1 and the wiring M2) than the pad PD1. If the thickness of the coil CL1 is thick, it becomes difficult to embed a space between adjacent spiral coil wirings constituting the coil CL1 with an insulating film. Therefore, it is necessary to manage the film forming process of the insulating film relatively strictly. On the other hand, in the first embodiment, since the coil CL1 is formed below the pad PD1, the thickness of the coil CL1 can be made thinner (smaller) than the thickness of the pad PD1. For this reason, since it becomes easy to embed a space between adjacent spiral coil wirings constituting the coil CL1 with an insulating film, the film forming process of the insulating film can be easily managed. For this reason, it becomes easy to manufacture a semiconductor device. In addition, since the space between adjacent spiral coil wires constituting the coil CL1 can be more reliably embedded with an insulating film, the reliability of the semiconductor device can be further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

BW, BW8, BW9 Bonding wire CC Control circuit CF Copper film CL1, CL1a, CL1b, CL2, CL2a, CL2b Coil CL5, CL6, CL7, CL8 Coil CP1, CP2 Semiconductor chips CW5, CW6, CW7, CW8 Coil wiring DB Die bond material DP1, DP2 Die pad DR Drive circuit G1, G2 Gate electrode GF Gate insulating film HW1, HW2, HW3a Lead wiring HW3 Connection wiring IL1, IL2, IL3 Interlayer insulating film LD Lead LF Multilayer film LF1 Silicon oxide film LF2 Silicon nitride film LF3 Resin film LOD load M1, M2, M3 wiring MR sealing resin part NS n-type semiconductor region NW n-type well OP1, OP1a, OP1b, OP1c, OP2, OP3 opening PA protective film PD1, PD2, PD3, PD5, PD5a, PD b pad PD6, PD6a, PD6b, PD7, PD7a, PD7b pad PD8, PD9, PD10, PD11 pad PKG semiconductor package PR1, PR2 resist pattern PS p-type semiconductor region PW p-type well RW rewiring RX1, RX2 receiving circuit SB semiconductor substrate SE seed film SG1, SG2, SG3, SG4 signal ST element isolation region TR1, TR2 transformer TX1, TX2 transmitting circuit UM base metal film V1 plug V2, V3 via part

Claims (10)

A semiconductor substrate;
A first coil formed on the semiconductor substrate via a first inorganic insulating film;
A laminated insulating film formed on the semiconductor substrate so as to cover the first inorganic insulating film and the first coil;
A second coil formed on the laminated insulating film and disposed above the first coil;
A first pad formed on the laminated insulating film and disposed inside the second coil and having a polygonal shape in plan view;
A second pad formed on the laminated insulating film and disposed outside the second coil;
A first organic insulating film formed to cover the laminated insulating film, the second coil, a part of the first pad and a part of the second pad;
A semiconductor device comprising:
The first pad has a plurality of corners and a plurality of sides in a plan view,
Each of the plurality of corners of the first pad is an obtuse angle in plan view,
The plurality of sides of the first pad include a first side and a second side extending in a direction intersecting with an extending direction of the first side in plan view,
One end of the second coil is connected to the first side of the first pad via a first connection portion in plan view,
The other end of the second coil is connected to the second pad via a second connection portion in plan view,
The width of the first connection portion in the extending direction of the first side of the first pad gradually decreases from the first side toward the one end of the second coil in plan view.
The first connection portion is connected near the corner where the extending direction of the first side and the extending direction of the second side intersect rather than the center of the first side in plan view,
The first coil overlaps the second coil in plan view,
The semiconductor device, wherein the first coil and the second coil are magnetically coupled without being connected by a conductor. The semiconductor device according to claim 1,
The laminated insulating film comprises a second inorganic insulating film and a second organic insulating film on the second inorganic insulating film,
The second coil is formed on the second organic insulating film,
The semiconductor device, wherein the second organic insulating film is sandwiched between the first organic insulating film and the second inorganic insulating film in a cross-sectional view. The semiconductor device according to claim 2,
The second inorganic insulating film of the laminated insulating film includes a silicon oxide film, a silicon nitride film on the silicon oxide film, and the second organic insulating film on the silicon nitride film,
The semiconductor device, wherein the second organic insulating film is a resin film. The semiconductor device according to claim 1,
The width of the connection portion along the first side of the first connection portion and the first pad is larger than the width of the wiring of the second coil. The semiconductor device according to claim 3.
The planar shape of the first pad is a substantially octagon,
The semiconductor device in which the planar shape of the second coil is a substantially octagon. The semiconductor device according to claim 1,
The second pad has a polygonal shape having a plurality of corners and a plurality of sides in a plan view,
Each of the plurality of corners of the second pad is an obtuse angle in plan view,
The plurality of sides of the second pad include a third side and a fourth side extending in a direction intersecting with an extending direction of the third side in plan view,
The other end of the second coil is connected to the third side via the second connection portion in plan view,
The width of the second connection portion in the extending direction of the third side of the second pad gradually decreases from the third side toward the other end of the second coil in plan view.
The second connection portion is a semiconductor device connected in a plan view in the vicinity of an intersection between the extending direction of the third side and the extending direction of the fourth side rather than the center of the third side. The semiconductor device according to claim 4.
The laminated insulating film comprises a second inorganic insulating film and a second organic insulating film on the second inorganic insulating film,
The second coil is formed on the second organic insulating film,
The semiconductor device, wherein the second organic insulating film is sandwiched between the first organic insulating film and the second inorganic insulating film in a cross-sectional view. The semiconductor device according to claim 1,
The first organic insulating film is a polyimide film, and has a first opening from which the first pad is exposed and a second opening from which the second pad is exposed,
The exposed portion of the first pad of the first opening is connected to the semiconductor chip via a first bonding wire,
An exposed portion of the second pad of the second opening is connected to the semiconductor chip via a second bonding wire;
The semiconductor device, wherein the semiconductor substrate and the semiconductor chip are electrically insulated. The semiconductor device according to claim 8.
The side surface of the semiconductor substrate and the side surface of the semiconductor chip are arranged so as to face each other,
A plurality of first leads are arranged side by side on the side opposite to the side of the semiconductor substrate,
A plurality of second leads are arranged side by side on the side opposite to the side of the semiconductor chip,
Each of the first leads is connected to the semiconductor substrate via a plurality of first wires,
Each of the second leads is connected to the semiconductor chip via a plurality of second wires,
Each of the semiconductor substrate, the semiconductor chip, the first and second bonding wires, the plurality of first and second wires, a part of each of the plurality of first leads, and each of the plurality of second leads. The part is a semiconductor device sealed with resin. A semiconductor substrate;
A first coil formed on the semiconductor substrate via a first inorganic insulating film;
A laminated insulating film formed on the semiconductor substrate so as to cover the first inorganic insulating film and the first coil;
A second coil formed on the laminated insulating film and disposed above the first coil;
A first pad formed on the laminated insulating film and disposed inside the second coil and having a polygonal shape in plan view;
A second pad formed on the laminated insulating film and disposed outside the second coil;
A second insulating film formed to cover the laminated insulating film, the second coil, a part of the first pad and a part of the second pad;
A semiconductor device.

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