JPH07201855A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH07201855A
JPH07201855A JP5336434A JP33643493A JPH07201855A JP H07201855 A JPH07201855 A JP H07201855A JP 5336434 A JP5336434 A JP 5336434A JP 33643493 A JP33643493 A JP 33643493A JP H07201855 A JPH07201855 A JP H07201855A
Authority
JP
Japan
Prior art keywords
guard ring
conductive film
semiconductor chip
semiconductor device
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5336434A
Other languages
Japanese (ja)
Inventor
Akihiro Iwase
章弘 岩瀬
Eisaku Ito
栄作 伊藤
Shinji Nagai
真二 永井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP5336434A priority Critical patent/JPH07201855A/en
Publication of JPH07201855A publication Critical patent/JPH07201855A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To improve moisture proofness by reducing an external stress to generate a crack in a guard ring at the time of sealing a semiconductor chip by molding to improve the defect of characteristics due to the crack in a semiconductor device which has a elongated conductor film such as a guard ring used for improving, for instance, moisture proofness, in the region between the peripheral edge of a semiconductor chip and a wiring pad. CONSTITUTION:A guard ring 4 composed of a conductor film 3 provided in the region between the peripheral edge of a semiconductor chip 1 and a wiring pad 2 is constituted of a pattern which is bent in a zigzag form or curved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体基板の周辺部に細
長い導体膜を有する半導体装置に関し、例えば耐湿性向
上のために使用されるガードリングの形成技術に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an elongated conductor film on the periphery of a semiconductor substrate, and more particularly to a technique for forming a guard ring used for improving moisture resistance.

【0002】[0002]

【従来の技術】図3は従来例の説明図である。図におい
て、1は半導体チップ、2は配線パッド、3は導電膜、
4はガードリング、9は四隅部、10はスリットである。
2. Description of the Related Art FIG. 3 is an explanatory view of a conventional example. In the figure, 1 is a semiconductor chip, 2 is a wiring pad, 3 is a conductive film,
4 is a guard ring, 9 is four corners, and 10 is a slit.

【0003】従来、半導体チップ1をモールド樹脂で封
止した場合、図3(a)に示したような半導体チップ1
の周縁と配線パッド2間の領域に設けられた導電膜3か
らなる直線状のガードリング4のパターンでは、モール
ド樹脂による強い応力が特に半導体チップ1周縁の四隅
部9に大きく加わり、半導体チップ1の周縁に設けられ
たガードリング4の上、及び周辺でガードリング4の導
電膜3を覆った図示しないパッシベーション膜にクラッ
クが生ずることが知られている。
Conventionally, when the semiconductor chip 1 is sealed with a mold resin, the semiconductor chip 1 as shown in FIG.
In the pattern of the linear guard ring 4 formed of the conductive film 3 provided in the region between the peripheral edge of the semiconductor chip 1 and the wiring pad 2, a strong stress due to the molding resin is exerted particularly on the four corners 9 of the peripheral edge of the semiconductor chip 1, and It is known that cracks occur in the passivation film (not shown) that covers the conductive film 3 of the guard ring 4 on and around the guard ring 4 provided at the periphery of the guard ring 4.

【0004】そこで、特開平2−77132号公報で
は、図3(b)に示すように、ガードリング4に延在す
るリング方向に平行なスリット10を設けて、上記の欠点
の改良を行っている。
Therefore, in JP-A-2-77132, as shown in FIG. 3B, a slit 10 extending in the guard ring 4 and parallel to the ring direction is provided to improve the above-mentioned drawbacks. There is.

【0005】[0005]

【発明が解決しようとする課題】ところが、半導体装置
の微細化にともない、ガードリングの幅も非常に細くな
り、スリットを入れることにより配線幅はより細くなっ
て、目的とは逆にパッシベーション膜のクラックによる
ガードリングの断線を招くようになってきた。
However, with the miniaturization of semiconductor devices, the width of the guard ring has become very narrow, and the slits make the wiring width narrower. Contrary to the purpose, the passivation film The cracks have caused wire breaks in the guard ring.

【0006】本発明は、以上のような点を鑑み、モール
ド樹脂成形時のガードリング上のパッシベーション膜
の、外部応力によるクラック等に起因する特性不良の改
善や、耐湿性の向上を達成することができる半導体装置
を提供することを目的とする。
In view of the above points, the present invention achieves improvement of characteristic defects and improvement of moisture resistance of a passivation film on a guard ring at the time of molding resin molding due to cracks and the like due to external stress. It is an object of the present invention to provide a semiconductor device capable of achieving the above.

【0007】[0007]

【課題を解決するための手段】図1は本発明の原理説明
図である。図において、1は半導体チップ、2は配線パ
ッド、3は導電膜、4はガードリング、5は直線状パタ
ーン、6は屈曲部である。
FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, 1 is a semiconductor chip, 2 is a wiring pad, 3 is a conductive film, 4 is a guard ring, 5 is a linear pattern, and 6 is a bent portion.

【0008】上記問題点を解決するために、チップの周
縁に設けたガードリング4の直線部分を少なくするため
に直線状パターン5をより短くして、複数の屈曲部6を
設けると良い。
In order to solve the above-mentioned problems, it is advisable to shorten the linear pattern 5 and provide a plurality of bent portions 6 in order to reduce the linear portion of the guard ring 4 provided on the periphery of the chip.

【0009】即ち、本発明の目的は、図1に示すよう
に、半導体チップ1の周縁と配線パッド2間の領域に設
けられた導電膜3からなるガードリング4が、蛇行状に
屈曲、或いは湾曲したパターンからなることにより、ま
た、後述の実施例と図2で説明するように、前記ガード
リング4が複数層の導電膜3からなり、上層と下層の導
電膜3は層間絶縁膜7のスルーホール8を介して互いに
接続されてなることにより、更に、前記複数層の導電膜
3は少なくとも上層の導電膜3aが、下層の導電膜3bに覆
い被さるように積層してなることにより達成される。
That is, as shown in FIG. 1, the object of the present invention is that the guard ring 4 formed of the conductive film 3 provided in the region between the peripheral edge of the semiconductor chip 1 and the wiring pad 2 is bent in a meandering shape, or Due to the curved pattern, the guard ring 4 is composed of a plurality of conductive films 3 and the upper and lower conductive films 3 are composed of the interlayer insulating film 7 as will be described later in the embodiment and FIG. Since the conductive films 3 are connected to each other through the through holes 8, the conductive film 3 of the plurality of layers is further formed by stacking at least the conductive film 3a of the upper layer so as to cover the conductive film 3b of the lower layer. It

【0010】[0010]

【作用】本発明の手段によれば、上記ガードリングの導
電膜の直線状パターンを短くし、複数の屈曲部を設けて
いるので、外部応力を短い直線状パターンの部分に分割
し、大きな応力を分散させるとともに、複数の屈曲部を
設け、そのバネの原理を利用して、応力を吸収し、クラ
ックの発生を緩和する。
According to the means of the present invention, since the linear pattern of the conductive film of the guard ring is shortened and a plurality of bent portions are provided, the external stress is divided into the short linear pattern portions, and the large stress is increased. Is dispersed, and a plurality of bent portions are provided, and the principle of the spring is used to absorb stress and reduce the occurrence of cracks.

【0011】[0011]

【実施例】図2は本発明の一実施例の模式断面図であ
る。図において、1は半導体チップ、2は配線パッド、
3は導電膜、3aは上層の導電膜、3bは下層の導電膜、4
はガードリング、5は直線状パターン、6は屈曲部、7
は層間絶縁膜、8はスルーホール、9は四隅部、11はSi
基板である。
FIG. 2 is a schematic sectional view of an embodiment of the present invention. In the figure, 1 is a semiconductor chip, 2 is a wiring pad,
3 is a conductive film, 3a is an upper conductive film, 3b is a lower conductive film, 4
Is a guard ring, 5 is a linear pattern, 6 is a bent portion, and 7 is
Is an interlayer insulating film, 8 is a through hole, 9 is a four corner portion, 11 is Si
The substrate.

【0012】図2を用いて、本発明の一実施例について
説明する。図2(a)に示すように、ガードリング4に
ポリSi膜からなる上層の導電膜3a、Al膜からなる下層の
導電膜3bを使用し、50μm程度の間隔でSiO2膜からなる
層間絶縁膜7にスルーホール(導通窓)8を設けて上層
の導電膜3aと下層の導電膜3bとを接続させている。
An embodiment of the present invention will be described with reference to FIG. As shown in FIG. 2A, an upper layer conductive film 3a made of a poly-Si film and a lower conductive film 3b made of an Al film are used for the guard ring 4, and interlayer insulation made of a SiO 2 film is provided at intervals of about 50 μm. A through hole (conduction window) 8 is provided in the film 7 to connect the upper conductive film 3a and the lower conductive film 3b.

【0013】ガードリング4の直線状パターン5は出来
るだけ短くし、多くの屈曲部6を持たせる。屈曲部6の
内角は 135°としているが、この屈曲部6は多角形化
し、円周に近い形がより効果的である。
The linear pattern 5 of the guard ring 4 is made as short as possible and has many bent portions 6. The inner angle of the bent portion 6 is 135 °, but the bent portion 6 is polygonal, and a shape close to the circumference is more effective.

【0014】図2(b)は図2(a)のA−A’間の断
面図である。二層目の上層の導体膜3aは一層目の下層の
導体膜3bより外側に覆い被せてある。このような構造に
おいて、例えば、大きな応力がチップの四隅部9から加
わったとしても、ガードリング4のパターンは短い直線
状パターン5に分散され、且つ、a〜a”系列、及び、
c〜c”の系列はバネの作用をして、下層の導電膜3bを
被覆する図示しないパッシベーション膜のクラックや、
それによるガードリング4の断線を防止出来る。
FIG. 2B is a sectional view taken along the line AA 'in FIG. The upper-layer conductor film 3a of the second layer covers the outside of the lower-layer conductor film 3b of the first layer. In such a structure, for example, even if a large stress is applied from the four corners 9 of the chip, the pattern of the guard ring 4 is dispersed in the short linear pattern 5, and the a to a ″ series, and
The series of c to c ″ acts as a spring, and cracks in a passivation film (not shown) covering the lower conductive film 3b,
It is possible to prevent disconnection of the guard ring 4 due to it.

【0015】[0015]

【発明の効果】本発明によれば、スリットの形成が困難
な細いガードリングであっても、短い直線部と複数の屈
曲部を形成することにより、パッシベーション膜に加わ
る応力を緩和でき、ガードリングの断線率を低下させ、
半導体装置の外部応力による特性不良の改善、耐湿性の
向上を達成でき、半導体装置の信頼性の向上に著しく寄
与する。
According to the present invention, even with a thin guard ring in which it is difficult to form a slit, the stress applied to the passivation film can be relieved by forming a short straight portion and a plurality of bent portions, so that the guard ring can be relaxed. Decrease the disconnection rate of
It is possible to improve the characteristic failure due to the external stress of the semiconductor device and improve the moisture resistance, which remarkably contributes to the improvement of the reliability of the semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.

【図2】 本発明の一実施例の説明図FIG. 2 is an explanatory diagram of an embodiment of the present invention.

【図3】 従来例の説明図FIG. 3 is an explanatory diagram of a conventional example.

【符号の説明】 1 半導体チップ 2 配線パッド 3 導電膜 3a 上層の導電膜 3b 下層の導電膜 4 ガードリング 5 直線状パターン 6 屈曲部 7 層間絶縁膜 8 スルーホール 11 Si基板[Explanation of symbols] 1 semiconductor chip 2 wiring pad 3 conductive film 3a upper conductive film 3b lower conductive film 4 guard ring 5 linear pattern 6 bent portion 7 interlayer insulating film 8 through hole 11 Si substrate

───────────────────────────────────────────────────── フロントページの続き (72)発明者 永井 真二 愛知県春日井市高蔵寺町二丁目1844番2 富士通ヴィエルエスアイ株式会社内 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Shinji Nagai 1844-2, Kozoji-cho, Kasugai-shi, Aichi Prefecture

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップ(1) の周縁と配線パッド
(2) 間の領域に設けられた導電膜(3) からなるガードリ
ング(4) が、蛇行状に屈曲、或いは湾曲したパターンか
らなることを特徴とする半導体装置。
1. A peripheral edge of a semiconductor chip (1) and a wiring pad
A semiconductor device characterized in that a guard ring (4) formed of a conductive film (3) provided in a region between (2) has a meandering curved or curved pattern.
【請求項2】 前記ガードリング(4) が複数層の導電膜
(3) からなり、該導電膜(3) は層間絶縁膜(7) のスルー
ホール(8) を介して互いに接続されてなることを特徴と
する請求項1記載の半導体装置。
2. The conductive film in which the guard ring (4) has a plurality of layers.
2. The semiconductor device according to claim 1, wherein the conductive film (3) is formed of (3) and is connected to each other through the through hole (8) of the interlayer insulating film (7).
【請求項3】 前記複数層の導電膜(3) は少なくとも上
層の導電膜(3a) が下層の導電膜(3b)に覆い被さるよう
に積層してなることを特徴とする請求項1または2記載
の半導体装置。
3. The conductive film (3) of a plurality of layers is laminated so that at least the conductive film (3a) of the upper layer covers the conductive film (3b) of the lower layer. The semiconductor device described.
JP5336434A 1993-12-28 1993-12-28 Semiconductor device Withdrawn JPH07201855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5336434A JPH07201855A (en) 1993-12-28 1993-12-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5336434A JPH07201855A (en) 1993-12-28 1993-12-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH07201855A true JPH07201855A (en) 1995-08-04

Family

ID=18299096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5336434A Withdrawn JPH07201855A (en) 1993-12-28 1993-12-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH07201855A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0797253A2 (en) * 1996-03-19 1997-09-24 Matsushita Electric Industrial Co., Ltd Chip carrier and semiconductor device using the same
WO1997040528A1 (en) * 1996-04-19 1997-10-30 Matsushita Electronics Corporation Semiconductor device
JP2005175204A (en) * 2003-12-11 2005-06-30 Fujitsu Ltd Semiconductor device and its manufacturing method
US6921959B2 (en) * 2003-09-10 2005-07-26 Kabushiki Kaisha Toshiba Semiconductor device
US6949775B1 (en) 1999-03-19 2005-09-27 Fujitsu Limited Semiconductor device having a guard ring
KR100704584B1 (en) * 2005-08-22 2007-04-06 후지쯔 가부시끼가이샤 Semiconductor device with multiple wiring layers and moisture-protective ring
KR100781850B1 (en) * 2005-07-20 2007-12-03 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same
KR100823043B1 (en) * 2000-06-27 2008-04-17 에이저 시스템즈 가디언 코포레이션 An integrated circuit and a method of manufacturing an integrated circuit
US7723753B2 (en) 2007-03-13 2010-05-25 Renesas Technology Corp. Semiconductor device and manufacturing method of the same
KR100983457B1 (en) * 2000-06-27 2010-09-27 에이저 시스템즈 가디언 코포레이션 A method of testing an integrated circuit
US8841784B2 (en) 2011-08-10 2014-09-23 Renesas Electronics Corporation Semiconductor apparatus and substrate
EP2863431A3 (en) * 2002-07-31 2015-07-22 Socionext Inc. Semiconductor device

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0797253A3 (en) * 1996-03-19 1999-04-14 Matsushita Electric Industrial Co., Ltd Chip carrier and semiconductor device using the same
EP0797253A2 (en) * 1996-03-19 1997-09-24 Matsushita Electric Industrial Co., Ltd Chip carrier and semiconductor device using the same
WO1997040528A1 (en) * 1996-04-19 1997-10-30 Matsushita Electronics Corporation Semiconductor device
US6081036A (en) * 1996-04-19 2000-06-27 Matsushita Electronics Corp. Semiconductor device
KR100299338B1 (en) * 1996-04-19 2001-10-19 마츠시타 덴끼 산교 가부시키가이샤 Semiconductor device
US6949775B1 (en) 1999-03-19 2005-09-27 Fujitsu Limited Semiconductor device having a guard ring
KR100617276B1 (en) * 1999-03-19 2006-08-30 후지쯔 가부시끼가이샤 Semiconductor device
US7169699B2 (en) 1999-03-19 2007-01-30 Fujitsu Limited Semiconductor device having a guard ring
KR100823043B1 (en) * 2000-06-27 2008-04-17 에이저 시스템즈 가디언 코포레이션 An integrated circuit and a method of manufacturing an integrated circuit
KR100983457B1 (en) * 2000-06-27 2010-09-27 에이저 시스템즈 가디언 코포레이션 A method of testing an integrated circuit
US9406611B2 (en) 2002-07-31 2016-08-02 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9412697B2 (en) 2002-07-31 2016-08-09 Socionext Inc. Semiconductor device having groove-shaped via-hole
US10403543B2 (en) 2002-07-31 2019-09-03 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9972531B2 (en) 2002-07-31 2018-05-15 Socionext Inc. Method of manufacturing a semiconductor device having groove-shaped via-hole
EP3208846A1 (en) * 2002-07-31 2017-08-23 Socionext Inc. Semiconductor device
US9502353B2 (en) 2002-07-31 2016-11-22 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9412698B2 (en) 2002-07-31 2016-08-09 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9412696B2 (en) 2002-07-31 2016-08-09 Socionext Inc. Semiconductor device having groove-shaped via-hole
EP2863431A3 (en) * 2002-07-31 2015-07-22 Socionext Inc. Semiconductor device
EP2863430A3 (en) * 2002-07-31 2015-07-22 Socionext Inc. Semiconductor device
US9412699B2 (en) 2002-07-31 2016-08-09 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9224689B2 (en) 2002-07-31 2015-12-29 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9224690B2 (en) 2002-07-31 2015-12-29 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9406613B2 (en) 2002-07-31 2016-08-02 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9406612B2 (en) 2002-07-31 2016-08-02 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9406610B2 (en) 2002-07-31 2016-08-02 Socionext Inc. Semiconductor device having groove-shaped via-hole
US6921959B2 (en) * 2003-09-10 2005-07-26 Kabushiki Kaisha Toshiba Semiconductor device
JP2005175204A (en) * 2003-12-11 2005-06-30 Fujitsu Ltd Semiconductor device and its manufacturing method
JP4659355B2 (en) * 2003-12-11 2011-03-30 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
KR100781850B1 (en) * 2005-07-20 2007-12-03 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same
US8013447B2 (en) 2005-07-20 2011-09-06 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same
KR100704584B1 (en) * 2005-08-22 2007-04-06 후지쯔 가부시끼가이샤 Semiconductor device with multiple wiring layers and moisture-protective ring
US7723753B2 (en) 2007-03-13 2010-05-25 Renesas Technology Corp. Semiconductor device and manufacturing method of the same
US9190363B2 (en) 2011-08-10 2015-11-17 Renesas Electronics Corporation Semiconductor apparatus and substrate
US8841784B2 (en) 2011-08-10 2014-09-23 Renesas Electronics Corporation Semiconductor apparatus and substrate

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Effective date: 20010306